298
Development Tools User’s Guide
Intel
®
IXP2400/IXP2800 Network Processors
Intel XScale® Core Memory Bus Functional Model
where:
addr
:
32-bit Intel XScale
address,
intVector
:
0..31 in correspond to the interrupt vector defined in the EAS (chapter 2,
section 2.21),
return
value:
1 if the address/interrupt-vector is reserved, otherwise it returns 0
C.1.6
Additional CMB_IO API
The CMB_IO API also provides several routines that emulate the Intel XScale
load, store, and
swap bus operations. The
cmbRead32
and
cmbWrite32
routines are similar to the simRead32 and
simWrite32 routines except that the cmbXXXX routines return a request-id and the operation is
completed when
cmbSetCb
callback occurs, after the appropriate simulation delay. If the operation
was a read then
cmbSetCb
will also return data.
These two sets of API functions are one-to-one mapping from one set to the other. The purpose of
providing two sets of API is to provide the basic functions that supports software group to develop
code for Intel XScale
related library file, in which all the accesses from the Intel XScale
are 32-
bit, and to support for a more generic use. i.e. A more comprehensive transaction types, such as
long-burst transactions, atomic transactions, etc. are covered.
C.1.7
cmbRead32 / cmbWrite32
These two functions provide the interface for issuing a Intel XScale
load/store of single long-
word (LW).
If the Intel XScale
Gasket command FIFO is full then the
CMB_ERROR_QUEUE_FULL
code
is returned.
If no callback is registered then the
CMB_ERROR_NO_CB_REGISTER
code is returned.
int
cmbRead32
(char
*chip_name
,
unsigned int
addr
)
int
cmbWrite32
(char
*chip_name
,
unsigned int
addr
,
unsigned int
data
)
where:
chip_name
:
name of the instantiated IXP2800/IXP2400 instance,
addr
:
32-bit Intel XScale
address,
data
: write
data,
return
value:
request-id (positive value, 0-n), or error code (negative value). Such as:
-3: no callback function registered
CMB_ERROR_NO_CB_REGISTER
,
-2: request queue is full
CMB_ERROR_QUEUE_FULL
