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Development Tools User’s Guide
Intel
®
IXP2400/IXP2800 Network Processors
Transactor
Deletes the entire instantiated simulation model and all associated model states. Memory for
all simulation states is freed by this command. A new model maybe instantiated (via the
inst
command) and initialized (via the
init
command) after executing this command.
8.3.35
sim_reset
Format:
sim_reset
Definition:
Resets the state of the model to the point just after the model was first initialized. Therefore, all
states predefined by the logic model are reset and all user-defined states are deleted. User-
defined states include all int's, strings, vectors, watches, breakpoints, and functions. All open
trace files are closed. Previously loaded foreign models remain in effect.
8.3.36
time
Format:
time
Definition:
Prints the current wallclock time.
Example:
>>> time
time: 14:20:30 date: 05/16/02
8.3.37
trace
Format:
trace |[/dino|/vcd|vcd+]|file_name name_list
Definition:
Opens a trace file to log simulation data over time for subsequent use by a waveform editor.
/dino
specifies the binary template format for “dinotrace”.
/vcd
Specifies the ASCII Verilog trace format.
/vcd+
specifies the Verilog binary trace format.
file_name
Specifies the name of the file that contains the trace logging data.
name_list
A list of simulation states (separated by blanks). If “@” is prepended to
a name, the name then refers to a file from which additional names will
be derived.
Wildcards
The wildcard character, “*”, may be used as a shorthand method of
specifying one or more state names.
Arrays
If a signal is an array, an index range specification must be applied to
address particular elements within the array.