IDEC FC4A-C10R2, User Manual

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9: M
OVE
I
NSTRUCTIONS
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Repeat Operation in the Indirect Bit Move Instructions
Repeat Bit Operands (Source and Destination)
If a repeat operation is designated for bit operands such as input, output, internal relay, or shift register, bit operands as
many as the repeat cycles are moved.
Repeat Word Operands (Source and Destination)
If a repeat operation is designated for word operands such as data register, bit statuses as many as the repeat cycles in the
designated data register are moved.
S1 –
D10
I0
IBMV S2
5
D1 –
D20
SOTU
REP D2
12
D10
+
5
→
D20 + 12
Bit 15
Bit 5
Bit 12
Since source operand S1 is a data register and the value of
source operand S2 is 5, the source data is bit 5 of data register
D10 designated by source operand S1.
Since destination operand D1 is a data register and the value of
source operand D2 is 12, the destination is bit 12 of data regis-
ter D20 designated by destination operand D1.
As a result, when input I0 is on, the ON/OFF status of data regis-
ter D10 bit 5 is moved to data register D20 bit 12.
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D10
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D20
S1 R
M10
I1
IBMV S2
5
D1 R
Q30
SOTU
REP
3
D2
9
M10
+
5
→
Q30 + 9
Repeat = 3
M27 M10 M17 M20 M15
5th from M10
Q47 Q30 Q37 Q41
9th from Q30
Q44
Since source operand S1 is internal relay M10 and the value of
source operand S2 is 5, the source data is 3 internal relays star t-
ing with M15.
Since destination operand D1 is output Q30 and the value of desti-
nation operand D2 is 9, the destination is 3 outputs star ting with
Q41.
As a result, when input I1 is on, the ON/OFF statuses of internal
relays M15 through M17 are moved to outputs Q41 through Q43.
Q43
S1 R
D10
I2
IBMV S2
5
D1 R
D20
SOTU
REP
3
D2
12
D10
+
5
→
D20 + 12
Repeat = 3
Since source operand S1 is data register D10 and the value of
source operand S2 is 5, the source data is 3 bits star ting with bit
5 of data register D10.
Since destination operand D1 is data register D20 and the value
of destination operand D2 is 12, the destination is 3 bits star ting
with bit 12 of data register D20.
As a result, when input I2 is on, the ON/OFF statuses of data reg-
ister D10 bits 5 through 7 are moved to data register D20 bits 12
through 14.
Bit 15
Bit 5
Bit 12
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D10
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D20