IDEC FC4A-C10R2, User Manual

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9: M
OVE
I
NSTRUCTIONS
9-4 « FC4A M
ICRO
S
MART
U
SER
’
S
M
ANUAL
»
MOVN (Move Not)
Applicable CPU Modules
Valid Operands
For the valid operand number range, see pages 6-1 and 6-2.
▲
Internal relays M0 through M1277 can be designated as D1. Special internal relays cannot be designated as D1.
When T (timer) or C (counter) is used as S1, the timer/counter current value is read out. When T (timer) or C (counter) is
used as D1, the data is written in as a preset value which can be 0 through 65535.
Valid Data Types
Examples: MOVN
FC4A-C10R2/C FC4A-C16R2/C FC4A-C24R2/C FC4A-D20K3/S3 FC4A-D20RK1/RS1 & FC4A-D40K3/S3
X X X X X
Operand Function I Q M R T C D Constant Repeat
S1 (Source 1) First operand number to move X X X X X X X X 1-99
D1 (Destination 1) First operand number to move to — X
▲
X X X X — 1-99
W (word) I (integer)
X X
S1 NOT
→
D1
When input is on, 16-bit data from operand designated by S1 is inver ted
bit by bit and moved to operand designated by D1.
REP
**
S1(R)
*****
D1(R)
*****
MOVN(*)
When a bit operand such as I (input), Q (output), M (internal relay), or R (shift register) is
designated as the source or destination, 16 points are used. When repeat is designated for a
bit operand, the quantity of operand bits increases in 16-point increments.
When a word operand such as T (timer), C (counter), or D (data register) is designated as the
source or destination, 1 point is used. When repeat is designated for a word operand, the
quantity of operand words increases in 1-point increments.
M10 NOT
→
M50
When input I0 is on, the 16 internal relays star ting with M10 designated
by source operand S1 are inver ted bit by bit and moved to 16 internal
relays star ting with M50 designated by destination operand D1.
M10 through M17, M20 through M27 NOT M50 through M57, M60 through M67
The ON/OFF statuses of the 16 internal relays M10
through M17 and M20 through M27 are inver ted
and moved to 16 internal relays M50 through M57
and M60 through M67. M50 is the LSB (least signif-
icant bit), and M67 is the MSB (most significant bit).
Before inversion
0 1 0 0 1 0 0 0 0 1 0 0 1 0 1 1
MSB LSB
S1
After inversion
1 0 1 1 0 1 1 1 1 0 1 1 0 1 0 0
MSB LSB
D1
I0
REP S1 –
M10 D1 –
M50 MOVN(W)
(M27-M10):
(M67-M50):
810 NOT
→
D2
When input I1 is on, decimal constant 810 designated by source operand
S1 is conver ted into 16-bit binar y data, and the ON/OFF statuses of the
16 bits are inver ted and moved to data register D2 designated by destina-
tion operand D1.
D1
D0
64725 D2 810
Before inversion (810):
0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 0
MSB LSB
S1
After inversion (64725): 1 1 0 1 1 1 1 0 1 0 0 1 1 1 0 1
MSB LSB
D1
I1
REP S1 –
810
D1 –
D2
MOVN(W)
D30 NOT
→
D20
When input I2 is on, the data in data register
D30 designated by S1 is inver ted bit by bit and
moved to data register D20 designated by D1.
64605
D20
930 D30
I2
REP S1 –
D30
D1 –
D20
MOVN(W)