IDEC FC4A-C10R2, User Manual

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Reverse Shift Register (SFRN)
For reverse shifting, use the SFRN instruction. When SFRN instructions are programmed, two addresses are always
required. The SFRN instructions are entered, followed by a shift register number selected from appropriate operand num-
bers. The shift register number corresponds to the lowest bit number in a string. The number of bits is the second required
address after the SFRN instructions.
The SFRN instruction requires three inputs. The reverse shift register circuit must be programmed in the following order:
reset input, pulse input, data input, and the SFRN instruction, followed by the last bit and the number of bits.
Structural Diagram
I2
I0
R20
Reset
Data
I1
Pulse
R21 R22 R23
Shift Direction
Last Bit: R20 # of Bits: 7
R24 R25 R26
Note: Output is initiated only for those bits highlighted in bold print.
Note: When power is turned off, the statuses of all shift register bits are normally cleared. It is also possible to maintain
the statuses of shift register bits by using the Function Area Settings as required. See page 5-4.
•
The last bit status output can be programmed directly after the SFRN instruction. In this example, the status of bit R20
is read to output Q0.
•
Each bit can be loaded using the LOD R# instructions.
•
For details of reset, pulse, and data inputs, see page 7-18.
Ladder Diagram
I0
I1
SFRN R20
7
I2
Reset
Pulse
Data
R21
Last Bit
# of Bits
R23
R25
Instruction Data
LOD
LOD
LOD
SFRN
OUT
LOD
OUT
LOD
OUT
LOD
OUT
I0
I1
I2
R20
7
Q0
R21
Q1
R23
Q2
R25
Q3
Program List
Q0
Q1
Q3
Q2
CPU Type All-in-One 10-I/O Others
Last Bit R0 to R63 R0 to R127
# of Bits 1 to 64 1 to 128
Caution
•
For restrictions on ladder programming of shift register instructions, see page 29-22.