Hitachi H8/3044 Hardware Manual Download Page 701

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Figure 21-7 Basic Bus Cycle: Two-State Access

CYC

AS1

ASD

ACC3

ASD

ACC3

ACC1

ASD

AS1

WDD

WDS1

WSW1

PCH

RDH

RDS

PCH

WDH

to A

(read)

to D

(read)

HWR

LWR

(write)

to D

(write)

cyc

693

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Summary of Contents for H8/3044

Page 1: ...tachi Single Chip Microcomputer H8 3048 Series H8 3048 HD64F3048 HD6473048 HD6433048 H8 3047 HD6433047 H8 3045 HD6433045 H8 3044 HD6433044 Hardware Manual ADE 602 073B www DataSheet4U com 查询64F3048F16供应商 ...

Page 2: ...d in standby and the frequency of the system clock supplied to the chip can be divided down under software control The address space is divided into eight areas The data bus width and access cycle length can be selected independently in each area simplifying the connection of different types of memory Seven operating modes modes 1 to 7 are provided offering a choice of data bus width and address s...

Page 3: ... General Register Data Formats 23 2 5 2 Memory Data Formats 25 2 6 Instruction Set 26 2 6 1 Instruction Set Overview 26 2 6 2 Instructions and Addressing Modes 27 2 6 3 Tables of Instructions Classified by Function 28 2 6 4 Basic Instruction Formats 38 2 6 5 Notes on Use of Bit Manipulation Instructions 39 2 7 Addressing Modes and Effective Address Calculation 39 2 7 1 Addressing Modes 39 2 7 2 Ef...

Page 4: ...3 Mode 3 60 3 4 4 Mode 4 60 3 4 5 Mode 5 60 3 4 6 Mode 6 60 3 4 7 Mode 7 61 3 5 Pin Functions in Each Operating Mode 61 3 6 Memory Map in Each Operating Mode 61 Section 4 Exception Handling 71 4 1 Overview 71 4 1 1 Exception Handling Types and Priority 71 4 1 2 Exception Handling Operation 71 4 1 3 Exception Vector Table 72 4 2 Reset 73 4 2 1 Overview 73 4 2 2 Reset Sequence 73 4 2 3 Interrupts af...

Page 5: ...rupt Disabling Instruction 107 5 5 2 Instructions that Inhibit Interrupts 108 5 5 3 Interrupts during EEPMOV Instruction Execution 108 5 5 4 Notes on External Interrup to during Use 108 Section 6 Bus Controller 111 6 1 Overview 111 6 1 1 Features 111 6 1 2 Block Diagram 112 6 1 3 Input Output Pins 113 6 1 4 Register Configuration 113 6 2 Register Descriptions 114 6 2 1 Bus Width Control Register A...

Page 6: ...Timer Counter RTCNT 155 7 2 4 Refresh Time Constant Register RTCOR 155 7 3 Operation 156 7 3 1 Overview 156 7 3 2 DRAM Refresh Control 157 7 3 3 Pseudo Static RAM Refresh Control 172 7 3 4 Interval Timing 177 7 4 Interrupt Source 183 7 5 Usage Notes 183 Section 8 DMA Controller 185 8 1 Overview 185 8 1 1 Features 185 8 1 2 Block Diagram 186 8 1 3 Functional Overview 187 8 1 4 Input Output Pins 188...

Page 7: ...8 4 14 DMAC States in Reset State Standby Modes and Sleep Mode 236 8 5 Interrupts 237 8 6 Usage Notes 238 8 6 1 Note on Word Data Transfer 238 8 6 2 DMAC Self Access 238 8 6 3 Longword Access to Memory Address Registers 238 8 6 4 Note on Full Address Mode Setup 238 8 6 5 Note on Activating DMAC by Internal Interrupts 239 8 6 6 NMI Interrupts and Block Transfer Mode 240 8 6 7 Memory and I O Address...

Page 8: ...in Functions 279 9 12 Port B 284 9 12 1 Overview 284 9 12 2 Register Descriptions 286 9 12 3 Pin Functions 288 Section 10 16 Bit Integrated Timer Unit ITU 295 10 1 Overview 295 10 1 1 Features 295 10 1 2 Block Diagrams 298 10 1 3 Input Output Pins 303 10 1 4 Register Configuration 304 10 2 Register Descriptions 307 10 2 1 Timer Start Register TSTR 307 10 2 2 Timer Synchro Register TSNC 308 10 2 3 ...

Page 9: ...pts 376 10 5 1 Setting of Status Flags 376 10 5 2 Clearing of Status Flags 378 10 5 3 Interrupt Sources and DMA Controller Activation 379 10 6 Usage Notes 380 Section 11 Programmable Timing Pattern Controller 395 11 1 Overview 395 11 1 1 Features 395 11 1 2 Block Diagram 396 11 1 3 TPC Pins 397 11 1 4 Registers 398 11 2 Register Descriptions 399 11 2 1 Port A Data Direction Register PADDR 399 11 2...

Page 10: ... 425 12 2 3 Reset Control Status Register RSTCSR 427 12 2 4 Notes on Register Access 429 12 3 Operation 431 12 3 1 Watchdog Timer Operation 431 12 3 2 Interval Timer Operation 432 12 3 3 Timing of Setting of Overflow Flag OVF 433 12 3 4 Timing of Setting of Watchdog Timer Reset Bit WRST 434 12 4 Interrupts 435 12 5 Usage Notes 435 Section 13 Serial Communication Interface 437 13 1 Overview 437 13 ...

Page 11: ...ions 500 14 2 1 Smart Card Mode Register SCMR 500 14 2 2 Serial Status Register SSR 501 14 2 3 Serial Mode Register SMR 503 14 2 4 Serial Control Register SCR 504 14 3 Operation 505 14 3 1 Overview 505 14 3 2 Pin Connections 505 14 3 3 Data Format 506 14 3 4 Register Settings 508 14 3 5 Clock 510 14 3 6 Transmitting and Receiving Data 512 14 4 Usage Notes 519 Section 15 A D Converter 523 15 1 Over...

Page 12: ...0 1 547 16 2 2 D A Control Register DACR 547 16 2 3 D A Standby Control Register DASTCR 549 16 3 Operation 550 16 4 D A Output Control 551 16 5 Usage Notes 551 Section 17 RAM 553 17 1 Overview 553 17 1 1 Block Diagram 553 17 1 2 Register Configuration 554 17 2 System Control Register SYSCR 555 17 3 Operation 556 Section 18 ROM 557 18 1 Overview 557 18 1 1 Block Diagram 558 18 2 PROM Mode 559 18 2 ...

Page 13: ...590 18 7 3 Programming Flowchart and Sample Program 591 18 7 4 Erase Mode 593 18 7 5 Erase Verify Mode 594 18 7 6 Erasing Flowchart and Sample Program 595 18 7 7 Prewrite Verify Mode 607 18 7 8 Protect Modes 607 18 7 9 NMI Input Masking 610 18 8 Flash Memory Emulation by RAM 611 18 9 PROM Mode 613 18 9 1 PROM Mode Setting 613 18 9 2 Socket Adapter and Memory Map 614 18 9 3 Operation in PROM Mode 6...

Page 14: ...by Mode 651 20 5 2 Exit from Hardware Standby Mode 651 20 5 3 Timing for Hardware Standby Mode 651 20 6 Module Standby Function 652 20 6 1 Module Standby Timing 652 20 6 2 Read Write in Module Standby 652 20 6 3 Usage Notes 652 20 7 System Clock Output Disabling Function 653 Section 21 Electrical Characteristics 649 21 1 Absolute Maximum Ratings 649 21 2 Electrical Characteristics of Masked ROM an...

Page 15: ...ction 738 Appendix C I O Port Block Diagrams 818 C 1 Port 1 Block Diagram 818 C 2 Port 2 Block Diagram 819 C 3 Port 3 Block Diagram 820 C 4 Port 4 Block Diagram 821 C 5 Port 5 Block Diagram 822 C 6 Port 6 Block Diagrams 823 C 7 Port 7 Block Diagrams 827 C 8 Port 8 Block Diagrams 828 C 9 Port 9 Block Diagrams 831 C 10 Port A Block Diagrams 835 C 11 Port B Block Diagrams 839 Appendix D Pin States 84...

Page 16: ...er and other facilities The four members of the H8 3048 Series are the H8 3048 the H8 3047 H8 3045 and the H8 3044 The H8 3048 has 128 kbytes of ROM and 4 kbytes of RAM The H8 3047 has 96 kbytes of ROM and 4 kbytes of RAM The H8 3045 has 64 kbytes of ROM and 2 kbytes of RAM The H8 3044 has 32 kbytes of ROM and 2 kbytes of RAM Seven MCU operating modes offer a choice of data bus width and address s...

Page 17: ...bits 16 bits Signed and unsigned divide instructions 16 bits 8 bits 32 bits 16 bits Bit accumulator function Bit manipulation instructions with register indirect specification of bit positions Memory H8 3048 ROM 128 kbytes RAM 4 kbytes H8 3047 ROM 96 kbytes RAM 4 kbytes H8 3045 ROM 64 kbytes RAM 2 kbytes H8 3044 ROM 32 kbytes RAM 2 kbytes Interrupt Seven external interrupt pins NMI IRQ0 to IRQ5 co...

Page 18: ...U pulse inputs 16 bit timer counter channels 0 to 4 Two multiplexed output compare input capture pins channels 0 to 4 Operation can be synchronized channels 0 to 4 PWM mode available channels 0 to 4 Phase counting mode available channel 2 Buffering available channels 3 and 4 Reset synchronized PWM mode available channels 3 and 4 Complementary PWM mode available channels 3 and 4 DMAC can be activat...

Page 19: ... 8 bits 16 bits Mode 7 1 Mbyte On chip ROM is disabled in modes 1 to 4 Power down Sleep mode state Software standby mode Hardware standby mode Module standby function Programmable system clock frequency division Other features On chip clock pulse generator Product lineup Model 5 V Model 3 V Package ROM HD64F3048TF HD64F3048VTF 100 pin TQFP TFP 100B Flash memory HD64F3048F HD64F3048VF 100 pin QFP F...

Page 20: ...3 2 1 0 1 0 PB TP DREQ ADTRG PB 6 TP 14 DREQ 0 CS 7 PB TP TOCXB PB TP TOCXA PB TP TIOCB PB TP TIOCA PB TP TIOCB PB TP TIOCA 15 1 7 4 4 4 4 3 3 5 4 13 12 3 2 11 10 1 0 9 8 Port 8 P8 CS P8 CS IRQ P8 CS IRQ P8 CS IRQ P8 RFSH IRQ 4 0 3 2 1 0 1 2 3 3 2 1 0 MD MD MD EXTAL XTAL ø STBY RES V RESO NMI 2 1 0 H8 300H CPU Clock pulse generator Interrupt controller ROM masked ROM PROM or flash memory DMA contr...

Page 21: ... 3 2 1 0 7 6 PA TP TIOCB A PA TP TIOCA A CS 4 PA TP TIOCB A CS 5 PA TP TIOCA A CS 6 PA TP TIOCB TCLKD PA TP TIOCA TCLKC PA TP TEND TCLKB PA TP TEND TCLKA V P8 CS P8 CS IRQ P8 CS IRQ P8 CS IRQ P8 RFSH IRQ 7 6 5 4 3 2 1 0 AV P7 AN DA P7 AN DA P7 AN P7 AN P7 AN P7 AN P7 AN P7 AN V AV 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 2 3 1 0 3 2 1 7 6 5 4 3 2 1 0 D P4 D P3 D P3 D P3 D P3 D P3 D P3 D P3 D ...

Page 22: ...G RESO VSS P90 TxD0 P91 TxD1 P92 RxD0 P93 RxD1 P94 SCK0 IRQ4 P95 SCK1 IRQ5 P40 D0 1 P41 D1 1 P42 D2 1 P43 D3 1 VSS P44 D4 1 P45 D5 1 P46 D6 1 P47 D7 1 D8 D9 D10 D11 D12 D13 D14 VCC PB0 TP8 TIOCA3 PB1 TP9 TIOCB3 PB2 TP10 TIOCA4 PB3 TP11 TIOCB4 PB4 TP12 TOCXA4 PB5 TP13 TOCXB4 PB6 TP14 DREQ0 CS7 PB7 TP15 DREQ1 ADTRG RESO VSS P90 TxD0 P91 TxD1 P92 RxD0 P93 RxD1 P94 SCK0 IRQ4 P95 SCK1 IRQ5 P40 D0 2 P41...

Page 23: ... A12 A13 A14 A15 A16 A17 A18 A19 VSS P60 WAIT P61 BREQ P62 BACK ø STBY RES NMI VSS EXTAL XTAL VCC AS RD D15 VCC A0 A1 A2 A3 A4 A5 A6 A7 VSS A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 VSS P60 WAIT P61 BREQ P62 BACK ø STBY RES NMI VSS EXTAL XTAL VCC AS RD D15 VCC P10 A0 P11 A1 P12 A2 P13 A3 P14 A4 P15 A5 P16 A6 P17 A7 VSS P20 A8 P21 A9 P22 A10 P23 A11 P24 A12 P25 A13 P26 A14 P27 A15 P50 A16 P51 A...

Page 24: ...A6 TP6 TIOCA2 CS4 PA7 TP7 TIOCB2 HWR LWR MD0 MD1 MD2 AVCC VREF P70 AN0 P71 AN1 P72 AN2 P73 AN3 P74 AN4 P75 AN5 P76 AN6 DA0 P77 AN7 DA1 AVSS P80 RFSH IRQ0 P81 CS3 IRQ1 P82 CS2 IRQ2 P83 CS1 IRQ3 P84 CS0 VSS PA0 TP0 TEND0 TCLKA PA1 TP1 TEND1 TCLKB PA2 TP2 TIOCA0 TCLKC PA3 TP3 TIOCB0 TCLKD PA4 TP4 TIOCA1 CS6 PA5 TP5 TIOCB1 CS5 PA6 TP6 TIOCA2 CS4 A20 HWR LWR MD0 MD1 MD2 AVCC VREF P70 AN0 P71 AN1 P72 AN...

Page 25: ...sonator and external clock input see section 19 Clock Pulse Generator EXTAL 66 Input For connection to a crystal resonator or input of an external clock signal For examples of crystal resonator and external clock input see section 19 Clock Pulse Generator ø 61 Output System clock Supplies the system clock to external devices Operating MD2 to MD0 75 to 73 Input Mode 2 to mode 0 For setting the oper...

Page 26: ...equest 5 to 0 Maskable interrupt IRQ0 90 to 87 request pins Address bus A23 to A0 97 to 100 Output Address bus Outputs address signals 56 to 45 43 to 36 Data bus D15 to D0 34 to 23 Input Data bus Bidirectional data bus 21 to 18 output Bus control CS7 to CS0 8 97 to 99 Output Chip select Select signals for areas 7 to 0 88 to 91 AS 69 Output Address strobe Goes low to indicate valid address output o...

Page 27: ...ite enable signal for DRAM connected to area 3 used with 2WE DRAM Lower column address strobe LCAS Column address strobe signal for DRAM connected to area 3 used with 2CAS DRAM DREQ1 9 8 Input DMA request 1 and 0 DMAC activation DREQ0 requests TEND1 94 93 Output Transfer end 1 and 0 These signals indicate TEND0 that the DMAC has ended a data transfer TCLKD to 96 to 93 Input Clock input D to A Exte...

Page 28: ... when not using the A D and D A converters AVSS 86 Input Ground pin for the A D and D A converters Connect to system ground 0 V VREF 77 Input Reference voltage input pin for the A D and D A converters Connect to the system power supply 5 V when not using the A D and D A converters I O ports P17 to P10 43 to 36 Input Port 1 Eight input output pins The direction of output each pin can be selected in...

Page 29: ...input pins P84 to P80 91 to 87 Input Port 8 Five input output pins The direction of output each pin can be selected in the port 8 data direction register P8DDR P95 to P90 17 to 12 Input Port 9 Six input output pins The direction of output each pin can be selected in the port 9 data direction register P9DDR PA7 to PA0 100 to 93 Input Port A Eight input output pins The direction of output each pin c...

Page 30: ...er architecture Sixteen 16 bit general registers also usable as sixteen 8 bit registers or eight 32 bit registers Sixty two basic instructions 8 16 32 bit data transfer and arithmetic and logic instructions Multiply and divide instructions Powerful bit manipulation instructions Eight addressing modes Register direct Rn Register indirect ERn Register indirect with displacement d 16 ERn or d 24 ERn ...

Page 31: ... 3048 Series Advanced mode Low power mode Transition to power down state by SLEEP instruction 2 1 2 Differences from H8 300 CPU In comparison to the H8 300 CPU the H8 300H has the following enhancements More general registers Eight 16 bit registers have been added Expanded address space Advanced mode supports a maximum 16 Mbyte address space Normal mode supports the same 64 kbyte address space as ...

Page 32: ... to 16 Mbytes See figure 2 1 The H8 3048 Series can be used only in advanced mode Information from this point on will apply to advanced mode unless otherwise stated Figure 2 1 CPU Operating Modes CPU operating modes Normal mode Advanced mode Maximum 64 kbytes program and data areas combined Maximum 16 Mbytes program and data areas combined 17 www DataSheet4U com ...

Page 33: ...others supporting the full 16 Mbytes Figure 2 2 shows the address ranges of the H8 3048 Series For further details see section 3 6 Memory Map in Each Operating Mode The 1 Mbyte operating modes use 20 bit addressing The upper 4 bits of effective addresses are ignored Figure 2 2 Memory Map H 00000 H FFFFF H 000000 H FFFFFF a 1 Mbyte modes b 16 Mbyte modes 18 www DataSheet4U com ...

Page 34: ...5 ER6 ER7 E0 E1 E2 E3 E4 E5 E6 E7 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L 0 7 0 7 0 15 SP 23 0 PC 7 CCR 6 5 4 3 2 1 0 I UI H U N Z V C General Registers ERn Control Registers CR Legend SP PC CCR I UI H U N Z V C Stack pointer Program counter Condition code register Interrupt mask bit User bit or interrupt mask bit Half carry flag User bit Negative flag Zero flag Overflow fl...

Page 35: ... R0 to R7 These registers are functionally equivalent providing a maximum sixteen 16 bit registers The E registers E0 to E7 are also referred to as extended registers The R registers divide into 8 bit general registers designated by the letters RH R0H to R7H and RL R0L to R7L These registers are functionally equivalent providing a maximum sixteen 8 bit registers Figure 2 4 illustrates the usage of...

Page 36: ... PC bit is ignored When an instruction is fetched the least significant PC bit is regarded as 0 Condition Code Register CCR This 8 bit register contains internal CPU status information including the interrupt mask bit I and half carry H negative N zero Z overflow V and carry C flags Bit 7 Interrupt Mask Bit I Masks interrupts other than NMI when set to 1 NMI is accepted regardless of the I bit set...

Page 37: ...0 Carry Flag C Set to 1 when a carry occurs and cleared to 0 otherwise Used by Add instructions to indicate a carry Subtract instructions to indicate a borrow Shift and rotate instructions to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions Some instructions leave flag bits unchanged Operations can be performed on CCR by t...

Page 38: ... data 2 5 1 General Register Data Formats Figures 2 6 and 2 7 show the data formats in general registers Figure 2 6 General Register Data Formats 1 7 RnH RnL RnH RnL RnH RnL 1 bit data 1 bit data 4 bit BCD data 4 bit BCD data Byte data Byte data 6 5 4 3 2 1 0 7 0 Don t care 7 6 5 4 3 2 1 0 7 0 Don t care Don t care 7 0 4 3 Lower digit Upper digit 7 4 3 Lower digit Upper digit Don t care 0 7 0 Don ...

Page 39: ... data 15 0 MSB LSB General Register Data Type Data Format 15 0 MSB LSB 31 16 MSB 15 0 LSB Legend ERn En Rn RnH RnL MSB LSB General register General register E General register R General register RH General register RL Most significant bit Least significant bit 24 www DataSheet4U com ...

Page 40: ...ant bit of the address is regarded as 0 so the access starts at the preceding address This also applies to instruction fetches Figure 2 8 Memory Data Formats When ER7 SP is used as an address register to access the stack the operand size should be word size or longword size 7 6 5 4 3 2 1 0 Address L Address L LSB MSB MSB LSB 7 0 MSB LSB 1 bit data Byte data Word data Longword data Address Data Typ...

Page 41: ...tions AND OR XOR NOT 4 Shift operations SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR 8 Bit manipulation BSET BCLR BNOT BTST BAND BIAND BOR BIOR BXOR 14 BIXOR BLD BILD BST BIST Branch Bcc 3 JMP BSR JSR RTS 5 System control TRAPA RTE SLEEP LDC STC ANDC ORC XORC NOP 9 Block data transfer EEPMOV 1 Total 62 types Notes 1 POP W Rn is identical to MOV W SP Rn PUSH W Rn is identical to MOV W Rn SP POP L ERn ...

Page 42: ... BWL POP PUSH WL MOVFPE B MOVTPE ADD CMP BWL BWL SUB WL BWL ADDX SUBX B B ADDS SUBS L INC DEC BWL DAA DAS B MULXU BW MULXS DIVXU DIVXS NEG BWL EXTU EXTS WL Logic AND OR BWL BWL operations XOR NOT BWL Shift instructions BWL Bit manipulation B B B Branch Bcc BSR o o JMP JSR o o o RTS o TRAPA o RTE o SLEEP o LDC B B W W W W W W STC B W W W W W W ANDC ORC B XORC NOP o Block data transfer BW Legend B B...

Page 43: ...ation operand EAs Source operand CCR Condition code register N N negative flag of CCR Z Z zero flag of CCR V V overflow flag of CCR C C carry flag of CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move NOT logical complement 3 8 16 24 3 8 16 or 24 bit length Note General registers...

Page 44: ...ed in the H8 3048 Series MOVTPE B Rs EAs Cannot be used in the H8 3048 Series POP W L SP Rn Pops a general register from the stack POP W Rn is identical to MOV W SP Rn Similarly POP L ERn is identical to MOV L SP ERn PUSH W L Rn SP Pushes a general register onto the stack PUSH W Rn is identical to MOV W Rn SP Similarly PUSH L ERn is identical to MOV L ERn SP Note Size refers to the operand size B ...

Page 45: ...eneral register by 1 or 2 Byte operands can be incremented or decremented by 1 only L Rd 1 Rd Rd 2 Rd Rd 4 Rd Adds or subtracts the value 1 2 or 4 to or from data in a 32 bit register B Rd decimal adjust Rd Decimal adjusts an addition or subtraction result in a general register by referring to CCR to produce 4 bit BCD data MULXU B W Rd Rs Rd Performs unsigned multiplication on data in two general ...

Page 46: ...ral register with data in another general register or with immediate data and sets CCR according to the result NEG B W L 0 Rd Rd Takes the two s complement arithmetic complement of data in a general register EXTS W L Rd sign extension Rd Extends byte data in the lower 8 bits of a 16 bit register to word data or extends word data in the lower 16 bits of a 32 bit register to longword data by extendi...

Page 47: ...er general register or immediate data NOT B W L Rd Rd Takes the one s complement of general register contents Note Size refers to the operand size B Byte W Word L Longword Table 2 6 Shift Instructions Instruction Size Function B W L Rd shift Rd Performs an arithmetic shift on general register contents B W L Rd shift Rd Performs a logical shift on general register contents B W L Rd rotate Rd Rotate...

Page 48: ... bit number is specified by 3 bit immediate data or the lower 3 bits of a general register BTST B bit No of EAd Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower 3 bits of a general register BAND B C bit No of EAd C ANDs the carry flag with a specified bit in a general register ...

Page 49: ... the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag The bit number is specified by 3 bit immediate data BLD B bit No of EAd C Transfers a specified bit in a general register or memory operand to the carry flag BILD B bit No of EAd C Transfers the inverse of a specified bit in a general register or memory operand to the...

Page 50: ...me C Z 1 Bcc BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N 0 BMI Minus N 1 BGE Greater or equal N V 0 BLT Less than N V 1 BGT Greater than Z N V 0 BLE Less or equal Z N V 1 JMP Branches unconditionally to a specified address BSR Branches to a subroutine at a specified address JSR Branches to a subro...

Page 51: ... is read by word access STC B W CCR EAd Transfers the CCR contents to a destination location The condition code register size is one byte but in transfer to memory data is written by word access ANDC B CCR IMM CCR Logically ANDs the condition code register with immediate data ORC B CCR IMM CCR Logically ORs the condition code register with immediate data XORC B CCR IMM CCR Logically exclusive ORs ...

Page 52: ... if R4 0 then repeat ER5 ER6 R4 1 R4 until R4 0 else next Transfers a data block according to parameters set in general registers R4L or R4 ER5 and ER6 R4L or R4 Size of block bytes ER5 Starting source address ER6 Starting destination address Execution of the next instruction begins as soon as the transfer is completed 37 www DataSheet4U com ...

Page 53: ...ata registers by 3 bits or 4 bits Some instructions have two register fields Some have no register field Effective Address Extension Eight 16 or 32 bits specifying immediate data an absolute address or a displacement A 24 bit address or displacement is treated as 32 bit data in which the first 8 bits are 0 H 00 Condition Field Specifies the branching condition of Bcc instructions Figure 2 9 shows ...

Page 54: ...set of these addressing modes Arithmetic and logic instructions can use the register direct and immediate modes Data transfer instructions can use all addressing modes except program counter relative and memory indirect Bit manipulation instructions use register direct register indirect or absolute aa 8 addressing mode to specify an operand and register direct BSET BCLR BNOT and BTST instructions ...

Page 55: ... the address of a memory operand After the operand is accessed 1 2 or 4 is added to the address register contents 32 bits and the sum is stored in the address register The value added is 1 for byte access 2 for word access or 4 for longword access For word or longword access the register value should be even Register indirect with pre decrement ERn The value 1 2 or 4 is subtracted from an address ...

Page 56: ... Bcc and BSR instructions An 8 bit or 16 bit displacement contained in the instruction code is sign extended to 24 bits and added to the 24 bit PC contents to generate a 24 bit branch address The PC value to which the displacement is added is the address of the first byte of the next instruction so the possible branching range is 126 to 128 bytes 63 to 64 words or 32766 to 32768 bytes 16383 to 163...

Page 57: ... 0 The accessed data or instruction code therefore begins at the preceding address See section 2 5 2 Memory Data Formats 2 7 2 Effective Address Calculation Table 2 13 explains how an effective address is calculated in each addressing mode In the 1 Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to generate a 20 bit effective address Specified by aa 8 Reserved...

Page 58: ...0 23 0 Register indirect with displacement d 16 ERn d 24 ERn 3 op r General register contents 31 0 23 0 disp Sign extension disp Register indirect with post increment or pre decrement 4 General register contents 31 0 23 0 1 2 or 4 op r General register contents 31 0 23 0 1 2 or 4 op r 1 for a byte operand 2 for a word operand 4 for a longword operand Register indirect with post increment ERn Regis...

Page 59: ...lation Effective Address Absolute address aa 8 5 op Program counter relative d 8 PC or d 16 PC 7 0 23 0 abs 23 0 8 7 aa 16 op abs 23 0 16 15 H FFFF Sign extension aa 24 op 23 0 abs Immediate xx 8 xx 16 or xx 32 6 Operand is immediate data op disp 23 0 PC contents disp op IMM Sign extension 44 www DataSheet4U com ...

Page 60: ...uction Format No Effective Address Calculation Effective Address 8 Legend r rm rn op disp IMM abs Register field Operation field Displacement Immediate data Absolute address Memory indirect aa 8 8 op 23 0 abs 23 0 8 7 H 0000 0 abs 31 Memory contents 45 www DataSheet4U com ...

Page 61: ...g states Program execution state Bus released state Reset state Power down state The CPU executes program instructions in sequence A transient state in which the CPU executes a hardware sequence saving PC and CCR fetching a vector etc in response to a reset interrupt or other exception The external bus has been released in response to a bus request signal from a bus master other than the CPU The C...

Page 62: ...epted at all times in the program execution state Table 2 14 Exception Handling Types and Priority Priority Type of Exception Detection Timing Start of Exception Handling High Reset Synchronized with clock Exception handling starts immediately when RES changes from low to high Interrupt End of instruction When an interrupt is requested execution or end of exception handling starts at the end of ex...

Page 63: ...are standby mode Hardware standby mode Power down state End of bus release Bus request End of bus release Bus request End of exception handling Exception Interrupt SLEEP instruction with SSBY 0 SLEEP instruction with SSBY 1 NMI IRQ IRQ or IRQ interrupt STBY RES 1 0 RES 1 0 1 2 1 2 Notes 1 2 From any state except hardware standby mode a transition to the reset state occurs whenever goes low From an...

Page 64: ... the stack Next if the UE bit in the system control register SYSCR is set to 1 the CPU sets the I bit in the condition code register to 1 If the UE bit is cleared to 0 the CPU sets both the I bit and the UI bit in the condition code register to 1 Then the CPU fetches a start address from the exception vector table and execution branches to that address Figure 2 14 shows the stack after the excepti...

Page 65: ...leep mode software standby mode and hardware standby mode Sleep Mode A transition to sleep mode is made if the SLEEP instruction is executed while the SSBY bit is cleared to 0 in the system control register SYSCR CPU operations stop immediately after execution of the SLEEP instruction but the contents of CPU registers are retained Software Standby Mode A transition to software standby mode is made...

Page 66: ...s space Access to the external address space can be controlled by the bus controller 2 9 2 On Chip Memory Access Timing On chip memory is accessed in two states The data bus is 16 bits wide permitting both byte and word access Figure 2 15 shows the on chip memory access cycle Figure 2 16 indicates the pin states Figure 2 15 On Chip Memory Access Cycle T state Bus cycle Internal address bus Interna...

Page 67: ...Figure 2 16 Pin States during On Chip Memory Access T AS ø 1 T2 Address bus D to D 15 0 RD HWR LWR High Address High impedance 52 www DataSheet4U com ...

Page 68: ...accessed Figure 2 17 shows the on chip supporting module access timing Figure 2 18 indicates the pin states Figure 2 17 Access Cycle for On Chip Supporting Modules Address bus Internal read signal Internal data bus Internal write signal Address Internal data bus ø T state Bus cycle 1 T state 2 T state 3 Read access Write access Write data Read data 53 www DataSheet4U com ...

Page 69: ...space is divided into eight areas areas 0 to 7 Bus controller settings determine whether each area is accessed via an 8 bit or 16 bit bus and whether it is accessed in two or three states For details see section 6 Bus Controller T AS ø 1 T2 Address bus D to D 15 0 RD HWR LWR High High impedance T3 Address 54 www DataSheet4U com ...

Page 70: ...8 bits Enabled Enabled 2 Mode 7 1 1 1 Single chip advanced Enabled Enabled mode Notes 1 In modes 1 to 6 an 8 bit or 16 bit data bus can be selected on a per area basis by settings made in the area bus width control register ABWCR For details see section 6 Bus Controller 2 If the RAME bit in SYSCR is cleared to 0 these addresses become external addresses For the address space size there are two cho...

Page 71: ...3048 Series can be used only in modes 1 to 7 The inputs at the mode pins must select one of these seven modes The inputs at the mode pins must not be changed during operation 3 1 2 Register Configuration The H8 3048 Series has a mode control register MDCR that indicates the inputs at the mode pins MD2 to MD0 and a system control register SYSCR Table 3 2 summarizes these registers Table 3 2 Registe...

Page 72: ... MDS2 to MDS0 These bits indicate the logic levels at pins MD2 to MD0 the current operating mode MDS2 to MDS0 correspond to MD2 to MD0 MDS2 to MDS0 are read only bits The mode pin MD2 to MD0 levels are latched into these bits when MDCR is read Bit Initial value Read Write 7 1 6 1 5 0 4 0 3 0 0 MDS0 R 2 MDS2 R 1 MDS1 R Reserved bits Mode select 2 to 0 Bits indicating the current operating mode Rese...

Page 73: ...causes transition to sleep mode Initial value 1 SLEEP instruction causes transition to software standby mode Bit Initial value Read Write 7 SSBY 0 R W 6 STS2 0 R W 5 STS1 0 R W 4 STS0 0 R W 3 UE 1 R W 0 RAME 1 R W 2 NMIEG 0 R W 1 1 Software standby Enables transition to software standby mode User bit enable Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit NMI edge se...

Page 74: ...1 0 0 Waiting time 131 072 states 1 0 1 Waiting time 1 024 states 1 1 Illegal setting Bit 3 User Bit Enable UE Selects whether to use the UI bit in the condition code register as a user bit or an interrupt mask bit Bit 3 UE Description 0 UI bit in CCR is used as an interrupt mask bit 1 UI bit in CCR is used as a user bit Initial value Bit 2 NMI Edge Select NMIEG Selects the valid edge of the NMI i...

Page 75: ... address space The initial bus mode after a reset is 16 bits with 16 bit access to all areas If all areas are designated for 8 bit access in ABWCR the bus mode switches to 8 bits A23 to A21 are valid when 0 is written in bits 7 to 5 of BRCR In this mode A20 is always used for address output 3 4 5 Mode 5 Ports 1 2 and 5 can function as address pins A19 to A0 permitting access to a maximum 1 Mbyte a...

Page 76: ...PA4 PA7 to PA5 A20 3 PA7 to PA4 Notes 1 Initial state The bus mode can be switched by settings in ABWCR These pins function as P47 to P40 in 8 bit bus mode and as D7 to D0 in 16 bit bus mode 2 Initial state These pins become address output pins when the corresponding bits in the data direction registers P1DDR P2DDR P5DDR are set to 1 3 Initial state A20 is always an address output pin PA7 to PA5 a...

Page 77: ...F8000 H FEF0F H FEF10 H FFF00 H FFF0F H FFF10 H FFF1B H FFF1C H FFFFF Note External addresses can be accessed by disabling on chip RAM Modes 3 and 4 16 Mbyte expanded modes with on chip ROM disabled H 000000 H 0000FF H 007FFF Memory indirect branch addresses 16 bit absolute addresses H 1FFFFF H 200000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 External address space Vector area On chi...

Page 78: ...FF1C H FFFFF H 00000 H 000FF H 07FFF Memory indirect branch addresses 16 bit absolute addresses Vector area On chip ROM On chip RAM On chip registers 8 bit absolute addresses 16 bit absolute addresses H FEF10 H FFF00 H FFF0F H FFF1C H FFFFF H 1FFFF H F8000 Note External addresses can be accessed by disabling on chip RAM On chip ROM H 000000 H 0000FF H 007FFF Memory indirect branch addresses 16 bit...

Page 79: ...F8000 H FEF0F H FEF10 H FFF00 H FFF0F H FFF10 H FFF1B H FFF1C H FFFFF Note External addresses can be accessed by disabling on chip RAM Modes 3 and 4 16 Mbyte expanded modes with on chip ROM disabled H 000000 H 0000FF H 007FFF Memory indirect branch addresses 16 bit absolute addresses H 1FFFFF H 200000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 External address space Vector area On chi...

Page 80: ...rect branch addresses 16 bit absolute addresses Vector area On chip ROM On chip ROM Reserved 1 On chip RAM On chip registers 8 bit absolute addresses 16 bit absolute addresses H FEF10 H FFF00 H FFF0F H FFF1C H FFFFF H 17FFF H F8000 Notes H 1FFFF H 20000 Reserved 1 2 1 2 Do not access the reserved area External addresses can be accessed by disabling on chip RAM H 000000 H 0000FF H 007FFF Memory ind...

Page 81: ...10 H FFF00 H FFF0F H FFF10 H FFF1B H FFF1C H FFFFF Modes 3 and 4 16 Mbyte expanded modes with on chip ROM disabled H 000000 H 0000FF H 007FFF Memory indirect branch addresses 16 bit absolute addresses H 1FFFFF H 200000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 External address space Vector area On chip RAM 2 Reserved 1 External address space On chip registers 8 bit absolute addresses...

Page 82: ... 000FF Memory indirect branch addresses 16 bit absolute addresses Vector area On chip ROM On chip RAM On chip registers 8 bit absolute addresses 16 bit absolute addresses H FF710 H FFF00 H FFF0F H FFF1C H FFFFF H 07FFF H F8000 Notes Reserved 1 1 2 Do not access the reserved area External addresses can be accessed by disabling on chip RAM H 000000 H 0000FF H 007FFF H 008000 H 01FFFF Memory indirect...

Page 83: ...FF710 H FFF00 H FFF0F H FFF10 H FFF1B H FFF1C H FFFFF Modes 3 and 4 16 Mbyte expanded modes with on chip ROM disabled H 000000 H 0000FF H 007FFF Memory indirect branch addresses 16 bit absolute addresses H 1FFFFF H 200000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 External address space Vector area On chip RAM 2 Reserved 1 External address space On chip registers 8 bit absolute addres...

Page 84: ... 00000 H 000FF Memory indirect branch addresses 16 bit absolute addresses Vector area On chip ROM On chip RAM On chip registers 8 bit absolute addresses 16 bit absolute addresses H FF710 H FFF00 H FFF0F H FFF1C H FFFFF H 07FFF H 0FFFF H F8000 Notes Reserved 1 1 2 Do not access the reserved area External addresses can be accessed by disabling on chip RAM H 000000 H 0000FF H 007FFF H 00FFFF H 010000...

Page 85: ...tely after a low to high transition at the RES pin Interrupt Interrupt requests are handled when execution of the current instruction or handling of the current exception is completed Low Trap instruction TRAPA Started by execution of a trap instruction TRAPA 4 1 2 Exception Handling Operation Exceptions originate from various sources Trap instructions and interrupts are handled as follows 1 The p...

Page 86: ...0020 to H 0023 9 H 0024 to H 0027 10 H 0028 to H 002B 11 H 002C to H 002F External interrupt IRQ0 12 H 0030 to H 0033 External interrupt IRQ1 13 H 0034 to H 0037 External interrupt IRQ2 14 H 0038 to H 003B External interrupt IRQ3 15 H 003C to H 003F External interrupt IRQ4 16 H 0040 to H 0043 External interrupt IRQ5 17 H 0044 to H 0047 Reserved for system use 18 H 0048 to H 004B 19 H 004C to H 004...

Page 87: ...ast 20 ms at power up To reset the chip during operation hold the RES pin low for at least 10 system clock ø cycles See appendix D 2 Pin States at Reset for the states of the pins in the reset state When the RES pin goes high after being held low for the necessary time the chip starts reset exception handling as follows The internal state of the CPU and the registers of the on chip supporting modu...

Page 88: ...program instruction 1 3 5 7 2 4 6 8 9 10 Note After a reset the wait state controller inserts three wait states in every bus cycle Address of reset vector 1 H 00000 3 H 00001 5 H 00002 7 H 00003 Start address contents of reset vector Start address First instruction of program High 1 3 5 7 9 2 4 6 8 10 LWR 74 www DataSheet4U com ...

Page 89: ...Prefetch of first program instruction 1 3 2 4 5 6 Note After a reset the wait state controller inserts three wait states in every bus cycle High LWR Address of reset vector 1 H 000000 3 H 000002 Start address contents of reset vector Start address First instruction of program 2 4 3 1 5 6 75 www DataSheet4U com ...

Page 90: ... The first instruction of the program is always executed immediately after the reset state ends This instruction should initialize the stack pointer example MOV L xx 32 SP Vector fetch Internal processing Prefetch of first program instruction ø Internal address bus RES Internal read signal Internal write signal Internal data bus 16 bits wide 1 3 5 2 4 6 1 3 2 4 5 6 Address of reset vector 1 H 0000...

Page 91: ...controller The interrupt controller can assign interrupts other than NMI to two priority levels and arbitrate between simultaneous interrupts Interrupt priorities are assigned in interrupt priority registers A and B IPRA and IPRB in the interrupt controller For details on interrupts see section 5 Interrupt Controller Figure 4 5 Interrupt Sources and Number of Interrupts Interrupts External interru...

Page 92: ... the system control register SYSCR the exception handling sequence sets the I bit to 1 in CCR If the UE bit is 0 the I and UI bits are both set to 1 The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3 which is specified in the instruction code 78 www DataSheet4U com ...

Page 93: ... 4 Before exception handling After exception handling Stack area CCR PC PC PC E H L Even address Pushed on stack Legend PCE PCH PCL CCR SP Notes PC indicates the address of the first instruction that will be executed after return Registers must be saved in word or longword size at even addresses 1 2 Bits 23 to 16 of program counter PC Bits 15 to 8 of program counter PC Bits 7 to 0 of program count...

Page 94: ...ng instructions to restore registers POP W Rn or MOV W SP Rn POP L ERn or MOV L SP ERn Setting SP to an odd value may lead to a malfunction Figure 4 7 shows an example of what happens when the SP value is odd Figure 4 7 Operation when SP Value is Odd TRAPA instruction executed CCR Legend CCR PC R1L SP SP PC R1L PC SP SP MOV B R1L ER7 SP set to H FFFEFF Data saved above SP CCR contents lost Conditi...

Page 95: ...A and B IPRA and IPRB Three level masking by the I and UI bits in the CPU condition code register CCR Independent vector addresses All interrupts are independently vectored the interrupt service routine does not have to identify the interrupt source Seven external interrupt pins NMI has the highest priority and is always accepted either the rising or falling edge can be selected For each of IRQ0 t...

Page 96: ...I ADIE CPU CCR I UI UE SYSCR ISCR IER ISR IPRA IPRB SYSCR NMI input IRQ input IRQ input section ISR Interrupt controller Priority decision logic Interrupt request Vector number IRQ sense control register IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B System control register Legend 82 www DataSheet4U com ...

Page 97: ...r Configuration Table 5 2 lists the registers of the interrupt controller Table 5 2 Interrupt Controller Registers Address 1 Name Abbreviation R W Initial Value H FFF2 System control register SYSCR R W H 0B H FFF4 IRQ sense control register ISCR R W H 00 H FFF5 IRQ enable register IER R W H 00 H FFF6 IRQ status register ISR R W 2 H 00 H FFF8 Interrupt priority register A IPRA R W H 00 H FFF9 Inter...

Page 98: ...ection 3 3 System Control Register SYSCR SYSCR is initialized to H 0B by a reset and in hardware standby mode It is not initialized in software standby mode Bit Initial value Read Write 7 SSBY 0 R W 6 STS2 0 R W 5 STS1 0 R W 4 STS0 0 R W 3 UE 1 R W 0 RAME 1 R W 2 NMIEG 0 R W 1 1 Software standby Standby timer select 2 to 0 User bit enable Selects whether to use the UI bit in CCR as a user bit or i...

Page 99: ... used as user bit Initial value Bit 2 NMI Edge Select NMIEG Selects the NMI input edge Bit 2 NMIEG Description 0 Interrupt is requested at falling edge of NMI input Initial value 1 Interrupt is requested at rising edge of NMI input 5 2 2 Interrupt Priority Registers A and B IPRA IPRB IPRA and IPRB are 8 bit readable writable registers that control interrupt priority 85 www DataSheet4U com ...

Page 100: ...ts Priority level A3 Selects the priority level of WDT and refresh controller interrupt requests Priority level A2 Selects the priority level of ITU channel 0 interrupt requests Priority level A1 Selects the priority level of ITU channel 1 interrupt requests Priority level A0 Selects the priority level of ITU channel 2 interrupt requests Selects the priority level of IRQ interrupt requests Priorit...

Page 101: ... 1 IRQ1 interrupt requests have priority level 1 high priority Bit 5 Priority Level A5 IPRA5 Selects the priority level of IRQ2 and IRQ3 interrupt requests Bit 5 IPRA5 Description 0 IRQ2 and IRQ3 interrupt requests have priority level 0 low priority Initial value 1 IRQ2 and IRQ3 interrupt requests have priority level 1 high priority Bit 4 Priority Level A4 IPRA4 Selects the priority level of IRQ4 ...

Page 102: ...ty level 0 low priority Initial value 1 ITU channel 0 interrupt requests have priority level 1 high priority Bit 1 Priority Level A1 IPRA1 Selects the priority level of ITU channel 1 interrupt requests Bit 1 IPRA1 Description 0 ITU channel 1 interrupt requests have priority level 0 low priority Initial value 1 ITU channel 1 interrupt requests have priority level 1 high priority Bit 0 Priority Leve...

Page 103: ...level B7 Selects the priority level of ITU channel 3 interrupt requests Priority level B3 Selects the priority level of SCI channel 0 interrupt requests Priority level B2 Selects the priority level of SCI channel 1 interrupt requests Priority level B1 Selects the priority level of A D converter interrupt request Reserved bit Selects the priority level of ITU channel 4 interrupt requests Priority l...

Page 104: ...6 Description 0 ITU channel 4 interrupt requests have priority level 0 low priority Initial value 1 ITU channel 4 interrupt requests have priority level 1 high priority Bit 5 Priority Level B5 IPRB5 Selects the priority level of DMAC interrupt requests channels 0 and 1 Bit 5 IPRB5 Description 0 DMAC interrupt requests channels 0 and 1 have priority level 0 Initial value low priority 1 DMAC interru...

Page 105: ...s Bit 2 IPRB2 Description 0 SCI1 interrupt requests have priority level 0 low priority Initial value 1 SCI1 interrupt requests have priority level 1 high priority Bit 1 Priority Level B1 IPRB1 Selects the priority level of A D converter interrupt requests Bit 1 IPRB1 Description 0 A D converter interrupt requests have priority level 0 low priority Initial value 1 A D converter interrupt requests h...

Page 106: ...nditions Initial value 0 is written in IRQnF after reading the IRQnF flag when IRQnF 1 IRQnSC 0 IRQn input is high and interrupt exception handling is carried out IRQnSC 1 and IRQn interrupt exception handling is carried out 1 Setting conditions IRQnSC 0 and IRQn input is low IRQnSC 1 and IRQn input changes from high to low Note n 5 to 0 Bit Initial value Read Write 7 0 These bits indicate IRQ to ...

Page 107: ...le interrupts Bits 5 to 0 IRQ5 to IRQ0 Enable IRQ5E to IRQ0E These bits enable or disable IRQ5 to IRQ0 interrupts Bits 5 to 0 IRQ5E to IRQ0E Description 0 IRQ5 to IRQ0 interrupts are disabled Initial value 1 IRQ5 to IRQ0 interrupts are enabled Bit Initial value Read Write 7 0 R W These bits enable or disable IRQ to IRQ interrupts 6 0 R W 5 IRQ5E 0 R W 4 IRQ4E 0 R W 3 IRQ3E 0 R W 2 IRQ2E 0 R W 1 IR...

Page 108: ...0SC These bits select whether interrupts IRQ5 to IRQ0 are requested by level sensing of pins IRQ5 to IRQ0 or by falling edge sensing Bits 5 to 0 IRQ5SC to IRQ0SC Description 0 Interrupts are requested when IRQ5 to IRQ0 inputs are low Initial value 1 Interrupts are requested by falling edge input at IRQ5 to IRQ0 Bit Initial value Read Write 7 0 R W These bits select level sensing or falling edge se...

Page 109: ...o IRQ5 Interrupts These interrupts are requested by input signals at pins IRQ0 to IRQ5 The IRQ0 to IRQ5 interrupts have the following features ISCR settings can select whether an interrupt is requested by the low level of the input at pins IRQ0 to IRQ5 or by the falling edge IER settings can enable or disable the IRQ0 to IRQ5 interrupts Interrupt priority levels can be assigned by four bits in IPR...

Page 110: ...rting module has status flags for indicating interrupt status and enable bits for enabling or disabling interrupts Interrupt priority levels can be assigned in IPRA and IPRB ITU and SCI interrupt requests can activate the DMAC in which case no interrupt request is sent to the interrupt controller and the I and UI bits are disregarded 5 3 3 Interrupt Vector Table Table 5 3 lists the interrupt sourc...

Page 111: ... 0050 to H 0053 IPRA3 interval timer timer CMI Refresh 21 H 0054 to H 0057 compare match controller Reserved 22 H 0058 to H 005B 23 H 005C to H 005F IMIA0 ITU channel 0 24 H 0060 to H 0063 IPRA2 compare match input capture A0 IMIB0 25 H 0064 to H 0067 compare match input capture B0 OVI0 overflow 0 26 H 0068 to H 006B Reserved 27 H 006C to H 006F IMIA1 ITU channel 1 28 H 0070 to H 0073 IPRA1 compar...

Page 112: ...capture A3 IMIB3 37 H 0094 to H 0097 compare match input capture B3 OVI3 overflow 3 38 H 0098 to H 009B Reserved 39 H 009C to H 009F IMIA4 ITU channel 4 40 H 00A0 to H 00A3 IPRB6 compare match input capture A4 IMIB4 41 H 00A4 to H 00A7 compare match input capture B4 OVI4 overflow 4 42 H 00A8 to H 00AB Reserved 43 H 00AC to H 00AF DEND0A DMAC 44 H 00B0 to H 00B3 IPRB5 DEND0B 45 H 00B4 to H 00B7 DEN...

Page 113: ... H 00D4 to H 00D7 data full 0 TXI0 transmit 54 H 00D8 to H 00DB data empty 0 TEI0 transmit end 0 55 H 00DC to H 00DF ERI1 receive error 1 SCI channel 1 56 H 00E0 to H 00E3 IPRB2 RXI1 receive 57 H 00E4 to H 00E7 data full 1 TXI1 transmit 58 H 00E8 to H 00EB data empty 1 TEI1 transmit end 1 59 H 00EC to H 00EF ADI A D end A D 60 H 00F0 to H 00F3 IPRB1 Low Note Lower 16 bits of the address 99 www Dat...

Page 114: ...e cleared to 0 Table 5 4 UE I and UI Bit Settings and Interrupt Handling SYSCR CCR UE I UI Description 1 0 All interrupts are accepted Interrupts with priority level 1 have higher priority 1 No interrupts are accepted except NMI 0 0 All interrupts are accepted Interrupts with priority level 1 have higher priority 1 0 NMI and interrupts with priority level 1 are accepted 1 No interrupts are accepte...

Page 115: ...am execution state Interrupt requested NMI No Yes No Yes No Priority level 1 No IRQ0 Yes No IRQ1 Yes ADI Yes No IRQ0 Yes No IRQ1 Yes ADI Yes No I 0 Yes Save PC and CCR I 1 Branch to interrupt service routine Pending Yes Read vector address 101 www DataSheet4U com ...

Page 116: ...executed after the return from the interrupt service routine Next the I bit is set to 1 in CCR masking all interrupts except NMI The vector address of the accepted interrupt is generated and the interrupt service routine starts executing from the address indicated by the contents of the vector address UE 0 The I and UI bits in the CPU s CCR and the IPR bits enable three level masking of IRQ0 to IR...

Page 117: ...nd the UI bit is cleared to 0 only NMI and interrupts with priority level 1 are accepted interrupt requests with priority level 0 are held pending If the I bit and UI bit are both set to 1 only NMI is accepted all other interrupt requests are held pending When an interrupt request is accepted interrupt exception handling starts after execution of the current instruction has been completed In inter...

Page 118: ...tate Interrupt requested NMI No Yes No Yes No Priority level 1 No IRQ0 Yes No IRQ1 Yes ADI Yes No IRQ0 Yes No IRQ1 Yes ADI Yes No I 0 Yes No I 0 Yes UI 0 Yes No Save PC and CCR I 1 UI 1 Pending Branch to interrupt service routine Yes Read vector address 104 www DataSheet4U com ...

Page 119: ...l decision and wait for end of instruction Interrupt accepted Instruction prefetch Internal processing Stack Vector fetch Internal processing Prefetch of interrupt service routine instruction High Instruction prefetch address not executed return address same as PC contents Instruction code not executed Instruction prefetch address not executed SP 2 SP 4 6 8 9 11 10 12 13 14 PC and CCR saved to sta...

Page 120: ...5 4 of states until end of current instruction 3 Saving PC and CCR 4 8 12 4 4 6 4 to stack 4 Vector fetch 4 8 12 4 4 6 4 5 Instruction prefetch 2 4 8 12 4 4 6 4 6 Internal processing 3 4 4 4 4 4 Total 19 to 41 31 to 57 43 to 73 19 to 41 25 to 49 Notes 1 1 state for internal interrupts 2 Prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt service routine ...

Page 121: ...is carried out If a higher priority interrupt is also requested however interrupt exception handling for the higher priority interrupt is carried out and the lower priority interrupt is ignored This also applies to the clearing of an interrupt flag Figure 5 8 shows an example in which an IMIEA bit is cleared to 0 in TIER of the ITU Figure 5 8 Contention between Interrupt and Interrupt Disabling In...

Page 122: ...ved on the stack is the address of the next instruction Programs should be coded as follows to allow for NMI interrupts during EEPMOV W execution L1 EEPMOV W MOV W R4 R4 BNE L1 5 5 4 Notes on External Interrupts during Use If the IRQnF flag is at IRQnF 1 after reading the IRQnF flag if the IRQnF flag writes 0 clear status is reached However there are times when clear status occurs in error and int...

Page 123: ...RQbF flag reaches 0 between occurrence conditions 1 and 2 IRQbF flag does not clear in error Figure 5 9 IRQnF Flag When Interrupt Processing Is Not Conducted In this situation conduct one of the following countermeasures Countermeasure 1 When IRQaF flag clears do not use the bit computation command read the ISR in bytes When IRQaF only is 0 write all other bits as 1 in bytes For example if a 0 MOV...

Page 124: ...MOV B R0L ISR Countermeasure 2 During IRQb interrupt processing carry out IRQb Fflag clear dummy processing For example if b 1 IRQB MOV B HFD R0L MOV B R0L ISR 110 www DataSheet4U com ...

Page 125: ...tures Features of the bus controller are listed below Independent settings for address areas 0 to 7 128 kbyte areas in 1 Mbyte modes 2 Mbyte areas in 16 Mbyte modes Chip select signals CS0 to CS7 can be output for areas 0 to 7 Areas can be designated for 8 bit or 16 bit access Areas can be designated for two state or three state access Four wait modes Programmable wait mode pin auto wait mode and ...

Page 126: ... width control register Access state control register Wait state controller enable register Wait control register Bus release control register Chip select control register CPU bus request signal DMAC bus request signal Refresh controller bus request signal CPU bus acknowledge signal DMAC bus acknowledge signal Refresh controller bus acknowledge signal Internal signals WCR BRCR Bus arbiter 7 Bus mo...

Page 127: ... to D0 Wait WAIT Input Wait request signal for access to external three state access areas Bus request BREQ Input Request signal for releasing the bus to an external device Bus acknowledge BACK Output Acknowledge signal indicating the bus is released to an external device 6 1 4 Register Configuration Table 6 2 summarizes the bus controller s registers Table 6 2 Bus Controller Registers Initial Val...

Page 128: ...a reset and in hardware standby mode ABWCR is not initialized in software standby mode Bits 7 to 0 Area 7 to 0 Bus Width Control ABW7 to ABW0 These bits select 8 bit access or 16 bit access to the corresponding address areas Bits 7 to 0 ABW7 to ABW0 Description 0 Areas 7 to 0 are 16 bit access areas 1 Areas 7 to 0 are 8 bit access areas ABWCR specifies the bus width of external memory areas The bu...

Page 129: ...ee states Bits 7 to 0 AST7 to AST0 Description 0 Areas 7 to 0 are accessed in two states 1 Areas 7 to 0 are accessed in three states Initial value ASTCR specifies the number of states in which external areas are accessed On chip memory and registers are accessed in a fixed number of states that does not depend on ASTCR settings These settings are therefore meaningless in single chip mode mode 7 Bi...

Page 130: ...y bits always read as 1 Bits 3 and 2 Wait Mode Select 1 and 0 WMS1 0 These bits select the wait mode Bit 3 Bit 2 WMS1 WMS0 Description 0 0 Programmable wait mode Initial value 1 No wait states inserted by wait state controller 1 0 Pin wait mode 1 1 Pin auto wait mode Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 WMS1 0 R W 0 WC0 1 R W 2 WMS0 0 R W 1 WC1 1 R W Wait count 1 0 These bits select the ...

Page 131: ...set and in hardware standby mode It is not initialized in software standby mode Bits 7 to 0 Wait State Controller Enable 7 to 0 WCE7 to WCE0 These bits enable or disable wait state control of external three state access areas Bits 7 to 0 WCE7 to WCE0 Description 0 Wait state control disabled pin wait mode 0 1 Wait state control enabled Initial value Since WCER enables or disables wait state contro...

Page 132: ...is the A23 address output pin 1 PA4 is the PA4 TP4 TIOCA1 input output pin Initial value Bit 6 Address 22 Enable A22E Enables PA5 to be used as the A22 address output pin Writing 0 in this bit enables A22 address output from PA5 In modes other than 3 4 and 6 this bit cannot be modified and PA5 has its ordinary input output functions Bit 6 A22E Description 0 PA5 is the A22 address output pin 1 PA5 ...

Page 133: ...alue can be used as input output pins 1 The bus can be released to an external device 6 2 6 Chip Select Control Register CSCR CSCR is an 8 bit readable writable register that enables or disables output of chip select signals CS7 to CS4 If a chip select signal CS7 to CS4 output is selected in this register the corresponding pin functions as a chip select signal CS7 to CS4 output this function takin...

Page 134: ...isable output of the corresponding chip select signal Bit n CSnE Description 0 Output of chip select signal CSn is disabled Initial value 1 Output of chip select signal CSn is enabled Note n 7 to 4 Bits 3 to 0 Reserved Read only bits always read as 1 120 www DataSheet4U com ...

Page 135: ...ea 4 2 Mbytes Area 5 2 Mbytes Area 6 2 Mbytes Area 7 2 Mbytes On chip RAM External address space On chip registers 1 2 1 3 H 1FFFFF H 200000 H 3FFFFF H 400000 H 5FFFFF H 600000 H 7FFFFF H 800000 H 9FFFFF H A00000 H BFFFFF H C00000 H DFFFFF H E00000 H FFFFFF H 000000 H 1FFFFF H 200000 H 3FFFFF H 400000 H 5FFFFF H 600000 H 7FFFFF H 800000 H 9FFFFF H A00000 H BFFFFF H C00000 H DFFFFF H E00000 H FFFFF...

Page 136: ... WCER WCR Bus Specifications Bus Access ABWn ASTn WCEn WMS1 WMS0 Width States Wait Mode 0 0 16 2 Disabled 1 0 16 3 Pin wait mode 0 1 0 0 16 3 Programmable wait mode 1 16 3 Disabled 1 0 16 3 Pin wait mode 1 1 16 3 Pin auto wait mode 1 0 8 2 Disabled 1 0 8 3 Pin wait mode 0 1 0 0 8 3 Programmable wait mode 1 8 3 Disabled 1 0 8 3 Pin wait mode 1 1 8 3 Pin auto wait mode Note n 0 to 7 122 www DataShee...

Page 137: ...th on chip ROM enabled a reset leaves pins CS0 to CS3 in the input state To output chip select signals CS0 to CS3 the corresponding DDR bits must be set to 1 For details see section 9 I O Ports Output of CS4 to CS7 Output of CS4 to CS7 is enabled or disabled in the chip select control register CSCR A reset leaves pins CS4 to CS7 in the input state To output chip select signals CS4 to CS7 the corre...

Page 138: ...bus Table 6 4 indicates how the two parts of the data bus are used under different access conditions Table 6 4 Access Conditions and Data Bus Usage Access Read Valid Upper Data Bus Lower Data Bus Area Size Write Address Strobe D15 to D8 D7 to D0 Read RD Valid Invalid Write HWR Undetermined data Byte Read Even RD Valid Invalid Odd Invalid Valid Write Even HWR Valid Undetermined data Odd LWR Undeter...

Page 139: ...s used to access these areas The LWR pin is always high Wait states can be inserted Figure 6 4 Bus Control Signal Timing for 8 Bit Three State Access Area ø Address bus CS AS RD D to D D to D HWR LWR D to D D to D n 15 8 7 0 15 8 7 0 T1 T2 T3 Read access Write access Bus cycle External address in area n Valid Invalid High Valid Undetermined data Note n 7 to 0 125 www DataSheet4U com ...

Page 140: ...these areas The LWR pin is always high Wait states cannot be inserted Figure 6 5 Bus Control Signal Timing for 8 Bit Two State Access Area ø Address bus CS AS RD D to D D to D HWR LWR D to D D to D 15 8 7 0 15 8 7 0 n T1 T2 Read access Write access High Bus cycle External address in area n Valid Invalid Valid Undetermined data Note n 7 to 0 126 www DataSheet4U com ...

Page 141: ...r address bus D7 to D0 is used to access odd addresses Wait states can be inserted Figure 6 6 Bus Control Signal Timing for 16 Bit Three State Access Area 1 Byte Access to Even Address ø Address bus CS AS RD D to D D to D HWR LWR D to D D to D n 15 8 7 0 15 8 7 0 T1 T2 T3 Read access Write access Bus cycle Even external address in area n Valid Invalid Valid Undetermined data High Note n 7 to 0 127...

Page 142: ...Area 2 Byte Access to Odd Address ø Address bus CS AS RD D to D D to D HWR LWR D to D D to D n 15 8 7 0 15 8 7 0 T1 T2 T3 Read access Write access Bus cycle Odd external address in area n Invalid Valid Undetermined data Valid High Note n 7 to 0 128 www DataSheet4U com ...

Page 143: ...Three State Access Area 3 Word Access ø Address bus CS AS RD D to D D to D HWR LWR D to D D to D n 15 8 7 0 15 8 7 0 T1 T2 T3 Read access Bus cycle External address in area n Valid Valid Valid Valid Write access Note n 7 to 0 129 www DataSheet4U com ...

Page 144: ...r address bus D7 to D0 is used to access odd addresses Wait states cannot be inserted Figure 6 9 Bus Control Signal Timing for 16 Bit Two State Access Area 1 Byte Access to Even Address ø Address bus CS AS RD D to D D to D HWR LWR D to D D to D 15 8 7 0 15 8 7 0 n T1 T2 Read access Write access Valid Undetermined data High Valid Invalid Bus cycle Even external address in area n Note n 7 to 0 130 w...

Page 145: ... Area 2 Byte Access to Odd Address ø Address bus CS AS RD D to D D to D HWR LWR D to D D to D 15 8 7 0 15 8 7 0 n T1 T2 Read access Invalid Valid High Bus cycle Odd external address in area n Write access Undetermined data Valid Note n 7 to 0 131 www DataSheet4U com ...

Page 146: ...it Two State Access Area 3 Word Access ø Address bus CS AS RD D to D D to D HWR LWR D to D D to D 15 8 7 0 15 8 7 0 n T1 T2 Read access Write access Valid Valid Valid Valid Bus cycle External address in area n Note n 7 to 0 132 www DataSheet4U com ...

Page 147: ...election ASTCR WCER WCR ASTn Bit WCEn Bit WMS1 Bit WMS0 Bit WSC Control Wait Mode 0 Disabled No wait states 1 0 Disabled Pin wait mode 0 1 0 0 Enabled Programmable wait mode 1 Enabled No wait states 1 0 Enabled Pin wait mode 1 1 Enabled Pin auto wait mode Note n 7 to 0 133 www DataSheet4U com ...

Page 148: ...trol During access to an external three state access area if the WAIT pin is low at the fall of the system clock ø in the T2 state a wait state TW is inserted If the WAIT pin remains low wait states continue to be inserted until the WAIT signal goes high Figure 6 12 shows the timing Figure 6 12 Pin Wait Mode 0 ø pin Address bus Data bus AS RD HWR Data bus LWR T1 T2 TW TW T3 Inserted by signal Writ...

Page 149: ...st of these wait states an additional wait state is inserted If the WAIT pin remains low wait states continue to be inserted until the WAIT signal goes high Pin wait mode 1 is useful for inserting four or more wait states or for inserting different numbers of wait states for different external devices If the wait count is 0 this mode operates in the same way as pin wait mode 0 Figure 6 13 shows th...

Page 150: ...e inserted even if the WAIT pin remains low Pin auto wait mode can be used for an easy interface to low speed memory simply by routing the chip select signal to the WAIT pin Figure 6 14 shows the timing when the wait count is 1 Figure 6 14 Pin Auto Wait Mode ø Address bus Data bus AS RD HWR Data bus LWR T1 T2 T3 T1 T2 TW T3 Read data Read data Write data Write data Read access Write access Note Ar...

Page 151: ...n all accesses to external three state access areas Figure 6 15 shows the timing when the wait count is 1 WC1 0 WC0 1 Figure 6 15 Programmable Wait Mode T1 T2 TW T3 ø Address bus AS RD HWR Data bus Data bus External address Read data Write data Read access Write access LWR 137 www DataSheet4U com ...

Page 152: ...1 0 0 1 0 0 1 1 1 1 1 1 Bit ASTCR H 0F WCER H 33 WCR H F3 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 3 state access area programmable wait mode 3 states inserted 3 state access area programmable wait mode 3 states inserted 3 state access area pin wait mode 0 3 state access area pin wait mode 0 2 state access area no wait states inserted 2 state access area no wait states inserted 2 st...

Page 153: ... three states via a 16 bit bus Two 32 kword 8 bit SRAM devices SRAM1 and SRAM2 are connected to area 1 These devices are accessed in two states via a 16 bit bus One 32 kword 8 bit SRAM SRAM3 is connected to area 2 This device is accessed via an 8 bit bus using three state access with an additional wait state inserted in pin auto wait mode Figure 6 17 Memory Map Example H 000000 H 07FFFF H 1FFFFF H...

Page 154: ... to A 18 1 SRAM1 even addresses A to A I O to I O CS OE WE 14 7 0 0 A to A 15 1 SRAM2 odd addresses A to A I O to I O CS OE WE 14 7 0 0 A to A 15 1 SRAM3 A to A I O to I O CS OE WE 14 7 0 0 A to A 14 0 H8 3048 Series CS CS CS 0 1 2 WAIT RD HWR LWR A to A 23 0 D to D D to D 15 8 7 0 140 www DataSheet4U com ...

Page 155: ...er refresh controller DMAC CPU Low The bus arbiter samples the bus request signals and determines priority at all times but it does not always grant the bus immediately even when it receives a bus request from a bus master with higher priority than the current bus master Each bus master has certain times at which it can release the bus to a higher priority bus master CPU The CPU is the lowest prio...

Page 156: ...esh controller releases the bus For details see section 7 Refresh Controller External Bus Master When the BRLE bit is set to 1 in BRCR the bus can be released to an external bus master The external bus master has highest priority and requests the bus right from the bus arbiter by driving the BREQ signal low Once the external bus master gets the bus it keeps the bus right until the BREQ signal goes...

Page 157: ...CK RD LWR T1 T2 Address 2 1 3 4 5 6 High CPU cycles External bus released CPU cycles Minimum 2 cycles High impedance High impedance High impedance High impedance 1 2 3 4 5 6 Low signal is sampled at rise of T state signal goes low at end of CPU read cycle releasing bus right to external bus master pin continues to be sampled while bus is released to external bus master High signal is sampled twice...

Page 158: ...4 2 Register Write Timing ABWCR ASTCR and WCER Write Timing Data written to ABWCR ASTCR or WCER takes effect starting from the next bus cycle Figure 6 20 shows the timing when an instruction fetched from area 0 changes area 0 from three state access to two state access Figure 6 20 ASTCR Write Timing ø T1 T2 T3 T1 T2 T3 T1 T2 ASTCR address 3 state access to area 0 2 state access to area 0 Address b...

Page 159: ... CS1 output Figure 6 21 DDR Write Timing BRCR Write Timing Data written to switch between A23 A22 or A21 output and generic input or output takes effect starting from the T3 state of the BRCR write cycle Figure 6 22 shows the timing when a pin is changed from generic input to A23 A22 or A21 output Figure 6 22 BRCR Write Timing ø CS1 T1 T2 T3 P8DDR address High impedance Address bus ø A to A 23 T1 ...

Page 160: ... incorrectly 6 4 4 Transition To Software Standby Mode If contention occurs between a transition to software standby mode and a bus request from an external bus master the bus may be released for one state just before the transition to software standby mode see figure 6 23 When using software standby mode clear the BRLE bit to 0 in BRCR before executing the SLEEP instruction Figure 6 23 Contention...

Page 161: ...esh controller can be used for one of three functions DRAM refresh control pseudo static RAM refresh control or 8 bit interval timing Features of the refresh controller are listed below Features as a DRAM Refresh Controller Enables direct connection of 16 bit wide DRAM Selection of 2CAS or 2WE mode Selection of 8 bit or 9 bit column address multiplexing for DRAM address input Examples 1 Mbit DRAM ...

Page 162: ... 1 2 Block Diagram Figure 7 1 shows a block diagram of the refresh controller Figure 7 1 Block Diagram of Refresh Controller ø 2 ø 8 ø 32 ø 128 ø 512 ø 2048 ø 4096 RTCNT RTCOR RTMCSR RFSHCR Legend RTCNT RTCOR RTMCSR RFSHCR Refresh signal Clock selector Comparator CMI interrupt Bus interface Internal data bus Module data bus Refresh timer counter Refresh time constant register Refresh timer control...

Page 163: ...ress strobe or LCAS pin of 2CAS DRAM RD Column address strobe CAS WE Output Connects to the CAS pin of 2WE write enable DRAM or WE pin of 2CAS DRAM CS3 Row address strobe RAS Output Connects to the RAS pin of DRAM 7 1 4 Register Configuration Table 7 2 summarizes the refresh controller s registers Table 7 2 Refresh Controller Registers Address Name Abbreviation R W Initial Value H FFAC Refresh con...

Page 164: ...W 4 CAS WE 0 R W 3 M9 M8 0 R W 0 RCYCE 0 R W 2 RFSHE 0 R W 1 1 Self refresh mode Selects self refresh mode PSRAM enable and DRAM enable These bits enable or disable connection of pseudo static RAM and DRAM Strobe mode select Selects 2CAS or 2WE strobing of DRAM Address multiplex mode select Selects the number of column address bits Refresh pin enable Enables refresh signal output from the refresh ...

Page 165: ... standby mode Bit 6 PSRAM Enable PSRAME and Bit 5 DRAM Enable DRAME These bits enable or disable connection of pseudo static RAM and DRAM to area 3 of the external address space When DRAM or pseudo static RAM is connected the bus cycle and refresh cycle of area 3 consist of three states regardless of the setting in the access state control register ASTCR If AST3 0 in ASTCR wait states cannot be in...

Page 166: ...fresh Pin Enable RFSHE Enables or disables refresh signal output from the RFSH pin This bit is write disabled when the PSRAME or DRAME bit is set to 1 Bit 2 RFSHE Description 0 Refresh signal output at the RFSH pin is disabled Initial value the RFSH pin can be used as a generic input output port 1 Refresh signal output at the RFSH pin is enabled Bit 1 Reserved Read only bit always read as 1 Bit 0 ...

Page 167: ...are Match Flag CMF This status flag indicates that the RTCNT and RTCOR values have matched Bit 7 CMF Description 0 Clearing condition Cleared by reading CMF when CMF 1 then writing 0 in CMF 1 Setting condition When RTCNT RTCOR Bit Initial value Read Write 7 CMF 0 R W 6 CMIE 0 R W 5 CKS2 0 R W 4 CKS1 0 R W 3 CKS0 0 R W 0 1 2 1 1 1 Compare match flag Status flag indicating that RTCNT has matched RTC...

Page 168: ...h control the refresh controller outputs a refresh request at periodic intervals determined by compare match between RTCNT and RTCOR When used as an interval timer the refresh controller generates CMI interrupts at periodic intervals determined by compare match These bits are write disabled when the PSRAME bit or DRAME bit is set to 1 Bit 5 Bit 4 Bit 3 CKS2 CKS1 CKS0 Description 0 0 0 Clock input ...

Page 169: ...TCOR is an 8 bit readable writable register that determines the interval at which RTCNT is compare matched RTCOR and RTCNT are constantly compared When their values match the CMF flag is set to 1 in RTMCSR and RTCNT is simultaneously cleared to H 00 RTCOR is write disabled when the PSRAME bit or DRAME bit is set to 1 RTCOR is initialized to H FF by a reset and in hardware standby mode In software ...

Page 170: ...ut Cleared to 0 RCYCE Selects insertion of refresh cycles RTCOR Refresh interval setting Interrupt interval setting RTMCSR CKS2 to CKS0 CMF Set to 1 when RTCNT RTCOR CMIE Cleared to 0 Enables or disables interrupt requests P8DDR P81DDR Set to 1 CS3 output Set to 0 or 1 ABWCR ABW3 Cleared to 0 DRAM Interface To set up area 3 for connection to 16 bit wide DRAM initialize RTCOR RTMCSR and RFSHCR in t...

Page 171: ... to 1 7 3 2 DRAM Refresh Control Refresh Request Interval and Refresh Cycle Execution The refresh request interval is determined by the settings of RTCOR and bits CKS2 to CKS0 in RTMCSR Figure 7 2 illustrates the refresh request interval Figure 7 2 Refresh Request Interval RCYCE 1 Refresh requests are generated at regular intervals as shown in figure 7 2 but the refresh cycle is not actually execu...

Page 172: ... refresh cycle but goes into the refresh request pending state Note this point when using a DRAM that requires a refresh cycle for initialization When a refresh request occurs in the refresh request pending state the refresh controller acquires the bus right then executes a refresh cycle If another refresh request occurs during execution of the refresh cycle it is ignored Figure 7 3 State Transiti...

Page 173: ...A6 A5 A4 A3 A2 A1 A0 address output M9 M8 0 A23 to A10 A9 A9 A16 A15 A14 A13 A12 A11 A10 A0 M9 M8 1 A23 to A10 A18 A17 A16 A15 A14 A13 A12 A11 A10 A0 Figure 7 4 Multiplexed Address Output Example without Wait States Address signals during column address output ø A to A A A to A 23 9 0 8 1 T1 T2 T3 A to A Row address 8 1 A to A Column address 16 9 A to A A 23 9 0 Address bus ø A to A A A to A 23 10...

Page 174: ...es Pins DRAM Pin H8 3048 Series Pin CAS WE 0 2WE Mode CAS WE 1 2CAS Mode HWR UW UCAS LWR LW LCAS RD CAS WE CS3 RAS RAS Figure 7 5 1 shows the interface timing for 2WE DRAM Figure 7 5 2 shows the interface timing for 2CAS DRAM Figure 7 5 DRAM Control Signal Output Timing 1 2WE Mode ø CS RAS 3 RD CAS HWR UW LWR LW RFSH AS Read cycle Write cycle Refresh cycle Row Column Row Column Area 3 top address ...

Page 175: ...or details see section 6 3 7 Bus Arbiter Operation Wait State Insertion When bit AST3 is set to 1 in ASTCR bus controller settings can cause wait states to be inserted into bus cycles and refresh cycles For details see section 6 3 5 Wait Modes ø CS RAS 3 HWR UCAS LWR LCAS RD WE RFSH AS Read cycle Write cycle Refresh cycle Row Column Row Column Area 3 top address Note 16 bit access Address bus 161 ...

Page 176: ... CAS and RAS outputs both go high Table 7 7 shows the pin states in software standby mode Figure 7 6 shows the signal output timing Table 7 7 Pin States in Software Standby Mode 1 PSRAME 0 DRAME 1 Software Standby Mode SRFMD 0 SRFMD 1 self refresh mode Signal CAS WE 0 CAS WE 1 CAS WE 0 CAS WE 1 HWR High impedance High impedance High Low LWR High impedance High impedance High Low RD High impedance ...

Page 177: ...S HWR UW LWR LW RFSH 3 High High ø CS RAS RD WE RFSH 3 Software standby mode High impedance Oscillator settling time a 2 mode SRFMD 1 b 2 mode SRFMD 1 Software standby mode High impedance Oscillator settling time WE CAS Address bus Address bus HWR UCAS LWR LCAS 163 www DataSheet4U com ...

Page 178: ... takes a certain length of time which can be measured by using an interrupt from another timer module or by counting the number of times RTMCSR bit 7 CMF is set Note that no refresh cycle is executed for the first refresh request after exit from the reset state or standby mode the first time the CMF flag is set see figure 7 3 When using this example check the DRAM device characteristics carefully ...

Page 179: ... 2WE 1 Mbit DRAM 1 Mbyte Mode Set area 3 for 16 bit access Set P8 DDR to 1 for output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H 23 in RFSHCR Wait for DRAM to be initialized DRAM can be accessed CS 1 3 165 www DataSheet4U com ...

Page 180: ... addresses Its address area is H 600000 to H 67FFFF Figure 7 9 Interconnections and Address Map for 2WE 4 Mbit DRAM Example A A A A A A A A 8 7 6 5 4 3 2 1 CS RD HWR LWR 3 D to D0 15 A A A A A A A A 7 6 5 4 3 2 1 0 RAS CAS UW LW OE I O to I O 15 0 A A 18 17 A A 9 8 H 600000 H 67FFFF H 680000 H 7FFFFF H8 3048 Series 2 4 Mbit DRAM with 10 bit row address 8 bit column address and 16 bit organization ...

Page 181: ...Bit Row Address and 8 Bit Column Address 16 Mbyte Mode Set area 3 for 16 bit access Set P8 DDR to 1 for output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H 23 in RFSHCR Wait for DRAM to be initialized DRAM can be accessed CS 1 3 167 www DataSheet4U com ...

Page 182: ...umn addresses Its address area is H 600000 to H 67FFFF Figure 7 11 Interconnections and Address Map for 2CAS 4 Mbit DRAM Example A A A A A A A A A 9 8 7 6 5 4 3 2 1 CS HWR LWR RD 3 D to D0 A A A A A A A A A 8 7 6 5 4 3 2 1 0 RAS UCAS LCAS WE OE I O to I O 15 0 15 H 600000 H 67FFFF H 680000 H 7FFFFF H8 3048 Series 2 4 Mbit DRAM with 9 bit row address 9 bit column address and 16 bit organization CAS...

Page 183: ...Bit Row Address and 9 Bit Column Address 16 Mbyte Mode Set area 3 for 16 bit access Set P8 DDR to 1 for output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H 3B in RFSHCR Wait for DRAM to be initialized DRAM can be accessed CS 1 3 169 www DataSheet4U com ...

Page 184: ...column addresses Both chips must be refreshed simultaneously so the RFSH pin must be used Figure 7 13 Interconnections and Address Map for Multiple 2CAS 4 Mbit DRAM Chips Example H 600000 H 67FFFF H 680000 H 6FFFFF H 700000 H 7FFFFF A to A RAS UCAS LCAS WE OE I O to I O 15 0 8 0 No 1 A to A RAS UCAS LCAS I O to I O 15 0 8 0 No 2 WE OE A A to A 19 9 1 CS HWR LWR RD RFSH 3 D to D 15 0 H8 3048 Series...

Page 185: ... with 9 Bit Row Address and 9 Bit Column Address 16 Mbyte Mode Set area 3 for 16 bit access Set P8 DDR to 1 for CS output 1 3 Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H 3F in RFSHCR Wait for DRAM to be initialized DRAM can be accessed 171 www DataSheet4U com ...

Page 186: ...o static RAM read write cycles and refresh cycles are the same as for DRAM see table 7 4 The state transitions are as shown in figure 7 3 Pseudo Static RAM Control Signals Figure 7 15 shows the control signals for pseudo static RAM read write and refresh cycles Figure 7 15 Pseudo Static RAM Control Signal Output Timing ø CS RD HWR LWR RFSH AS 3 Read cycle Write cycle Refresh cycle Area 3 top addre...

Page 187: ...tion After the SRFMD bit is set to 1 in RFSHCR when a transition to software standby mode occurs the H8 3048 Series CS3 output goes high and its RFSH output goes low so that the pseudo static RAM self refresh function can be used On exit from software standby mode the RFSH output goes high Table 7 8 shows the pin states in software standby mode Figure 7 16 shows the signal output timing Table 7 8 ...

Page 188: ...operate in hardware standby mode In software standby mode RTCNT is initialized but RFSHCR RTMCSR bits 5 to 3 and RTCOR retain their settings prior to the transition to software standby mode ø CS RD HWR LWR RFSH 3 High Software standby mode Oscillator settling time High impedance High impedance High impedance High impedance Address bus 174 www DataSheet4U com ...

Page 189: ...example of a circuit for generating an OE RFSH signal Check the device characteristics carefully and design a circuit that fits them Figure 7 18 shows a setup procedure to be followed by a program Figure 7 17 Interconnection to Pseudo Static RAM with OE RFSH Signal Example H8 3048 Series PSRAM RD RFSH OE RFSH 175 www DataSheet4U com ...

Page 190: ...Setup Procedure for Pseudo Static RAM Set P8 DDR to 1 for CS output 1 3 Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H 47 in RFSHCR Wait for PSRAM to be initialized PSRAM can be accessed 176 www DataSheet4U com ...

Page 191: ...hich the values match when RTCNT is updated from the matching value to a new value Accordingly when RTCNT and RTCOR match the compare match signal is not generated until the next counter clock pulse Figure 7 19 shows the timing Figure 7 19 Timing of Setting of CMF Flag Operation in Power Down State The interval timer function operates in sleep mode It does not operate in hardware standby mode In s...

Page 192: ... an RTCNT write cycle clearing of the counter takes priority and the write is not performed See figure 7 20 Figure 7 20 Contention between RTCNT Write and Clear ø Address bus RTCNT T1 T2 T3 RTCNT address N H 00 RTCNT write cycle by CPU Internal write signal Counter clear signal 178 www DataSheet4U com ...

Page 193: ...RTCNT write cycle writing takes priority and RTCNT is not incremented See figure 7 21 Figure 7 21 Contention between RTCNT Write and Increment T1 T2 T3 RTCNT address N M ø Address bus RTCNT RTCNT write cycle by CPU Internal write signal RTCNT input clock Counter write data 179 www DataSheet4U com ...

Page 194: ... the relation between the time of the switchover by writing to bits CKS2 to CKS0 and the operation of RTCNT The RTCNT input clock is generated from the internal clock source by detecting the falling edge of the internal clock If a switchover is made from a high clock source to a low clock source as in case No 3 in table 7 9 the switchover will be regarded as a falling edge an RTCNT clock pulse wil...

Page 195: ...luding switchovers from a low clock source to the halted state and from the halted state to a low clock source 2 Including switchover from the halted state to a high clock source Old clock source New clock source RTCNT N N 1 CKS bits rewritten RTCNT clock Old clock source New clock source RTCNT N N 1 CKS bits rewritten N 2 RTCNT clock 181 www DataSheet4U com ...

Page 196: ...witchover Notes 1 Including switchover from a high clock source to the halted state 2 The switchover is regarded as a falling edge causing RTCNT to increment Old clock source New clock source RTCNT clock RTCNT N N 1 CKS bits rewritten N 2 2 Old clock source New clock source RTCNT clock RTCNT N N 1 CKS bits rewritten N 2 182 www DataSheet4U com ...

Page 197: ...n the DRAM enable bit DRAME or PSRAM enable bit PSRAME in the refresh control register RFSHCR is cleared to 0 after being set to 1 Figure 7 23 Operation when DRAM PSRAM Connection is Switched Refresh cycles are not executed while the bus is released during software standby mode and when a bus cycle is greatly prolonged by insertion of wait states When these conditions occur other means of refreshi...

Page 198: ...mode see figure 7 25 When using software standby mode clear the BRLE bit to 0 in BRCR before executing the SLEEP instruction When making a transition to self refresh mode the strobe waveform output may not be guaranteed due to the same kind of contention This too can be prevented by clearing the BRLE bit to 0 in BRCR Figure 7 25 Contention between Bus Released State and Software Standby Mode 184 ø...

Page 199: ... address or vice versa Maximum four channels available Selection of I O mode idle mode or repeat mode Full address mode 24 bit source and destination addresses Maximum two channels available Selection of normal mode or block transfer mode Directly addressable 16 Mbyte address space Selection of byte or word transfer Activation by internal interrupts external requests or auto request depending on t...

Page 200: ... Address buffer Arithmetic logic unit MAR0A MAR0B MAR1A MAR1B IOAR0A IOAR0B IOAR1A IOAR1B ETCR0A ETCR0B ETCR1A ETCR1B Internal address bus Internal interrupts Interrupt signals Internal data bus Module data bus Legend DTCR MAR IOAR ETCR Data transfer control register Memory address register I O address register Execute transfer count register Channel 0A Channel 0B Channel 1A Channel 1B Channel 0 C...

Page 201: ...Transfers one byte or one word per request Holds the memory address fixed Executes 1 to 65 536 transfers Repeat mode Transfers one byte or one word per request Increments or decrements the memory address by 1 or 2 Executes a specified number 1 to 255 of transfers then returns to the initial state and continues Normal mode Auto request Retains the transfer request internally Executes a specified nu...

Page 202: ...est for DMAC channel 0 Transfer end 0 TEND0 Output Transfer end on DMAC channel 0 1 DMA request 1 DREQ1 Input External request for DMAC channel 1 Transfer end 1 TEND1 Output Transfer end on DMAC channel 1 Note External requests cannot be made to channel A in short address mode 8 1 5 Register Configuration Table 8 3 lists the DMAC registers 188 www DataSheet4U com ...

Page 203: ... count register 0BL ETCR0BL R W Undetermined H FF2F Data transfer control register 0B DTCR0B R W H 00 1 H FF30 Memory address register 1AR MAR1AR R W Undetermined H FF31 Memory address register 1AE MAR1AE R W Undetermined H FF32 Memory address register 1AH MAR1AH R W Undetermined H FF33 Memory address register 1AL MAR1AL R W Undetermined H FF36 I O address register 1A IOAR1A R W Undetermined H FF3...

Page 204: ...d automatically from the activation source An MAR consists of four 8 bit registers designated MARR MARE MARH and MARL All bits of MARR are reserved they cannot be modified and are always read as 1 An MAR functions as a source or destination address register depending on how the DMAC is activated as a destination address register if activation is by a receive data full interrupt from the serial com...

Page 205: ...ialized by a reset or in standby mode 8 2 3 Execute Transfer Count Registers ETCR An execute transfer count register ETCR is a 16 bit readable writable register that specifies the number of transfers to be executed These registers function in one way in I O mode and idle mode and another way in repeat mode I O mode and idle mode In I O mode and idle mode ETCR functions as a 16 bit counter The coun...

Page 206: ...ches H 00 the value in ETCRL is reloaded into ETCRH and the same operation is repeated The ETCRs are not initialized by a reset or in standby mode Bit Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 R W 2 R W 1 R W Undetermined Transfer counter ETCRH Bit Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 R W 2 R W 1 R W Undetermined Initial count ETCRL 192 www DataSheet4U com ...

Page 207: ...escription 0 Data transfer is disabled In I O mode or idle mode DTE is cleared to 0 Initial value when the specified number of transfers have been completed 1 Data transfer is enabled If DTIE is set to 1 a CPU interrupt is requested when DTE is cleared to 0 Bit Initial value Read Write 7 DTE 0 R W 6 DTSZ 0 R W 5 DTID 0 R W 4 RPE 0 R W 3 DTIE 0 R W 0 DTS0 0 R W 2 DTS2 0 R W 1 DTS1 0 R W Data transf...

Page 208: ...cremented by 1 after each transfer If DTSZ 1 MAR is incremented by 2 after each transfer 1 MAR is decremented after each data transfer If DTSZ 0 MAR is decremented by 1 after each transfer If DTSZ 1 MAR is decremented by 2 after each transfer MAR is not incremented or decremented in idle mode Bit 4 Repeat Enable RPE Selects whether to transfer data in I O mode idle mode or repeat mode Bit 4 Bit 3 ...

Page 209: ... match input capture A interrupt from ITU channel 1 1 0 Compare match input capture A interrupt from ITU channel 2 1 Compare match input capture A interrupt from ITU channel 3 1 0 0 Transmit data empty interrupt from SCI channel 0 1 Receive data full interrupt from SCI channel 0 1 0 Falling edge of DREQ input channel B Transfer in full address mode channel A 1 Low level of DREQ input channel B Tra...

Page 210: ...e always read as 1 The MAR value is incremented or decremented each time one byte or word is transferred automatically updating the source or destination memory address For details see section 8 3 4 Data Transfer Control Registers DTCR The MARs are not initialized by a reset or in standby mode 8 3 2 I O Address Registers IOAR The I O address registers IOARs are not used in full address mode Bit In...

Page 211: ...ock transfer mode Normal mode ETCRA ETCRB Is not used in normal mode In normal mode ETCRA functions as a 16 bit transfer counter The count is decremented by 1 each time one transfer is executed The transfer ends when the count reaches H 0000 ETCRB is not used Bit Initial value Read Write 14 R W 12 R W 10 R W 8 R W 6 R W 0 R W 4 R W 2 R W Transfer counter Undetermined 15 R W 13 R W 11 R W 9 R W 7 R...

Page 212: ...de ETCRB functions as a 16 bit block transfer counter ETCRB is decremented by 1 each time one block is transferred The transfer ends when the count reaches H 0000 The ETCRs are not initialized by a reset or in standby mode Bit Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 R W 2 R W 1 R W Undetermined Block size counter ETCRAH Bit Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 ...

Page 213: ... 6 DTSZ 0 R W 5 SAID 0 R W 4 SAIDE 0 R W 3 DTIE 0 R W 0 DTS0A 0 R W 2 DTS2A 0 R W 1 DTS1A 0 R W Data transfer enable Enables or disables data transfer Enables or disables the CPU interrupt at the end of the transfer Data transfer size Selects byte or word size Source address increment decrement Data transfer select 2A and 1A These bits must both be set to 1 Data transfer interrupt enable Source ad...

Page 214: ...ata transfer is enabled If DTIE is set to 1 a CPU interrupt is requested when DTE is cleared to 0 Bit 6 Data Transfer Size DTSZ Selects the data size of each transfer Bit 6 DTSZ Description 0 Byte size transfer Initial value 1 Word size transfer Bit 5 Source Address Increment Decrement SAID and Bit 4 Source Address Increment Decrement Enable SAIDE These bits select whether the source address regis...

Page 215: ...equested by DTE is enabled Bits 2 and 1 Data Transfer Select 2A and 1A DTS2A DTS1A A channel operates in full address mode when DTS2A and DTS1A are both set to 1 Bit 0 Data Transfer Select 0A DTS0A Selects normal mode or block transfer mode Bit 0 DTS0A Description 0 Normal mode Initial value 1 Block transfer mode Operations in these modes are described in sections 8 4 5 Normal Mode and 8 4 6 Block...

Page 216: ...ption 0 Data transfer is disabled DTME is cleared to 0 when an NMI interrupt Initial value occurs 1 Data transfer is enabled Bit Initial value Read Write 7 DTME 0 R W 6 0 R W 5 DAID 0 R W 4 DAIDE 0 R W 3 TMS 0 R W 0 DTS0B 0 R W 2 DTS2B 0 R W 1 DTS1B 0 R W Data transfer master enable Enables or disables data transfer together with the DTE bit and is cleared to 0 by an interrupt Reserved bit Destina...

Page 217: ...r each data transfer If DTSZ 0 MARB is incremented by 1 after each data transfer If DTSZ 1 MARB is incremented by 2 after each data transfer 1 0 MARB is held fixed 1 MARB is decremented after each data transfer If DTSZ 0 MARB is decremented by 1 after each data transfer If DTSZ 1 MARB is decremented by 2 after each data transfer Bit 3 Transfer Mode Select TMS Selects whether the source or destinat...

Page 218: ...EQ Block transfer mode Bit 2 Bit 1 Bit 0 DTS2B DTS1B DTS0B Description 0 0 0 Compare match input capture A interrupt from ITU channel 0 Initial value 1 Compare match input capture A interrupt from ITU channel 1 1 0 Compare match input capture A interrupt from ITU channel 2 1 Compare match input capture A interrupt from ITU channel 3 1 0 0 Cannot be used 1 Cannot be used 1 0 Falling edge of DREQ 1 ...

Page 219: ...or word is transferred per request A designated number of these transfers are executed A CPU interrupt can be requested at completion of the designated number of transfers One 24 bit address and one 8 bit address are specified The addresses are held fixed The transfer direction is determined automatically from the activation source Repeat Mode One byte or word is transferred per request A designat...

Page 220: ...til the designated number of transfers have been completed External request One byte or word is transferred per request A designated number of these transfers are executed A CPU interrupt can be requested at completion of the designated number of transfers Both addresses are 24 bit addresses Block Transfer Mode One block of a specified size is transferred per request A designated number of block t...

Page 221: ...CI 0 Receive Data Full Other Register Interrupt Activation Initial Setting Operation Destination Source Destination or Incremented or address address source address decremented register register once per transfer Source Destination Source or Held fixed address address destination register register address Transfer counter Number of Decremented transfers once per transfer until H 0000 is reached an...

Page 222: ... 536 obtained by setting ETCR to H 0000 Transfers can be requested activated by compare match input capture A interrupts from ITU channels 0 to 3 transmit data empty and receive data full interrupts from SCI channel 0 and external request signals For the detailed settings see section 8 2 4 Data Transfer Control Registers DTCR Address T Address B Transfer Legend L initial setting of MAR N initial s...

Page 223: ...address specified in MAR to the address specified in IOAR otherwise Table 8 7 indicates the register functions in idle mode Set source and destination addresses Set transfer count Read DTCR Set DTCR I O mode I O mode setup 1 2 3 4 1 2 3 4 Set the source and destination addresses in MAR and IOAR The transfer direction is determined automatically from the activation source Set the transfer count in ...

Page 224: ...per transfer until H 0000 is reached and transfer ends Legend MAR Memory address register IOAR I O address register ETCR Execute transfer count register MAR and IOAR specify the source and destination addresses MAR specifies a 24 bit source or destination address IOAR specifies the lower 8 bits of a fixed address The upper 16 bits are all 1s MAR and IOAR are not incremented or decremented Figure 8...

Page 225: ...ection 8 2 4 Data Transfer Control Registers DTCR Figure 8 5 shows a sample setup procedure for idle mode Figure 8 5 Idle Mode Setup Procedure Example Set source and destination addresses Set transfer count Read DTCR Set DTCR Idle mode Idle mode setup 1 2 3 4 1 2 3 4 Set the source and destination addresses in MAR and IOAR The transfer direction is deter mined automatically from the activation sou...

Page 226: ...AR if activated by an SCI channel 0 receive data full interrupt and from the address specified in MAR to the address specified in IOAR otherwise Table 8 8 indicates the register functions in repeat mode Table 8 8 Register Functions in Repeat Mode Function Activated by SCI 0 Receive Data Full Other Register Interrupt Activation Initial Setting Operation Destination Source Destination or Incremented...

Page 227: ...0 After DTE is cleared to 0 if the CPU sets DTE to 1 again transfers resume from the state at which DTE was cleared No CPU interrupt is requested As in I O mode MAR and IOAR specify the source and destination addresses MAR specifies a 24 bit source or destination address IOAR specifies the lower 8 bits of a fixed address The upper 16 bits are all 1s IOAR is not incremented or decremented Figure 8 ...

Page 228: ... 8 7 Repeat Mode Setup Procedure Example Set source and destination addresses Set transfer count Read DTCR Set DTCR Repeat mode Repeat mode 1 2 3 4 1 2 3 4 Set the source and destination addresses in MAR and IOAR The transfer direction is determined automatically from the activation source Set the transfer count in both ETCRH and ETCRL Read DTCR while the DTE bit is cleared to 0 Select byte size o...

Page 229: ... per transfers transfer Legend MARA Memory address register A MARB Memory address register B ETCRA Execute transfer count register A The source and destination addresses are both 24 bit addresses MARA specifies the source address MARB specifies the destination address MARA and MARB can be independently incremented decremented or held fixed as data is transferred The transfer count is specified as ...

Page 230: ...DMAC releases the bus temporarily after each transfer In burst mode the DMAC keeps the bus until the transfers are completed unless there is a bus request from a higher priority bus master For the detailed settings see section 8 3 4 Data Transfer Control Registers DTCR Address T Address B Transfer Legend L L N T B T B SAID DAID Address T Address B A B A A B B initial setting of MARA initial settin...

Page 231: ...DE bits to select whether MARB is incremented decremented or held fixed Select the DMAC activation source with bits DTS2B to DTS0B Clear the DTE bit to 0 Select byte or word size with the DTSZ bit Set the SAID and SAIDE bits to select whether MARA is incremented decremented or held fixed Set or clear the DTIE bit to enable or disable the CPU interrupt at the end of the transfer Clear the DTS0A bit...

Page 232: ...til H 00 is reached then reloaded from ETCRAL Initial block size Block size Held fixed Block transfer Number of block Decremented once per counter transfers block transfer until H 0000 is reached and the transfer ends Legend MARA Memory address register A MARB Memory address register B ETCRA Execute transfer count register A ETCRB Execute transfer count register B The source and destination addres...

Page 233: ...n this figure bit TMS is cleared to 0 meaning the block area is the destination Figure 8 10 Operation in Block Transfer Mode T B Transfer Legend L L M N T B T B Address T M bytes or words are transferred per request Address B A A Block 1 Block N B B Block area Block 2 initial setting of MARA initial setting of MARB initial setting of ETCRAH and ETCRAL initial setting of ETCRB L L SAIDE 1 2 M 1 L L...

Page 234: ...uld be initially set to the same value The above operation is repeated until ETCRB reaches H 0000 at which point the DTE bit is cleared to 0 and the transfer ends If the DTIE bit is set to 1 a CPU interrupt is requested at this time Figure 8 11 shows examples of a block transfer with byte data size when the block area is the destination In a the block area address is cycled In b the block area add...

Page 235: ...end transfer ETCRAH ETCRAL MARB MARB ETCRAL ETCRB ETCRB 1 ETCRB H 0000 Start DTE DTME 1 Transfer requested Get bus MARA MARA 1 Read from MARA address Write to MARB address ETCRAH ETCRAH 1 ETCRAH H 00 Release bus Clear DTE to 0 and end transfer ETCRB ETCRB 1 ETCRB H 0000 ETCRAH ETCRAL No No No Yes Yes Yes No No No Yes Yes Yes a DTSZ TMS 0 SAID DAID 0 SAIDE DAIDE 1 b DTSZ TMS 0 SAID 0 SAIDE 1 DAIDE ...

Page 236: ...RB is incremented decremented or held fixed Set or clear the TMS bit to make the block area the source or destination Select the DMAC activation source with bits DTS2B to DTS0B Clear the DTE to 0 Select byte size or word size with the DTSZ bit Set the SAID and SAIDE bits to select whether MARA is incremented decremented or held fixed Set or clear the DTIE bit to enable or disable the CPU interrupt...

Page 237: ...nternal Interrupts When an interrupt request is selected as a DMAC activation source and the DTE bit is set to 1 that interrupt request is not sent to the CPU It is not possible for an interrupt request to activate the DMAC and simultaneously generate a CPU interrupt When the DMAC is activated by an interrupt request the interrupt request flag is cleared automatically If the same interrupt is sele...

Page 238: ...er the current byte or word has been transferred When DREQ goes low the request is held internally until one byte or word has been transferred The TEND signal goes low during the last write cycle In block transfer mode an external request operates as follows Only edge sensitive transfer requests are possible in block transfer mode Each time a high to low transition of the DREQ input is detected a ...

Page 239: ...t reads from the source address and writes to the destination address During these read and write operations the bus is not released even if there is another bus request DMAC cycles comply with bus controller settings in the same way as CPU cycles Figure 8 13 DMA Transfer Bus Timing Example ø RD HWR LWR T1 T2 T1 T2 Td T1 T2 T1 T2 T3 T1 T2 T3 T1 T2 T1 T2 CPU cycle DMAC cycle word transfer CPU cycle...

Page 240: ...cess area The DMAC continues the transfer while the DREQ pin is held low Figure 8 14 Bus Timing of DMA Transfer Requested by Low DREQ Input ø DREQ RD HWR TEND T1 T2 T3 Td T1 T2 T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2 LWR CPU cycle DMAC cycle CPU cycle DMAC cycle last transfer cycle CPU cycle Source address Destination address Source address Destination address Address bus 226 www DataSheet4U com ...

Page 241: ... when the transfer is requested until the DMAC starts operating The DREQ pin is not sampled during the time between the transfer request and the start of the transfer In short address mode and normal mode the pin is next sampled at the end of the read cycle In block transfer mode the pin is next sampled at the end of one block transfer T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 ø RD CPU cycle...

Page 242: ...of DREQ in normal mode Figure 8 16 Timing of DMAC Activation by Falling Edge of DREQ in Normal Mode ø DREQ RD HWR T2 T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2 Td T1 T2 LWR CPU cycle DMAC cycle CPU cycle DMAC cycle Minimum 4 states Next sampling point Address bus 228 www DataSheet4U com ...

Page 243: ...tive low DREQ input in normal mode Figure 8 17 Timing of DMAC Activation by Low DREQ Level in Normal Mode DREQ RD HWR ø LWR T2 T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2 T1 T2 T1 CPU cycle DMAC cycle CPU cycle Minimum 4 states Next sampling point Address bus 229 www DataSheet4U com ...

Page 244: ...ck transfer mode Figure 8 18 Timing of DMAC Activation by Falling Edge of DREQ in Block Transfer Mode ø DREQ RD HWR TEND T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 Td T1 T2 DMAC cycle DMAC cycle CPU cycle Next sampling Minimum 4 states End of 1 block transfer LWR Address bus 230 www DataSheet4U com ...

Page 245: ...hannel releases the bus 3 After each transfer in short address mode and each externally requested or cycle steal transfer in normal mode the DMAC releases the bus and returns to step 1 After releasing the bus if there is a transfer request for another channel the DMAC requests the bus again 4 After completion of a burst mode transfer or after transfer of one block in block transfer mode the DMAC r...

Page 246: ...equest at this point the DMAC requests the bus right again Figure 8 20 shows an example of the timing of insertion of a refresh cycle during a burst transfer on channel 0 Figure 8 20 Bus Timing of Refresh Controller and DMAC ø RD T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2 Td T1 T2 T1 T2 DMAC cycle channel 1 CPU cycle DMAC cycle channel 0A CPU cycle DMAC cycle channel 1 Address bus HWR LWR ø RD HWR LWR T1 T2...

Page 247: ...ts the DTME bit to 1 again Check that the DTE bit is set to 1 and the DTME bit is cleared to 0 before setting the DTME bit to 1 Figure 8 21 shows the procedure for resuming a DMA transfer in normal mode on channel 0 after the transfer was halted by NMI input Figure 8 21 Procedure for Resuming a DMA Transfer Halted by NMI Example For information about NMI interrupts in block transfer mode see secti...

Page 248: ...In full address mode the DTME bit can be used for the same purpose Figure 8 22 shows the procedure for aborting a DMA transfer by software Figure 8 22 Procedure for Aborting a DMA Transfer DMA transfer abort Set DTCR DMA transfer aborted 1 1 Clear the DTE bit to 0 in DTCR To avoid generating an interrupt when aborting a DMA transfer clear the DTIE bit to 0 simultaneously 234 www DataSheet4U com ...

Page 249: ...mode follow the setup procedure for the relevant mode Figure 8 23 Procedure for Exiting Full Address Mode Example Exiting full address mode Halt the channel Initialize DTCRB Initialize DTCRA Initialized and halted 1 2 3 1 2 3 Clear the DTE bit to 0 in DTCRA or wait for the transfer to end and the DTE bit to be cleared to 0 Clear all DTCRB bits to 0 Clear all DTCRA bits to 0 235 www DataSheet4U com...

Page 250: ...he DMAC is initialized and halts DMAC operations continue in sleep mode Figure 8 24 shows the timing of a cycle steal transfer in sleep mode Figure 8 24 Timing of Cycle Steal Transfer in Sleep Mode ø Address bus RD HWR LWR 2 Td T T2 1 T2 T d T1 T 2 T1 T 2 T 1 T CPU cycle DMAC cycle DMAC cycle Sleep mode d T 236 www DataSheet4U com ...

Page 251: ...nsfer on channel 1B Low Each interrupt is enabled or disabled by the DTIE bit in the corresponding data transfer control register DTCR Separate interrupt signals are sent to the interrupt controller The interrupt priority order among channels is channel 0 channel 1 and channel A channel B Figure 8 25 shows the DMA end interrupt logic An interrupt is requested whenever DTE 0 and DTIE 1 Figure 8 25 ...

Page 252: ...s register can be accessed as longword data at the MARR address Example MOV L LBL ER0 MOV L ER0 MARR Four byte accesses are performed Note that the CPU may release the bus between the second byte MARE and third byte MARH Memory address registers should be written and read only when the DMAC is halted 8 6 4 Note on Full Address Mode Setup Full address mode is controlled by two registers DTCRA and D...

Page 253: ...MAC is halted and the selected activating source cannot generate a CPU interrupt If the DMAC is halted by an NMI interrupt for example the selected activating source cannot generate CPU interrupts To terminate DMAC operations in this state clear the DTE bit to 0 to allow CPU interrupts to be requested To continue DMAC operations carry out steps 2 and 4 in figure 8 26 before and after setting the D...

Page 254: ...he transfer is halted in the middle of a block the activating interrupt flag is cleared to 0 The activation request is not held pending While the DTE bit is set to 1 and the DTME bit is cleared to 0 the DMAC is halted and does not accept activating interrupt requests If an activating interrupt occurs in this state the DMAC does not operate and does not hold the transfer request pending internally ...

Page 255: ...I that clears the DTME bit if this halts a channel for which the DMAC has a transfer request pending internally a dead cycle may occur This dead cycle does not update the halted channel s address register or counter value Figure 8 27 shows an example in which an auto requested transfer in cycle steal mode on channel 0 is aborted by clearing the DTE bit in channel 0 Figure 8 27 Bus Timing at Abort ...

Page 256: ...ion to these registers ports 2 4 and 5 have an input pull up MOS control register PCR for switching input pull up MOS transistors on and off Ports 1 to 6 and port 8 can drive one TTL load and a 90 pF capacitive load Ports 9 A and B can drive one TTL load and a 30 pF capacitive load Ports 1 to 6 and 8 to B can drive a darlington pair Ports 1 2 5 and B can drive LEDs with 10 mA current sink Pins P82...

Page 257: ...ddress output A19 to A16 Address output A19 to Generic Input pull up A19 to A16 A16 and 4 bit generic input MOS input DDR 0 output Can drive LEDs generic input DDR 1 address output Port 6 7 bit I O port P66 LWR Bus control signal output LWR HWR RD AS Generic P65 HWR input P64 RD output P63 AS P62 BACK Bus control signal input output BACK BREQ WAIT and P61 BREQ 3 bit generic input output P60 WAIT P...

Page 258: ...t and ITU input ITU input TP6 to TIOCB1 A22 CS5 output TIOCA2 output TIOCA2 and output and output TP4 ITU PA4 TP4 TIOCB1 TIOCB1 TIOCA2 TIOCA2 input and TIOCA1 A23 CS6 TIOCA1 CS4 to TIOCA1 TIOCB1 TIOCB1 output CS6 output and address output TIOCA1 TIOCA1 TIOCA2 generic input A23 to A21 CS4 to CS6 address TIOCB1 output CS4 to CS6 output and output TIOCA1 output generic A23 to A21 and and generic inpu...

Page 259: ...utput A7 to A0 or generic input In mode 7 single chip mode port 1 is a generic input output port When DRAM is connected to area 3 A7 to A0 output row and column addresses in read and write cycles For details see section 7 Refresh Controller Pins in port 1 can drive one TTL load and a 90 pF capacitive load They can also drive a darlington transistor pair Figure 9 1 Port 1 Pin Configuration Port 1 P...

Page 260: ...d Port 1 functions as an address bus Modes 5 and 6 Expanded Modes with On Chip ROM Enabled A pin in port 1 becomes an address output pin if the corresponding P1DDR bit is set to 1 and a generic input pin if this bit is cleared to 0 Mode 7 Single Chip Mode Port 1 functions as an input output port A pin in port 1 becomes an output pin if the corresponding P1DDR bit is set to 1 and an input pin if th...

Page 261: ...readable writable register that stores port 1 output data When this register is read the pin logic level of a pin is read for bits for which the P1DDR setting is 0 and the P1DR value is read for bits for which the P1DDR setting is 1 P1DR is initialized to H 00 by a reset and in hardware standby mode In software standby mode it retains its previous setting Bit Initial value Read Write 7 P1 0 R W Po...

Page 262: ...or details see section 7 Refresh Controller Port 2 has software programmable built in pull up MOS Pins in port 2 can drive one TTL load and a 90 pF capacitive load They can also drive a darlington transistor pair Figure 9 2 Port 2 Pin Configuration Port 2 P2 A P2 A P2 A P2 A P2 A P2 A P2 A P2 A 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 P2 input output P2 input output P2 input output P2 input output P2...

Page 263: ...t be modified Port 2 functions as an address bus Modes 5 and 6 Expanded Modes with On Chip ROM Enabled Following a reset port 2 is an input port A pin in port 2 becomes an address output pin if the corresponding P2DDR bit is set to 1 and a generic input port if this bit is cleared to 0 Mode 7 Single Chip Mode Port 2 functions as an input output port A pin in port 2 becomes an output port if the co...

Page 264: ...previous setting Port 2 Input Pull Up MOS Control Register P2PCR P2PCR is an 8 bit readable writable register that controls the MOS input pull up transistors in port 2 In modes 5 to 7 when a P2DDR bit is cleared to 0 selecting generic input if the corresponding bit from P27PCR to P20PCR is set to 1 the input pull up MOS is turned on P2PCR is initialized to H 00 by a reset and in hardware standby m...

Page 265: ...Up MOS States Port 2 Mode Reset Hardware Standby Mode Software Standby Mode Other Modes 1 Off Off Off Off 2 3 4 5 Off Off On off On off 6 7 Legend Off The input pull up MOS is always off On off The input pull up MOS is on if P2PCR 1 and P2DDR 0 Otherwise it is off 252 www DataSheet4U com ...

Page 266: ... of port 3 Table 9 5 Port 3 Registers Address Name Abbreviation R W Initial Value H FFC4 Port 3 data direction register P3DDR W H 00 H FFC6 Port 3 data register P3DR R W H 00 Note Lower 16 bits of the address Port 3 P3 D P3 D P3 D P3 D P3 D P3 D P3 D P3 D 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 P3 input output P3 input output P3 input output P3 input output P3 input output P3 input output P3 input o...

Page 267: ...ftware standby mode Port 3 Data Register P3DR P3DR is an 8 bit readable writable register that stores output data for pins P37 to P30 When a bit in P3DDR is set to 1 if port 3 is read the value of the corresponding P3DR bit is returned When a bit in P3DDR is cleared to 0 if port 3 is read the corresponding pin level is read P3DR is initialized to H 00 by a reset and in hardware standby mode In sof...

Page 268: ...t output port Port 4 has software programmable built in pull up MOS Pins in port 4 can drive one TTL load and a 90 pF capacitive load They can also drive a darlington transistor pair Figure 9 4 Port 4 Pin Configuration Port 4 P4 D P4 D P4 D P4 D P4 D P4 D P4 D P4 D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 P4 input output D7 input output P4 input output D6 input output P4 input output D5 input output P4 inp...

Page 269: ... corresponding P4DDR bit is set to 1 and an input port if this bit is cleared to 0 When at least one area is designated as a 16 bit access area selecting 16 bit bus mode port 4 functions as part of the data bus Mode 7 Single Chip Mode Port 4 functions as an input output port A pin in port 4 becomes an output port if the corresponding P4DDR bit is set to 1 and an input port if this bit is cleared t...

Page 270: ...able writable register that controls the MOS input pull up transistors in port 4 In mode 7 single chip mode and in 8 bit bus mode in modes 1 to 6 expanded modes when a P4DDR bit is cleared to 0 selecting generic input if the corresponding P4PCR bit is set to 1 the input pull up MOS transistor is turned on P4PCR is initialized to H 00 by a reset and in hardware standby mode In software standby mode...

Page 271: ...tates Port 4 Hardware Software Mode Reset Standby Mode Standby Mode Other Modes 1 to 6 8 bit bus mode Off Off On off On off 16 bit bus mode Off Off 7 On off On off Legend Off The input pull up MOS transistor is always off On off The input pull up MOS transistor is on if P4PCR 1 and P4DDR 0 Otherwise it is off 258 www DataSheet4U com ...

Page 272: ...a 90 pF capacitive load They can also drive an LED or a darlington transistor pair Figure 9 5 Port 5 Pin Configuration 9 6 2 Register Descriptions Table 9 8 summarizes the registers of port 5 Table 9 8 Port 5 Registers Initial Value Address Name Abbreviation R W Modes 1 to 4 Modes 5 to 7 H FFC8 Port 5 data direction register P5DDR W H FF H F0 H FFCA Port 5 data register P5DR R W H F0 H F0 H FFDB P...

Page 273: ...return 1 when read P5DDR is initialized to H F0 by a reset and in hardware standby mode In software standby mode it retains its previous setting so if a P5DDR bit is set to 1 the corresponding pin maintains its output state in software standby mode Port 5 Data Register P5DR P5DR is an 8 bit readable writable register that stores output data for pins P53 to P50 When a bit in P5DDR is set to 1 if po...

Page 274: ... to H F0 by a reset and in hardware standby mode In software standby mode it retains its previous setting Table 9 9 summarizes the states of the input pull ups MOS in each mode Table 9 9 Input Pull Up MOS Transistor States Port 5 Mode Reset Hardware Standby Mode Software Standby Mode Other Modes 1 Off Off Off Off 2 3 4 5 Off Off On off On off 6 7 Legend Off The input pull up MOS transistor is alwa...

Page 275: ...a 30 pF capacitive load They can also drive a darlington transistor pair Figure 9 6 Port 6 Pin Configuration 9 7 2 Register Descriptions Table 9 10 summarizes the registers of port 6 Table 9 10 Port 6 Registers Initial Value Address Name Abbreviation R W Mode 1 to 5 Mode 6 7 H FFC9 Port 6 data direction register P6DDR W H F8 H 80 H FFCB Port 6 data register P6DR R W H 80 H 80 Note Lower 16 bits of...

Page 276: ... to 1 the corresponding pin maintains its output state in software standby mode Port 6 Data Register P6DR P6DR is an 8 bit readable writable register that stores output data for pins P66 to P60 When a bit in P6DDR is set to 1 if port 6 is read the value of the corresponding P6DR bit is returned When a bit in P6DDR is cleared to 0 if port 6 is read the corresponding pin level is read Bit 7 is reser...

Page 277: ...ss of P63DDR P63DDR 0 1 Pin function AS output P62 BACK Bit BRLE in BRCR and bit P62DDR select the pin function as follows BRLE 0 1 P62DDR 0 1 Pin function P62 input P62 output BACK output P61 BREQ Bit BRLE in BRCR and bit P61DDR select the pin function as follows BRLE 0 1 P61DDR 0 1 Pin function P61 input P61 output BREQ input P60 WAIT Bits WCE7 to WCE0 in WCER bit WMS1 in WCR and bit P60DDR sele...

Page 278: ...ions are the same in all operating modes Figure 9 7 shows the pin configuration of port 7 Figure 9 7 Port 7 Pin Configuration Port 7 P7 input AN input DA output P7 input AN input DA output P7 input AN input P7 input AN input P7 input AN input P7 input AN input P7 input AN input P7 input AN input 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Port 7 pins 1 0 265 www DataSheet4U com ...

Page 279: ...r Address Name Abbreviation R W Initial Value H FFCE Port 7 data register P7DR R Undetermined Note Lower 16 bits of the address Port 7 Data Register P7DR When port 7 is read the pin levels are always read Bit Initial value Read Write 0 P7 R Note 0 1 P7 R 1 2 P7 R 2 3 P7 R 3 4 P7 R 4 5 P7 R 5 6 P7 R 6 7 P7 R 7 7 0 Determined by pins P7 to P7 266 www DataSheet4U com ...

Page 280: ... is used for input or output For details see section 5 Interrupt Controller Pins in port 8 can drive one TTL load and a 90 pF capacitive load They can also drive a darlington transistor pair Pins P82 to P80 have Schmitt trigger inputs Figure 9 8 Port 8 Pin Configuration Port 8 P8 P8 P8 P8 P8 4 3 2 1 0 0 1 2 3 Port 8 pins CS CS CS CS RFSH 3 2 1 IRQ IRQ IRQ IRQ0 P8 input output P8 input output input...

Page 281: ... pins are input ports In modes 5 and 6 expanded modes with on chip ROM enabled following a reset all four pins are input ports When the refresh controller is enabled P80 is used unconditionally for RFSH output When the refresh controller is disabled P80 becomes a generic input output port according to the P8DDR setting For details see table 9 15 Mode 7 Single Chip Mode Port 8 is a generic input ou...

Page 282: ...P80 When a bit in P8DDR is set to 1 if port 8 is read the value of the corresponding P8DR bit is returned When a bit in P8DDR is cleared to 0 if port 8 is read the corresponding pin level is read Bits 7 to 5 are reserved They cannot be modified and always are read as 1 P8DR is initialized to H E0 by a reset and in hardware standby mode In software standby mode it retains its previous setting Bit I...

Page 283: ...in function P83 input CS1 output IRQ3 input P82 CS2 IRQ2 Bit P82DDR selects the pin function as follows P82DDR 0 1 Pin function P82 input CS2 output IRQ2 input P81 CS3 IRQ1 Bit P81DDR selects the pin function as follows P81DDR 0 1 Pin function P81 input CS3 output IRQ1 input P80 RFSH IRQ0 Bit RFSHE in RFSHCR and bit P80DDR select the pin function as follows RFSHE 0 1 P80DDR 0 1 Pin function P80 in...

Page 284: ...s follows P83DDR 0 1 Pin function P83 input P83 output IRQ3 input P82 IRQ2 Bit P82DDR selects the pin function as follows P82DDR 0 1 Pin function P82 input P82 output IRQ2 input P81 IRQ1 Bit P81DDR selects the pin function as follows P81DDR 0 1 Pin function P81 input P81 output IRQ1 input P80 IRQ0 Bit P80DDR select the pin function as follows P80DDR 0 1 Pin function P80 input P80 output IRQ0 input...

Page 285: ... the pin configuration of port 9 Pins in port 9 can drive one TTL load and a 30 pF capacitive load They can also drive a darlington transistor pair Figure 9 9 Port 9 Pin Configuration 9 10 2 Register Descriptions Table 9 16 summarizes the registers of port 9 Table 9 16 Port 9 Registers Address Name Abbreviation R W Initial Value H FFD0 Port 9 data direction register P9DDR W H C0 H FFD2 Port 9 data...

Page 286: ...output data for pins P95 to P90 When a bit in P9DDR is set to 1 if port 9 is read the value of the corresponding P9DR bit is returned When a bit in P9DDR is cleared to 0 if port 9 is read the corresponding pin level is read Bits 7 and 6 are reserved They cannot be modified and are always read as 1 P9DR is initialized to H C0 by a reset and in hardware standby mode In software standby mode it retai...

Page 287: ...its CKE0 and CKE1 in SCR of SCI0 and bit P94DDR select the pin function as follows CKE1 0 1 C A 0 1 CKE0 0 1 P94DDR 0 1 Pin function P94 P94 SCK0 output SCK0 output SCK0 input input output IRQ4 input P93 RxD1 Bit RE in SCR of SCI1 and bit P93DDR select the pin function as follows RE 0 1 P93DDR 0 1 Pin function P93 input P93 output RxD1 input P92 RxD0 Bit RE in SCR of SCI0 bit SMIF in SCMR and bit ...

Page 288: ...on P91 input P91 output TxD1 output P90 TxD0 Bit TE in SCR of SCI0 bit SMIF in SCMR and bit P90DDR select the pin function as follows SMIF 0 1 TE 0 1 P90DDR 0 1 Pin function P90 input P90 output TxD0 output TxD0 output Note Functions as the TxD0 output pin but there are two states one in which the pin is driven and another in which the pin is at high impedance 275 www DataSheet4U com ...

Page 289: ...in modes 3 4 and 6 one pin is always used for A20 output Usage of pins for TPC ITU and DMAC input and output is described in the sections on those modules For output of address bits A23 to A21 in modes 3 4 and 6 see section 6 2 5 Bus Release Control Register BRCR For output of CS4 to CS6 in modes 1 to 6 see section 6 3 2 Chip Select Signals Pins not assigned to any of these functions are available...

Page 290: ... 6 5 4 3 2 1 0 2 2 1 1 0 0 1 0 A20 PA input output TP output TIOCA input output A output CS4 output PA input output TP output TIOCB input output A output CS5 output PA input output TP output TIOCA input output A output CS6 output 6 5 4 3 2 1 0 Pin functions in modes 3 4 and 6 6 5 4 3 2 1 0 2 1 1 0 0 PA input output TP output TEND output TCLKA input PA input output TP output TIOCB input output TCLK...

Page 291: ...es 3 4 and 6 PA7DDR is fixed at 1 and PA7 functions as an address output pin PADDR is a write only register Its value cannot be read All bits return 1 when read PADDR is initialized to H 00 by a reset and in hardware standby mode in modes 1 2 5 and 7 It is initialized to H 80 by a reset and in hardware standby mode in modes 3 4 and 6 In software standby mode it retains its previous setting If a PA...

Page 292: ...Functions Pin Pin Functions and Selection Method PA7 TP7 The mode setting ITU channel 2 settings bit PWM2 in TMDR and bits IOB2 to TIOCB2 A20 IOB0 in TIOR2 bit NDER7 in NDERA and bit PA7DDR in PADDR select the pin function as follows Mode 1 2 5 7 3 4 6 ITU channel 2 settings 1 in table below 2 in table below PA7DDR 0 1 1 NDER7 0 1 Pin function TIOCB2 output PA7 PA7 TP7 A20 input output output outp...

Page 293: ...t TIOCA2 input TIOCA2 input Note TIOCA2 input when IOA2 1 ITU channel 2 settings 2 1 2 1 PWM2 0 1 IOA2 0 1 IOA1 0 0 1 IOA0 0 1 PA5 TP5 The mode setting bit A22E in BRCR bit CS5E in CSCR ITU channel 1 settings bit TIOCB1 PWM1 in TMDR and bits IOB2 to IOB0 in TIOR1 bit NDER5 in NDERA and bit A22 CS5 PA5DDR in PADDR select the pin function as follows Mode 1 2 5 3 4 6 7 CS5E 0 1 0 1 A22E 1 0 ITU 1 in ...

Page 294: ...t input output output output output input output output output output output input output output TIOCA1 input TIOCA1 input TIOCA1 input Note TIOCA1 input when IOA2 1 ITU channel 1 settings 2 1 2 1 PWM1 0 1 IOA2 0 1 IOA1 0 0 1 IOA0 0 1 PA3 TP3 ITU channel 0 settings bit PWM0 in TMDR and bits IOB2 to IOB0 in TIOR0 bits TIOCB0 TPSC2 to TPSC0 in TCR4 to TCR0 bit NDER3 in NDERA and bit PA3DDR in PADDR ...

Page 295: ...bit PA2DDR in PADDR TCLKC select the pin function as follows ITU channel 0 settings 1 in table below 2 in table below PA2DDR 0 1 1 NDER2 0 1 Pin function TIOCA0 output PA2 input PA2 output TP2 output TIOCA0 input 1 TCLKC input 2 Notes 1 TIOCA0 input when IOA2 1 2 TCLKC input when TPSC2 TPSC1 1 and TPSC0 0 in any of TCR4 to TCR0 ITU channel 0 settings 2 1 2 1 PWM0 0 1 IOA2 0 1 IOA1 0 0 1 IOA0 0 1 2...

Page 296: ...TCR4 to TCR0 DMAC channel 1 settings 2 1 2 1 2 1 DTS2A DTS1A Not both 1 Both 1 DTS0A 0 0 1 1 1 DTS2B 0 1 1 0 1 0 1 1 DTS1B 0 1 0 1 PA0 TP0 DMAC channel 0 settings bits DTS2 1 0A and DTS2 1 0B in DTCR0A and DTCR0B TCLKA bit NDER0 in NDERA and bit PA0DDR in PADDR select the pin function as follows TEND0 DMAC channel 0 settings 1 in table below 2 in table below PA0DDR 0 1 1 NDER0 0 1 Pin function TEN...

Page 297: ...set or hardware standby leaves port B as an input port Usage of pins for TPC ITU DMAC and A D converter input and output is described in the sections on those modules For output of CS7 in modes 1 to 6 see section 6 3 2 Chip Select Signals Pins not assigned to any of these functions are available for generic input output Figure 9 11 shows the pin configuration of port B Pins in port B can drive one...

Page 298: ...OCB4 input output PB2 input output TP10 output TIOCA4 input output PB1 input output TP9 output TIOCB3 input output PB0 input output TP8 output TIOCA3 input output Pin functions in modes 1 to 6 PB7 input output TP15 output DREQ1 input ADTRG input PB6 input output TP14 output DREQ0 input PB5 input output TP13 output TOCXB4 output PB4 input output TP12 output TOCXA4 output PB3 input output TP11 outpu...

Page 299: ... pin in port B becomes an output pin if the corresponding PBDDR bit is set to 1 and an input pin if this bit is cleared to 0 PBDDR is a write only register Its value cannot be read All bits return 1 when read PBDDR is initialized to H 00 by a reset and in hardware standby mode In software standby mode it retains its previous setting If a PBDDR bit is set to 1 the corresponding pin maintains its ou...

Page 300: ...a bit in PBDDR is cleared to 0 if port B is read the corresponding pin level is read PBDR is initialized to H 00 by a reset and in hardware standby mode In software standby mode it retains its previous setting 287 Bit Initial value Read Write 0 PB 0 R W 0 1 PB 0 R W 1 2 PB 0 R W 2 3 PB 0 R W 3 4 PB 0 R W 4 5 PB 0 R W 5 6 PB 0 R W 6 7 PB 0 R W 7 Port B data 7 to 0 These bits store data for port B p...

Page 301: ...bit NDER15 in NDERB and bit PB7DDR in PBDDR select the pin function as follows PB7DDR 0 1 1 NDER15 0 1 Pin function PB7 input PB7 output TP15 output DREQ1 input 1 ADTRG input 2 Notes 1 DREQ1 input under DMAC channel 1 settings 1 in the table below 2 ADTRG input when TRGE 1 DMAC channel 1 settings 2 1 2 1 2 1 DTS2A DTS1A Not both 1 Both 1 DTS0A 0 0 1 1 1 DTS2B 0 1 1 0 1 0 1 1 DTS1B 0 1 0 1 288 PB7 ...

Page 302: ...TS2A DTS1A Not both 1 Both 1 DTS0A 0 0 1 1 1 DTS2B 0 1 1 0 1 0 1 1 DTS1B 0 1 0 1 ITU channel 4 settings bit CMD1 in TFCR and bit EXB4 in TOER bit NDER13 in NDERB and bit PB5DDR in PBDDR select the pin function as follows EXB4 CMD1 Not both 1 Both 1 PB5DDR 0 1 1 NDER13 0 1 Pin function PB5 input PB5 output TP13 output TOCXB4 output ITU channel 4 settings bit CMD1 in TFCR and bit EXA4 in TOER bit ND...

Page 303: ... in NDERB and bit PB3DDR in PBDDR select the pin function as follows ITU channel 4 settings 1 in table below 2 in table below PB3DDR 0 1 1 NDER11 0 1 Pin function TIOCB4 output PB3 input PB3 output TP11 output TIOCB4 input Note TIOCB4 input when CMD1 PWM4 0 and IOB2 1 ITU channel 4 settings 2 2 1 2 1 EB4 0 1 CMD1 0 1 IOB2 0 0 0 1 IOB1 0 0 1 IOB0 0 1 PB3 TP11 TIOCB4 290 www DataSheet4U com ...

Page 304: ...NDERB and bit PB2DDR in PBDDR select the pin function as follows ITU channel 4 settings 1 in table below 2 in table below PB2DDR 0 1 1 NDER10 0 1 Pin function TIOCA4 output PB2 input PB2 output TP10 output TIOCA4 input Note TIOCA4 input when CMD1 PWM4 0 and IOA2 1 ITU channel 4 settings 2 2 1 2 1 EA4 0 1 CMD1 0 1 PWM4 0 1 IOA2 0 0 0 1 IOA1 0 0 1 IOA0 0 1 PB2 TP10 TIOCA4 291 www DataSheet4U com ...

Page 305: ...9 in NDERB and bit PB1DDR in PBDDR select the pin function as follows ITU channel 3 settings 1 in table below 2 in table below PB1DDR 0 1 1 NDER9 0 1 Pin function TIOCB3 output PB1 input PB1 output TP9 output TIOCB3 input Note TIOCB3 input when CMD1 PWM3 0 and IOB2 1 ITU channel 3 settings 2 2 1 2 1 EB3 0 1 CMD1 0 1 IOB2 0 0 0 1 IOB1 0 0 1 IOB0 0 1 PB1 TP9 TIOCB3 292 www DataSheet4U com ...

Page 306: ... NDERB and bit PB0DDR in PBDDR select the pin function as follows ITU channel 3 settings 1 in table below 2 in table below PB0DDR 0 1 1 NDER8 0 1 Pin function TIOCA3 output PB0 input PB0 output TP8 output TIOCA3 input Note TIOCA3 input when CMD1 PWM3 0 and IOA2 1 ITU channel 3 settings 2 2 1 2 1 EA3 0 1 CMD1 0 1 PWM3 0 1 IOA2 0 0 0 1 IOA1 0 0 1 IOA0 0 1 PB0 TP8 TIOCA3 293 www DataSheet4U com ...

Page 307: ...pture functions Selection of eight counter clock sources for each channel Internal clocks ø ø 2 ø 4 ø 8 External clocks TCLKA TCLKB TCLKC TCLKD Five operating modes selectable in all channels Waveform output by compare match Selection of 0 output 1 output or toggle output only 0 or 1 output in channel 2 Input capture function Rising edge falling edge or both edges selectable Counter clearing funct...

Page 308: ...mplementary waveforms Buffering Input capture registers can be double buffered Output compare registers can be updated automatically High speed access via internal 16 bit bus The 16 bit timer counters general registers and buffer registers can be accessed at high speed via a 16 bit bus Fifteen interrupt sources Each channel has two compare match input capture interrupts and an overflow interrupt A...

Page 309: ...input capture 0 o o o o o 1 o o o o o Toggle o o o o Input capture function o o o o o Synchronization o o o o o PWM mode o o o o o Reset synchronized o o PWM mode Complementary PWM o o mode Phase counting mode o Buffering o o DMAC activation GRA0 compare GRA1 compare GRA2 compare GRA3 compare match or match or match or match or input capture input capture input capture input capture Interrupt sour...

Page 310: ...odule data bus Bus interface On chip data bus IMIA0 to IMIA4 IMIB0 to IMIB4 OVI0 to OVI4 TCLKA to TCLKD ø ø 2 ø 4 ø 8 TOCXA4 TOCXB4 Clock selector Control logic TIOCA0 to TIOCA4 TIOCB0 to TIOCB4 TOER TOCR TSTR TSNC TMDR TFCR TOER TOCR TSTR TSNC TMDR Legend Timer output master enable register 8 bits Timer output control register 8 bits Timer start register 8 bits Timer synchro register 8 bits Timer...

Page 311: ... 2 Block Diagram of Channels 0 and 1 for Channel 0 Clock selector Comparator Control logic TCLKA to TCLKD ø ø 2 ø 4 ø 8 TIOCA0 TIOCB0 IMIA0 IMIB0 OVI0 TCNT GRA GRB TCR TIOR TIER TSR Module data bus Legend TCNT GRA GRB Timer counter 16 bits General registers A and B input capture output compare registers 16 bits 2 299 www DataSheet4U com ...

Page 312: ...ure 10 3 Block Diagram of Channel 2 Clock selector Comparator Control logic TCLKA to TCLKD ø ø 2 ø 4 ø 8 TIOCA2 TIOCB2 IMIA2 IMIB2 OVI2 TCNT2 GRA2 GRB2 TCR2 TIOR2 TIER2 TSR2 Module data bus Legend TCNT2 GRA2 GRB2 Timer counter 2 16 bits General registers A2 and B2 input capture output compare registers 16 bits 2 300 www DataSheet4U com ...

Page 313: ...nd TCNT3 GRA3 GRB3 BRA3 BRB3 Timer counter 3 16 bits General registers A3 and B3 input capture output compare registers 16 bits 2 Buffer registers A3 and B3 input capture output compare buffer registers Clock selector Comparator Control logic GRA3 BRB3 GRB3 TCR3 TIOR3 TIER3 TSR3 TCLKA to TCLKD ø ø 2 ø 4 ø 8 TIOCA3 TIOCB3 Module data bus IMIA3 IMIB3 OVI3 301 www DataSheet4U com ...

Page 314: ...s A4 and B4 input capture output compare registers 16 bits 2 Buffer registers A4 and B4 input capture output compare buffer registers Clock selector Comparator Control logic GRA4 BRB4 GRB4 TCR4 TIOR4 TIER4 TSR4 Module data bus TCLKA to TCLKD ø ø 2 ø 4 ø 8 TOCXA4 TOCXB4 TIOCA4 TIOCB4 IMIA4 IMIB4 OVI4 302 www DataSheet4U com ...

Page 315: ... GRA2 output compare or input capture pin compare A2 output PWM output pin in PWM mode Input capture output TIOCB2 Input GRB2 output compare or input capture pin compare B2 output 3 Input capture output TIOCA3 Input GRA3 output compare or input capture pin compare A3 output PWM output pin in PWM mode comple mentary PWM mode or reset synchronized PWM mode Input capture output TIOCB3 Input GRB3 outp...

Page 316: ...imer counter 0 high TCNT0H R W H 00 H FF69 Timer counter 0 low TCNT0L R W H 00 H FF6A General register A0 high GRA0H R W H FF H FF6B General register A0 low GRA0L R W H FF H FF6C General register B0 high GRB0H R W H FF H FF6D General register B0 low GRB0L R W H FF 1 H FF6E Timer control register 1 TCR1 R W H 80 H FF6F Timer I O control register 1 TIOR1 R W H 88 H FF70 Timer interrupt enable regist...

Page 317: ...82 Timer control register 3 TCR3 R W H 80 H FF83 Timer I O control register 3 TIOR3 R W H 88 H FF84 Timer interrupt enable register 3 TIER3 R W H F8 H FF85 Timer status register 3 TSR3 R W 2 H F8 H FF86 Timer counter 3 high TCNT3H R W H 00 H FF87 Timer counter 3 low TCNT3L R W H 00 H FF88 General register A3 high GRA3H R W H FF H FF89 General register A3 low GRA3L R W H FF H FF8A General register ...

Page 318: ...0 H FF97 Timer counter 4 low TCNT4L R W H 00 H FF98 General register A4 high GRA4H R W H FF H FF99 General register A4 low GRA4L R W H FF H FF9A General register B4 high GRB4H R W H FF H FF9B General register B4 low GRB4L R W H FF H FF9C Buffer register A4 high BRA4H R W H FF H FF9D Buffer register A4 low BRA4L R W H FF H FF9E Buffer register B4 high BRB4H R W H FF H FF9F Buffer register B4 low BR...

Page 319: ...TR4 Description 0 TCNT4 is halted Initial value 1 TCNT4 is counting Bit 3 Counter Start 3 STR3 Starts and stops timer counter 3 TCNT3 Bit 3 STR3 Description 0 TCNT3 is halted Initial value 1 TCNT3 is counting Bit 2 Counter Start 2 STR2 Starts and stops timer counter 2 TCNT2 Bit 2 STR2 Description 0 TCNT2 is halted Initial value 1 TCNT2 is counting Bit Initial value Read Write 7 1 6 1 5 1 4 STR4 0 ...

Page 320: ...g the corresponding bits to 1 TSNC is initialized to H E0 by a reset and in standby mode Bits 7 to 5 Reserved Read only bits always read as 1 Bit 4 Timer Sync 4 SYNC4 Selects whether channel 4 operates independently or synchronously Bit 4 SYNC4 Description 0 Channel 4 s timer counter TCNT4 operates independently Initial value TCNT4 is preset and cleared independently of other channels 1 Channel 4 ...

Page 321: ...hannels 1 Channel 2 operates synchronously TCNT2 can be synchronously preset and cleared Bit 1 Timer Sync 1 SYNC1 Selects whether channel 1 operates independently or synchronously Bit 1 SYNC1 Description 0 Channel 1 s timer counter TCNT1 operates independently Initial value TCNT1 is preset and cleared independently of other channels 1 Channel 1 operates synchronously TCNT1 can be synchronously pre...

Page 322: ...hether channel 2 operates normally or in phase counting mode Bit 6 MDF Description 0 Channel 2 operates normally Initial value 1 Channel 2 operates in phase counting mode Bit Initial value Read Write 7 1 6 MDF 0 R W 5 FDIR 0 R W 4 PWM4 0 R W 3 PWM3 0 R W 0 PWM0 0 R W 2 PWM2 0 R W 1 PWM1 0 R W Reserved bit PWM mode 4 to 0 These bits select PWM mode for channels 4 to 0 Phase counting mode flag Selec...

Page 323: ...terrupt functions of TIOR2 TIER2 and TSR2 remain effective in phase counting mode Bit 5 Flag Direction FDIR Designates the setting condition for the OVF flag in TSR2 The FDIR designation is valid in all modes in channel 2 Bit 5 FDIR Description 0 OVF is set to 1 in TSR2 when TCNT2 overflows or underflows Initial value 1 OVF is set to 1 in TSR2 when TCNT2 overflows Bit 4 PWM Mode 4 PWM4 Selects whe...

Page 324: ...ed Bit 2 PWM Mode 2 PWM2 Selects whether channel 2 operates normally or in PWM mode Bit 2 PWM2 Description 0 Channel 2 operates normally Initial value 1 Channel 2 operates in PWM mode When bit PWM2 is set to 1 to select PWM mode pin TIOCA2 becomes a PWM output pin The output goes to 1 at compare match with GRA2 and to 0 at compare match with GRB2 Bit 1 PWM Mode 1 PWM1 Selects whether channel 1 ope...

Page 325: ...d PWM mode and buffering for channels 3 and 4 TFCR is initialized to H C0 by a reset and in standby mode Bits 7 and 6 Reserved Read only bits always read as 1 Bit Initial value Read Write 7 1 6 1 5 CMD1 0 R W 4 CMD0 0 R W 3 BFB4 0 R W 0 BFA3 0 R W 2 BFA4 0 R W 1 BFB3 0 R W Reserved bits Combination mode 1 0 These bits select complementary PWM mode or reset synchronized PWM mode for channels 3 and ...

Page 326: ...ronized PWM mode they take precedence over the setting of the PWM mode bits PWM4 and PWM3 in TMDR Settings of timer sync bits SYNC4 and SYNC3 in TSNC are valid in complementary PWM mode and reset synchronized PWM mode however When complementary PWM mode is selected channels 3 and 4 must not be synchronized do not set bits SYNC3 and SYNC4 both to 1 in TSNC Bit 3 Buffer Mode B4 BFB4 Selects whether ...

Page 327: ...t Master Enable Register TOER TOER is an 8 bit readable writable register that enables or disables output settings for channels 3 and 4 TOER is initialized to H FF by a reset and in standby mode Bits 7 and 6 Reserved Read only bits always read as 1 Bit Initial value Read Write 7 1 6 1 5 EXB4 1 R W 4 EXA4 1 R W 3 EB3 1 R W 0 EA3 1 R W 2 EB4 1 R W 1 EA4 1 R W Reserved bits Master enable TOCXA4 TOCXB...

Page 328: ...ription 0 TOCXA4 output is disabled regardless of TFCR settings TOCXA4 operates as a generic input output pin If XTGD 0 EXA4 is cleared to 0 when input capture A occurs in channel 1 1 TOCXA4 is enabled for output according to TFCR settings Initial value Bit 3 Master Enable TIOCB3 EB3 Enables or disables ITU output at pin TIOCB3 Bit 3 EB3 Description 0 TIOCB3 output is disabled regardless of TIOR3 ...

Page 329: ...OCA4 output is disabled regardless of TIOR4 TMDR and TFCR settings TIOCA4 operates as a generic input output pin If XTGD 0 EA4 is cleared to 0 when input capture A occurs in channel 1 1 TIOCA4 is enabled for output according to TIOR4 TMDR and Initial value TFCR settings Bit 0 Master Enable TIOCA3 EA3 Enables or disables ITU output at pin TIOCA3 Bit 0 EA3 Description 0 TIOCA3 output is disabled reg...

Page 330: ...ered disabling of ITU output in complementary PWM mode and reset synchronized PWM mode Bit 4 XTGD Description 0 Input capture A in channel 1 is used as an external trigger signal in complementary PWM mode and reset synchronized PWM mode When an external trigger occurs bits 5 to 0 in TOER are cleared to 0 disabling ITU output 1 External triggering is disabled Initial value Bit Initial value Read Wr...

Page 331: ...3 TOCXA4 and TOCXB4 outputs are not inverted Initial value 10 2 7 Timer Counters TCNT TCNT is a 16 bit counter The ITU has five TCNTs one for each channel Channel Abbreviation Function 0 TCNT0 Up counter 1 TCNT1 2 TCNT2 Phase counting mode up down counter Other modes up counter 3 TCNT3 4 TCNT4 Each TCNT is a 16 bit readable writable register that counts pulse inputs from a clock source The clock s...

Page 332: ...ode 10 2 8 General Registers GRA GRB The general registers are 16 bit registers The ITU has 10 general registers two in each channel Channel Abbreviation Function 0 GRA0 GRB0 Output compare input capture register 1 GRA1 GRB1 2 GRA2 GRB2 3 GRA3 GRB3 4 GRA4 GRB4 A general register is a 16 bit readable writable register that can function as either an output compare register or an input capture regist...

Page 333: ... BRA4 BRB4 When the corresponding GRA or GRB functions as an output compare register BRA or BRB can function as an output compare buffer register the BRA or BRB value is automatically transferred to GRA or GRB at compare match When the corresponding GRA or GRB functions as an input capture register BRA or BRB can function as an input capture buffer register the GRA or GRB value is automatically tr...

Page 334: ...k sources and selects how the counter is cleared TCR is initialized to H 80 by a reset and in standby mode Bit 7 Reserved Read only bit always read as 1 TCR controls the timer counter The TCRs in all channels are functionally identical When phase counting mode is selected in channel 2 the settings of bits CKEG1 and CKEG0 and TPSC2 to TPSC0 in TCR2 are ignored Bit Initial value Read Write 7 1 6 CCL...

Page 335: ...s cleared by compare match when the general register functions as an output compare register and by input capture when the general register functions as an input capture register 2 Selected in TSNC Bits 4 and 3 Clock Edge 1 0 CKEG1 CKEG0 These bits select external clock input edges when an external clock source is used Bit 4 Bit 3 CKEG1 CKEG0 Description 0 0 Count rising edges Initial value 1 Coun...

Page 336: ...en bit TPSC2 is set to 1 an external clock source is selected and the timer counts the edge or edges selected by bits CKEG1 and CKEG0 When channel 2 is set to phase counting mode MDF 1 in TMDR the settings of bits TPSC2 to TPSC0 in TCR2 are ignored Phase counting takes precedence 10 2 11 Timer I O Control Register TIOR TIOR is an 8 bit register The ITU has five TIORs one in each channel Channel Ab...

Page 337: ...No output at compare match Initial value 1 0 output at GRB compare match 1 1 0 1 output at GRB compare match 1 1 Output toggles at GRB compare match 1 output in channel 2 1 2 1 0 0 GRB captures rising edge of input 1 GRB captures falling edge of input 1 0 GRB captures both edges of input 1 Notes 1 After a reset the output is 0 until the first compare match 2 Channel 2 output cannot be toggled by c...

Page 338: ...rising edge of input 1 GRA captures falling edge of input 1 0 GRA captures both edges of input 1 Notes 1 After a reset the output is 0 until the first compare match 2 Channel 2 output cannot be toggled by compare match This setting selects 1 output instead 10 2 12 Timer Status Register TSR TSR is an 8 bit register The ITU has five TSRs one in each channel Channel Abbreviation Function 0 TSR0 Indic...

Page 339: ...dition TCNT overflowed from H FFFF to H 0000 or underflowed from H 0000 to H FFFF Notes TCNT underflow occurs when TCNT operates as an up down counter Underflow occurs only under the following conditions 1 Channel 2 operates in phase counting mode MDF 1 in TMDR 2 Channels 3 and 4 operate in complementary PWM mode CMD1 1 and CMD0 0 in TFCR Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 2 OVF 0 R ...

Page 340: ...apture signal when GRB functions as an input capture register Bit 0 Input Capture Compare Match Flag A IMFA This status flag indicates GRA compare match or input capture events Bit 0 IMFA Description 0 Clearing condition Initial value Read IMFA when IMFA 1 then write 0 in IMFA DMAC activated by IMIA interrupt channels 0 to 3 only 1 Setting conditions TCNT GRA when GRA functions as an output compar...

Page 341: ...eneral register compare match and input capture interrupt requests TIER is initialized to H F8 by a reset and in standby mode Bits 7 to 3 Reserved Read only bits always read as 1 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 2 OVIE 0 R W 1 IMIEB 0 R W 0 IMIEA 0 R W Reserved bits Overflow interrupt enable Enables or disables OVF interrupts Input capture compare match interrupt enable B Enables o...

Page 342: ...s or disables the interrupt requested by the IMFB flag in TSR when IMFB is set to 1 Bit 1 IMIEB Description 0 IMIB interrupt requested by IMFB is disabled Initial value 1 IMIB interrupt requested by IMFB is enabled Bit 0 Input Capture Compare Match Interrupt Enable A IMIEA Enables or disables the interrupt requested by the IMFA flag in TSR when IMFA is set to 1 Bit 0 IMIEA Description 0 IMIA inter...

Page 343: ...ad a word at a time or a byte at a time Figures 10 6 and 10 7 show examples of word access to a timer counter TCNT Figures 10 8 10 9 10 10 and 10 11 show examples of byte access to TCNTH and TCNTL Figure 10 6 Access to Timer Counter CPU Writes to TCNT Word Figure 10 7 Access to Timer Counter CPU Reads TCNT Word On chip data bus CPU H L Bus interface H L Module data bus TCNTH TCNTL On chip data bus...

Page 344: ... TCNT Lower Byte Figure 10 10 Access to Timer Counter CPU Reads TCNT Upper Byte On chip data bus CPU H L Bus interface H L Module data bus TCNTH TCNTL On chip data bus CPU H L Bus interface H L Module data bus TCNTH TCNTL On chip data bus CPU H L Bus interface H L Module data bus TCNTH TCNTL 332 www DataSheet4U com ...

Page 345: ...inked to the CPU by an internal 8 bit data bus Figures 10 12 and 10 13 show examples of byte read and write access to a TCR If a word size data transfer instruction is executed two byte transfers are performed Figure 10 12 Access to Timer Counter CPU Writes to TCR On chip data bus CPU H L Bus interface H L Module data bus TCNTH TCNTL On chip data bus CPU H L Bus interface H L Module data bus TCR 3...

Page 346: ...Figure 10 13 Access to Timer Counter CPU Reads TCR On chip data bus CPU H L Bus interface H L Module data bus TCR 334 www DataSheet4U com ...

Page 347: ...lly become output compare registers Reset Synchronized PWM Mode Channels 3 and 4 are paired for three phase PWM output with complementary waveforms The three phases are related by having a common transition point When reset synchronized PWM mode is selected GRA3 GRB3 GRA4 and GRB4 automatically function as output compare registers TIOCA3 TIOCB3 TIOCA4 TOCXA4 TIOCB4 and TOCXB4 function as PWM outpu...

Page 348: ...M mode The buffer register value is transferred to the general register when TCNT3 and TCNT4 change counting direction Reset synchronized PWM mode The buffer register value is transferred to the general register at GRA3 compare match 10 4 2 Basic Functions Counter Operation When one of bits STR0 to STR4 is set to 1 in the timer start register TSTR the timer counter TCNT in the corresponding channe...

Page 349: ...match or GRB compare match 3 Set TIOR to select the output compare function of GRA or GRB whichever was selected in step 2 4 Write the count period in GRA or GRB whichever was selected in step 2 5 Set the STR bit to 1 in TSTR to start the timer counter Counter setup Select counter clock Type of counting Periodic counting No Yes Select counter clear source Select output compare register function Se...

Page 350: ... its counter cleared by compare match in that channel TCNT operates as a periodic counter Select the output compare function of GRA or GRB set bit CCLR1 or CCLR0 in TCR to have the counter cleared by compare match and set the count period in GRA or GRB After these settings the counter starts counting up as a periodic counter when the corresponding bit is set to 1 in TSTR When the count matches GRA...

Page 351: ... ø or one of three internal clock sources obtained by prescaling the system clock ø 2 ø 4 ø 8 Figure 10 17 shows the timing Figure 10 17 Count Timing for Internal Clock Sources TCNT value GR H 0000 STR bit IMF Time Counter cleared by general register compare match ø TCNT input TCNT Internal clock N 1 N N 1 339 www DataSheet4U com ...

Page 352: ...e pulse width of the external clock signal must be at least 1 5 system clocks when a single edge is selected and at least 2 5 system clocks when both edges are selected Shorter pulses will not be counted correctly Figure 10 18 shows the timing when both edges are detected Figure 10 18 Count Timing for External Clock Sources when Both Edges are Detected ø TCNT input TCNT External clock input N 1 N ...

Page 353: ...ates as a free running counter 0 output is selected for compare match A and 1 output is selected for compare match B When the pin is already at the selected output level the pin level does not change Output setup Select waveform output mode Set output timing Start counter Waveform output Select the compare match output mode 0 1 or toggle in TIOR When a waveform output mode is selected the pin swit...

Page 354: ...ch B Toggle output is selected for both compare match A and B Figure 10 21 Toggle Output Example Time H FFFF GRB TIOCB TIOCA GRA No change No change No change No change 1 output 0 output TCNT value H 0000 GRB TIOCB TIOCA GRA TCNT value Time Counter cleared by compare match with GRB Toggle output Toggle output H 0000 342 www DataSheet4U com ...

Page 355: ...next counter clock pulse Figure 10 22 shows the output compare timing Figure 10 22 Output Compare Timing Input Capture Function The TCNT value can be captured into a general register when a transition occurs at an input capture output compare pin TIOCA or TIOCB Capture can take place on the rising edge falling edge or both edges The input capture function can be used to measure pulse width or peri...

Page 356: ...ction Select input capture input Start counter Input capture Set TIOR to select the input capture function of a general register and the rising edge falling edge or both edges of the input capture signal Clear the port data direction bit to 0 before making these TIOR settings Set the STR bit to 1 in TSTR to start the timer counter 1 2 1 2 H 0005 H 0180 Time H 0180 H 0160 H 0005 H 0000 TIOCB TIOCA ...

Page 357: ...25 shows the timing when the rising edge is selected The pulse width of the input capture signal must be at least 1 5 system clocks for single edge capture and 2 5 system clocks for capture of both edges Figure 10 25 Input Capture Signal Timing N N ø Input capture input Internal input capture signal TCNT GRA GRB 345 www DataSheet4U com ...

Page 358: ...xample Setup for synchronization Synchronous preset Set the SYNC bits to 1 in TSNC for the channels to be synchronized When a value is written in TCNT in one of the synchronized channels the same value is simultaneously written in TCNT in the other channels synchronized preset 1 2 2 3 1 5 4 5 Select synchronization Synchronous preset Write to TCNT Synchronous clear Clearing synchronized to this ch...

Page 359: ...s counter clearing The timer counters in channels 0 1 and 2 are synchronously preset and are synchronously cleared by compare match with GRB0 A three phase PWM waveform is output from pins TIOCA0 TIOCA1 and TIOCA2 For further information on PWM mode see section 10 4 4 PWM Mode Figure 10 27 Synchronization Example Time TIOCA1 TIOCA0 GRA2 GRA1 GRB2 GRA0 GRB1 GRB0 Value of TCNT0 to TCNT2 Cleared by c...

Page 360: ...a PWM waveform with a duty cycle from 0 to 100 is output at the TIOCA pin PWM mode can be selected in all channels 0 to 4 Table 10 4 summarizes the PWM output pins and corresponding registers If the same value is set in GRA and GRB the output does not change when compare match occurs Table 10 4 PWM Output Pins and Registers Channel Output Pin 1 Output 0 Output 0 TIOCA0 GRA0 GRB0 1 TIOCA1 GRA1 GRB1...

Page 361: ...6 2 Set bits CCLR1 and CCLR0 in TCR to select the counter clear source 3 Set the time at which the PWM waveform should go to 1 in GRA 4 Set the time at which the PWM waveform should go to 0 in GRB 5 Set the PWM bit in TMDR to select PWM mode When PWM mode is selected regardless of the TIOR contents GRA and GRB become output compare registers specifying the times at which the PWM output goes to 1 a...

Page 362: ... the examples shown TCNT is cleared by compare match with GRA or GRB Synchronized operation and free running counting are also possible Figure 10 29 PWM Mode Example 1 TCNT value Counter cleared by compare match with GRA Time GRA GRB TIOCA a Counter cleared by GRA TCNT value Counter cleared by compare match with GRB Time GRB GRA TIOCA b Counter cleared by GRB H 0000 H 0000 350 www DataSheet4U com ...

Page 363: ...he counter is cleared by compare match with GRA and GRB is set to a higher value than GRA the duty cycle is 100 Figure 10 30 PWM Mode Example 2 TCNT value Counter cleared by compare match with GRB Time GRB GRA TIOCA a 0 duty cycle TCNT value Counter cleared by compare match with GRA Time GRA GRB TIOCA b 100 duty cycle Write to GRA Write to GRA Write to GRB Write to GRB H 0000 H 0000 351 www DataSh...

Page 364: ...put Pin Description 3 TIOCA3 PWM output 1 TIOCB3 PWM output 1 complementary waveform to PWM output 1 4 TIOCA4 PWM output 2 TOCXA4 PWM output 2 complementary waveform to PWM output 2 TIOCB4 PWM output 3 TOCXB4 PWM output 3 complementary waveform to PWM output 3 Table 10 6 Register Settings in Reset Synchronized PWM Mode Register Setting TCNT3 Initially set to H 0000 TCNT4 Not used operates independ...

Page 365: ...to TPSC0 in TCR to select the counter clock source for channel 3 If an external clock source is selected select the external clock edge s with bits CKEG1 and CKEG0 in TCR 3 Set bits CCLR1 and CCLR0 in TCR3 to select GRA3 compare match as the counter clear source 4 Set bits CMD1 and CMD0 in TFCR to select reset synchronized PWM mode TIOCA3 TIOCB3 TIOCA4 TIOCB4 TOCXA4 and TOCXB4 automatically become...

Page 366: ...0 The PWM outputs toggle at compare match of TCNT3 with GRB3 GRA4 and GRB4 respectively and all toggle when the counter is cleared Figure 10 32 Operation in Reset Synchronized PWM Mode Example when OLS3 OLS4 1 For the settings and operation when reset synchronized PWM mode and buffer mode are both selected see section 10 4 8 Buffering TCNT3 value Counter cleared at compare match with GRA3 Time GRA...

Page 367: ... overlapping complementary waveform to PWM output 1 4 TIOCA4 PWM output 2 TOCXA4 PWM output 2 non overlapping complementary waveform to PWM output 2 TIOCB4 PWM output 3 TOCXB4 PWM output 3 non overlapping complementary waveform to PWM output 3 Table 10 8 Register Settings in Complementary PWM Mode Register Setting TCNT3 Initially specifies the non overlap margin difference to TCNT4 TCNT4 Initially...

Page 368: ...s CKEG1 and CKEG0 in TCR Do not select any counter clear source with bits CCLR1 and CCLR0 in TCR 3 Set bits CMD1 and CMD0 in TFCR to select complementary PWM mode TIOCA3 TIOCB3 TIOCA4 TIOCB4 TOCXA4 and TOCXB4 automatically become PWM output pins 4 Clear TCNT4 to H 0000 Set the non overlap margin in TCNT3 Do not set TCNT3 and TCNT4 to the same value 5 GRA3 is the waveform period register Set the up...

Page 369: ...y PWM mode 1 Clear the CMD1 bit of TFCR to 0 to set channels 3 and 4 to normal operating mode Normal operating mode Clear complementary PWM mode 1 Stop counter operation 2 2 After setting channels 3 and 4 to normal operating mode wait at least one counter clock period then clear bits STR3 and STR4 of TSTR to 0 to stop counter operation of TCNT3 and TCNT4 357 www DataSheet4U com ...

Page 370: ...forms are generated by compare match with general registers GRB3 GRA4 and GRB4 Since TCNT3 is initially set to a higher value than TCNT4 compare match events occur in the sequence TCNT3 TCNT4 TCNT4 TCNT3 Figure 10 35 Operation in Complementary PWM Mode Example 1 OLS3 OLS4 1 TCNT3 and TCNT4 values Down counting starts at compare match between TCNT3 and GRA3 Time GRA3 GRB3 GRA4 GRB4 H 0000 TIOCA3 TI...

Page 371: ...3 to a value larger than GRA3 The duty cycle can be changed easily during operation by use of the buffer registers For further information see section 10 4 8 Buffering Figure 10 36 Operation in Complementary PWM Mode Example 2 OLS3 OLS4 1 TCNT3 and TCNT4 values Time GRA3 GRB3 TIOCA3 TIOCB3 0 duty cycle a 0 duty cycle TCNT3 and TCNT4 values Time GRA3 GRB3 TIOCA3 TIOCB3 100 duty cycle b 100 duty cyc...

Page 372: ...channel 3 and the OVF bit in channel 4 differ from the usual conditions In buffered operation the buffer transfer conditions also differ Timing diagrams are shown in figures 10 37 and 10 38 Figure 10 37 Overshoot Timing TCNT3 GRA3 IMFA Buffer transfer signal BR to GR GR N 1 N N 1 N N 1 N Set to 1 Flag not set No buffer transfer Buffer transfer 360 www DataSheet4U com ...

Page 373: ...te the following points Initial settings Do not set values from H 0000 to T 1 where T is the initial value of TCNT3 After the counters start and the first compare match A3 event has occurred however settings in this range also become possible Changing settings Use the buffer registers Correct waveform output may not be obtained if a general register is written to directly Cautions on changes of ge...

Page 374: ...om GRA3 T 1 to GRA3 do not transfer a buffer register value outside this range Conversely if the general register value is outside this range do not transfer a value within this range See figure 10 40 Figure 10 40 Changing a General Register Setting by Buffer Transfer Caution 1 GRA3 GR H 0000 BR GR Not allowed GRA3 1 GRA3 GRA3 T 1 GRA3 T Illegal changes TCNT3 TCNT4 362 www DataSheet4U com ...

Page 375: ... do not transfer a buffer register value outside this range Conversely when a general register value is outside this range do not transfer a value within this range See figure 10 41 Figure 10 41 Changing a General Register Setting by Buffer Transfer Caution 2 T T 1 H 0000 H FFFF Illegal changes TCNT3 TCNT4 363 www DataSheet4U com ...

Page 376: ...ting range the counting direction up or down must be the same both times See figure 10 42 Figure 10 42 Changing a General Register Setting by Buffer Transfer Example 2 Settings can be made in this way by detecting GRA3 compare match or TCNT4 underflow before writing to the buffer register They can also be made by using GRA3 compare match to activate the DMAC 0 duty cycle 100 duty cycle Write durin...

Page 377: ...2 GRA2 and GRB2 are valid The input capture and output compare functions can be used and interrupts can be generated Phase counting is available only in channel 2 Sample Setup Procedure for Phase Counting Mode Figure 10 43 shows a sample procedure for setting up phase counting mode Figure 10 43 Setup Procedure for Phase Counting Mode Example Phase counting mode Select phase counting mode Select fl...

Page 378: ...ates and the pulse width must be at least 2 5 states See figure 10 45 Figure 10 44 Operation in Phase Counting Mode Example Table 10 9 Up Down Counting Conditions Counting Direction Up Counting Down Counting TCLKB High Low High Low TCLKA Low High Low High Figure 10 45 Phase Difference Overlap and Pulse Width in Phase Counting Mode TCNT2 value Counting up Counting down Time TCLKB TCLKA TCLKA TCLKB ...

Page 379: ...e are described next General register used for output compare The buffer register value is transferred to the general register at compare match See figure 10 46 Figure 10 46 Compare Match Buffering General register used for input capture The TCNT value is transferred to the general register at input capture The previous general register value is transferred to the buffer register See figure 10 47 ...

Page 380: ...t compare match A3 Sample Buffering Setup Procedure Figure 10 48 shows a sample buffering setup procedure Figure 10 48 Buffering Setup Procedure Example Buffering Select general register functions Set buffer bits Start counters Buffered operation 1 1 2 3 2 3 Set TIOR to select the output compare or input capture function of the general registers Set bits BFA3 BFA4 BFB3 and BFB4 in TFCR to select b...

Page 381: ...tting when TIOCA toggles at compare match A the BRA value is simultaneously transferred to GRA This operation is repeated each time compare match A occurs Figure 10 50 shows the transfer timing Figure 10 49 Register Buffering Example 1 Buffering of Output Compare Register GRB H 0250 H 0200 H 0100 H 0000 BRA GRA TIOCB TIOCA TCNT value Counter cleared by compare match B Time Toggle output Toggle out...

Page 382: ...Figure 10 50 Compare Match and Buffer Transfer Timing Example ø TCNT BR GR Compare match signal Buffer transfer signal n n 1 n N N 370 www DataSheet4U com ...

Page 383: ...es at TIOCA Because of the buffer setting when the TCNT value is captured into GRA at input capture A the previous GRA value is simultaneously transferred to BRA Figure 10 52 shows the transfer timing Figure 10 51 Register Buffering Example 2 Buffering of Input Capture Register H 0180 H 0160 H 0005 H 0000 TIOCB TIOCA GRA BRA GRB H 0005 H 0160 H 0005 H 0180 TCNT value Counter cleared by input captu...

Page 384: ...Figure 10 52 Input Capture and Buffer Transfer Timing Example ø TCNT GR BR TIOC pin Input capture signal n n 1 N n M N 1 N n M m n M 372 www DataSheet4U com ...

Page 385: ...waveform with 0 duty cycle The BRB3 value is transferred to GRB3 when TCNT3 matches GRA3 and when TCNT4 underflows Figure 10 53 Register Buffering Example 3 Buffering in Complementary PWM Mode TCNT3 and TCNT4 values Time GRA3 H 0999 H 0000 TCNT3 TCNT4 GRB3 H 1FFF BRB3 GRB3 TIOCA3 TIOCB3 H 0999 H 0999 H 0999 H 1FFF H 0999 H 1FFF H 1FFF H 0999 373 www DataSheet4U com ...

Page 386: ...master enable bit to 0 in TOER An arbitrary value can be output by appropriate settings of the data register DR and data direction register DDR of the corresponding input output port Figure 10 54 illustrates the timing of the enabling and disabling of ITU output by TOER Figure 10 54 Timing of Disabling of ITU Output by Writing to TOER Example ø Address bus TOER ITU output pin TOER address Timer ou...

Page 387: ... Output Inversion by TOCR The output levels in reset synchronized PWM mode and complementary PWM mode can be inverted by inverting the output level select bits OLS4 and OLS3 in TOCR Figure 10 56 shows the timing Figure 10 56 Timing of Inverting of ITU Output Level by Writing to TOCR Example ø TIOCA1 pin TOER ITU output I O port ITU output I O port Generic input output Generic input output ITU outp...

Page 388: ...egister GR The compare match signal is generated in the last state in which the values match when TCNT is updated from the matching count to the next count Therefore when TCNT matches a general register the compare match signal is not generated until the next timer clock input Figure 10 57 shows the timing of the setting of IMFA and IMFB Figure 10 57 Timing of Setting of IMFA and IMFB by Compare M...

Page 389: ...the corresponding general register Figure 10 58 shows the timing Figure 10 58 Timing of Setting of IMFA and IMFB by Input Capture Timing of Setting of Overflow Flag OVF OVF is set to 1 when TCNT overflows from H FFFF to H 0000 or underflows from H 0000 to H FFFF Figure 10 59 shows the timing Input capture signal N N ø IMF TCNT GR IMI 377 www DataSheet4U com ...

Page 390: ...atus flag while it is set to 1 then writes 0 in the status flag the status flag is cleared Figure 10 60 shows the timing Figure 10 60 Timing of Clearing of Status Flags Overflow signal H FFFF H 0000 ø TCNT OVF OVI ø Address IMF OVF TSR write cycle TSR address T1 T2 T3 378 www DataSheet4U com ...

Page 391: ...d a CPU interrupt is not requested Table 10 10 lists the interrupt sources Table 10 10 ITU Interrupt Sources Interrupt DMAC Channel Source Description Activatable Priority 0 IMIA0 Compare match input capture A0 Yes High IMIB0 Compare match input capture B0 No OVI0 Overflow 0 No 1 IMIA1 Compare match input capture A1 Yes IMIB1 Compare match input capture B1 No OVI1 Overflow 1 No 2 IMIA2 Compare mat...

Page 392: ...ween TCNT Write and Clear If a counter clear signal occurs in the T3 state of a TCNT write cycle clearing of the counter takes priority and the write is not performed See figure 10 61 Figure 10 61 Contention between TCNT Write and Clear ø Address bus Internal write signal TCNT write cycle TCNT address T1 T2 T3 380 www DataSheet4U com ...

Page 393: ...a TCNT word write cycle writing takes priority and TCNT is not incremented See figure 10 62 Figure 10 62 Contention between TCNT Word Write and Increment ø Address bus Internal write signal TCNT input clock TCNT N TCNT address M TCNT write data TCNT word write cycle T1 T2 T3 381 www DataSheet4U com ...

Page 394: ... TCNT byte that was not written retains its previous value See figure 10 63 which shows an increment pulse occurring in the T2 state of a byte write to TCNTH Figure 10 63 Contention between TCNT Byte Write and Increment ø Address bus Internal write signal TCNT input clock TCNTH TCNTL TCNTH byte write cycle T1 T2 T3 N TCNTH address M TCNT write data X X X 1 382 www DataSheet4U com ...

Page 395: ...riting takes priority and the compare match signal is inhibited See figure 10 64 Figure 10 64 Contention between General Register Write and Compare Match ø Address bus Internal write signal TCNT GR Compare match signal General register write cycle T1 T2 T3 N GR address M N N 1 General register write data Inhibited 383 www DataSheet4U com ...

Page 396: ...s priority and the counter is not incremented OVF is set to 1 The same holds for underflow See figure 10 65 Figure 10 65 Contention between TCNT Write and Overflow ø Address bus Internal write signal TCNT input clock Overflow signal TCNT OVF H FFFF TCNT address M TCNT write data TCNT write cycle T1 T2 T3 384 www DataSheet4U com ...

Page 397: ...of a general register read cycle the value before input capture is read See figure 10 66 Figure 10 66 Contention between General Register Read and Input Capture ø Address bus Internal read signal Input capture signal GR Internal data bus GR address X General register read cycle T1 T2 T3 X M 385 www DataSheet4U com ...

Page 398: ...cording to the input capture signal The counter is not incremented by the increment signal The value before the counter is cleared is transferred to the general register See figure 10 67 Figure 10 67 Contention between Counter Clearing by Input Capture and Counter Increment ø Input capture signal Counter clear signal TCNT input clock TCNT GR N N H 0000 386 www DataSheet4U com ...

Page 399: ...orm Period Setting When a counter is cleared by compare match the counter is cleared in the last state at which the TCNT value matches the general register value at the time when this value would normally be updated to the next count The actual counter frequency is therefore given by the following formula f f counter frequency ø system clock frequency N value set in general register ø Address bus ...

Page 400: ...the T3 state of a write cycle input capture takes priority and the write to the buffer register is not performed See figure 10 69 Figure 10 69 Contention between Buffer Register Write and Input Capture ø Address bus Internal write signal Input capture signal GR BR BR address Buffer register write cycle T1 T2 T3 N X M N TCNT value 388 www DataSheet4U com ...

Page 401: ... precautions Write to bits CMD1 and CMD0 only when TCNT3 and TCNT4 are stopped Do not switch directly between reset synchronized PWM mode and complementary PWM mode First switch to normal mode by clearing bit CMD1 to 0 then select reset synchronized PWM mode or complementary PWM mode Byte write to channel 2 or byte write to channel 3 TCNT2 TCNT3 W Y X Z TCNT2 TCNT3 A A X X TCNT2 TCNT3 Y Y A A W d ...

Page 402: ...ted Output compare B o o o IOB2 0 o o Other bits unrestricted Input capture A o PWM0 0 IOA2 1 o o o Other bits unrestricted Input capture B o PWM0 0 o IOB2 1 o o Other bits unrestricted Counter By compare o o o o CCLR1 0 o clearing match input CCLR0 1 capture A By compare o o o o CCLR1 1 o match input CCLR0 0 capture B Syn SYNC0 1 o o o CCLR1 1 o chronous CCLR0 1 clear Legend o Setting available v...

Page 403: ...ut capture A o PWM1 0 o 2 IOA2 1 o o o Other bits unrestricted Input capture B o PWM1 0 o IOB2 1 o o Other bits unrestricted Counter By compare o o o o CCLR1 0 o clearing match input CCLR0 1 capture A By compare o o o o CCLR1 1 o match input CCLR0 0 capture B Syn SYNC1 1 o o o CCLR1 1 o chronous CCLR0 1 clear Legend o Setting available valid Setting does not affect this mode Notes 1 The input capt...

Page 404: ...2 0 o o Other bits unrestricted Input capture A o o PWM2 0 IOA2 1 o o o Other bits unrestricted Input capture B o o PWM2 0 o IOB2 1 o o Other bits unrestricted Counter By compare o o o o o CCLR1 0 o clearing match input CCLR0 1 capture A By compare o o o o o CCLR1 1 o match input CCLR0 0 capture B Syn SYNC2 1 o o o o CCLR1 1 o chronous CCLR0 1 clear Phase counting o MDF 1 o o o o o mode Legend o S...

Page 405: ...1 0 CMD1 0 o o 1 o o CCLR1 1 o match input CCLR0 0 capture B Syn SYNC3 1 o Illegal setting o o o 1 o o CCLR1 1 o chronous CMD1 1 CCLR0 1 clear CMD0 0 Complementary o 3 CMD1 1 CMD1 1 o o 6 o o CCLR1 0 o 5 PWM mode CMD0 0 CMD0 0 CCLR0 0 Reset synchronized o CMD1 1 CMD1 1 o o 6 o o CCLR1 0 o PWM mode CMD0 1 CMD0 1 CCLR0 1 Buffering o o o o BFA3 1 o 1 o o o o BRA Other bits unrestricted Buffering o o ...

Page 406: ...B CMD0 0 Syn SYNC4 1 o Illegal setting o 4 o o 1 o o CCLR1 1 o chronous CMD1 1 CCLR0 1 clear CMD0 0 Complementary o 3 CMD1 1 CMD1 1 o o o o CCLR1 0 o 5 PWM mode CMD0 0 CMD0 0 CCLR0 0 Reset synchronized o CMD1 1 CMD1 1 o o o o o 6 o 6 PWM mode CMD0 1 CMD0 1 Buffering o o o o BFA4 1 o 1 o o o o BRA Other bits unrestricted Buffering o o o o BFB4 1 o 1 o o o o BRB Other bits unrestricted Legend o Sett...

Page 407: ...ximum 16 bit data can be output TPC output can be enabled on a bit by bit basis Four output groups Output trigger signals can be selected in 4 bit groups to provide up to four different 4 bit outputs Selectable output trigger signals Output trigger signals can be selected for each group from the compare match signals of four ITU channels Non overlap mode A non overlap margin can be provided betwee...

Page 408: ...gnals Pulse output pins group 3 PBDR PADR Legend TPMR TPCR NDERB NDERA PBDDR PADDR NDRB NDRA PBDR PADR Pulse output pins group 2 Pulse output pins group 1 Pulse output pins group 0 TPC output mode register TPC output control register Next data enable register B Next data enable register A Port B data direction register Port A data direction register Next data register B Next data register A Port B...

Page 409: ...tput 3 TP3 Output TPC output 4 TP4 Output Group 1 pulse output TPC output 5 TP5 Output TPC output 6 TP6 Output TPC output 7 TP7 Output TPC output 8 TP8 Output Group 2 pulse output TPC output 9 TP9 Output TPC output 10 TP10 Output TPC output 11 TP11 Output TPC output 12 TP12 Output Group 3 pulse output TPC output 13 TP13 Output TPC output 14 TP14 Output TPC output 15 TP15 Output 397 www DataSheet4U...

Page 410: ... register A NDERA R W H 00 H FFA5 Next data register A NDRA R W H 00 H FFA7 3 H FFA4 Next data register B NDRB R W H 00 H FFA6 3 Notes 1 Lower 16 bits of the address 2 Bits used for TPC output cannot be written 3 The NDRA address is H FFA5 when the same output trigger is selected for TPC output groups 0 and 1 by settings in TPCR When the output triggers are different the NDRA address is H FFA7 for...

Page 411: ...s 0 and 1 when these TPC output groups are used For further information about PADR see section 9 11 Port A Bit Initial value Read Write 7 PA DDR 0 W Port A data direction 7 to 0 These bits select input or output for port A pins 7 6 PA DDR 0 W 6 5 PA DDR 0 W 5 4 PA DDR 0 W 4 3 PA DDR 0 W 3 2 PA DDR 0 W 2 1 PA DDR 0 W 1 0 PA DDR 0 W 0 Bit Initial value Read Write 0 PA 0 R W 0 1 PA 0 R W 1 2 PA 0 R W...

Page 412: ...n these TPC output groups are used For further information about PBDR see section 9 12 Port B Bit Initial value Read Write 7 PB DDR 0 W Port B data direction 7 to 0 These bits select input or output for port B pins 7 6 PB DDR 0 W 6 5 PB DDR 0 W 5 4 PB DDR 0 W 4 3 PB DDR 0 W 3 2 PB DDR 0 W 2 1 PB DDR 0 W 1 0 PB DDR 0 W 0 Bit Initial value Read Write 0 PB 0 R W 0 1 PB 0 R W 1 2 PB 0 R W 2 3 PB 0 R W...

Page 413: ...by mode Same Trigger for TPC Output Groups 0 and 1 If TPC output groups 0 and 1 are triggered by the same compare match event the NDRA address is H FFA5 The upper 4 bits belong to group 1 and the lower 4 bits to group 0 Address H FFA7 consists entirely of reserved bits that cannot be modified and are always read as 1 Address H FFA5 Address H FFA7 Bit Initial value Read Write 7 NDR7 0 R W 6 NDR6 0 ...

Page 414: ...A7 are reserved bits that cannot be modified and are always read as 1 Address H FFA5 Address H FFA7 Bit Initial value Read Write 7 NDR7 0 R W 6 NDR6 0 R W 5 NDR5 0 R W 4 NDR4 0 R W 3 1 2 1 1 1 0 1 Reserved bits Next data 7 to 4 These bits store the next output data for TPC output group 1 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 NDR3 0 R W 2 NDR2 0 R W 1 NDR1 0 R W 0 NDR0 0 R W Next data 3 to...

Page 415: ...The upper 4 bits belong to group 3 and the lower 4 bits to group 2 Address H FFA6 consists entirely of reserved bits that cannot be modified and are always read as 1 Address H FFA4 Address H FFA6 Bit Initial value Read Write 7 NDR15 0 R W 6 NDR14 0 R W 5 NDR13 0 R W 4 NDR12 0 R W 3 NDR11 0 R W 2 NDR10 0 R W 1 NDR9 0 R W 0 NDR8 0 R W Next data 11 to 8 These bits store the next output data for TPC o...

Page 416: ...e reserved bits that cannot be modified and are always read as 1 Address H FFA4 Address H FFA6 Bit Initial value Read Write 7 NDR15 0 R W 6 NDR14 0 R W 5 NDR13 0 R W 4 NDR12 0 R W 3 1 2 1 1 1 0 1 Reserved bits Next data 15 to 12 These bits store the next output data for TPC output group 3 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 NDR11 0 R W 2 NDR10 0 R W 1 NDR9 0 R W 0 NDR8 0 R W Next data 1...

Page 417: ...nge NDERA is initialized to H 00 by a reset and in hardware standby mode It is not initialized in software standby mode Bits 7 to 0 Next Data Enable 7 to 0 NDER7 to NDER0 These bits enable or disable TPC output groups 1 and 0 TP7 to TP0 on a bit by bit basis Bits 7 to 0 NDER7 to NDER0 Description 0 TPC outputs TP7 to TP0 are disabled Initial value NDR7 to NDR0 are not transferred to PA7 to PA0 1 T...

Page 418: ...RB is initialized to H 00 by a reset and in hardware standby mode It is not initialized in software standby mode Bits 7 to 0 Next Data Enable 15 to 8 NDER15 to NDER8 These bits enable or disable TPC output groups 3 and 2 TP15 to TP8 on a bit by bit basis Bits 7 to 0 NDER15 to NDER8 Description 0 TPC outputs TP15 to TP8 are disabled Initial value NDR15 to NDR8 are not transferred to PB7 to PB0 1 TP...

Page 419: ...1 R W 0 G0CMS0 1 R W 2 G1CMS0 1 R W 1 G0CMS1 1 R W Group 3 compare match select 1 and 0 These bits select the compare match event that triggers TPC output group 3 TP to TP Group 2 compare match select 1 and 0 These bits select the compare match event that triggers TPC output group 2 TP to TP Group 1 compare match select 1 and 0 These bits select the compare match event that triggers TPC output gro...

Page 420: ...PC output group 3 TP15 to TP12 is triggered by Initial value compare match in ITU channel 3 Bits 5 and 4 Group 2 Compare Match Select 1 and 0 G2CMS1 G2CMS0 These bits select the compare match event that triggers TPC output group 2 TP11 to TP8 Bit 5 Bit 4 G2CMS1 G2CMS0 Description 0 0 TPC output group 2 TP11 to TP8 is triggered by compare match in ITU channel 0 1 TPC output group 2 TP11 to TP8 is t...

Page 421: ...C output group 1 TP7 to TP4 is triggered by Initial value compare match in ITU channel 3 Bits 1 and 0 Group 0 Compare Match Select 1 and 0 G0CMS1 G0CMS0 These bits select the compare match event that triggers TPC output group 0 TP3 to TP0 Bit 1 Bit 0 G0CMS1 G0CMS0 Description 0 0 TPC output group 0 TP3 to TP0 is triggered by compare match in ITU channel 0 1 TPC output group 0 TP3 to TP0 is trigger...

Page 422: ...pping TPC Output TPMR is initialized to H F0 by a reset and in hardware standby mode It is not initialized in software standby mode Bits 7 to 4 Reserved Read only bits always read as 1 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 G3NOV 0 R W 0 G0NOV 0 R W 2 G2NOV 0 R W 1 G1NOV 0 R W Group 3 non overlap Selects non overlapping TPC output for group 3 TP to TP Reserved bits Group 2 non overlap Sele...

Page 423: ...in group 2 independent 1 and 0 output at compare match A and B in the selected ITU channel Bit 1 Group 1 Non Overlap G1NOV Selects normal or non overlapping TPC output for group 1 TP7 to TP4 Bit 1 G1NOV Description 0 Normal TPC output in group 1 output values change at Initial value compare match A in the selected ITU channel 1 Non overlapping TPC output in group 1 independent 1 and 0 output at co...

Page 424: ... operating conditions Figure 11 2 TPC Output Operation Table 11 3 TPC Operating Conditions NDER DDR Pin Function 0 0 Generic input port 1 Generic output port 1 0 Generic input port but the DR bit is a read only bit and when compare match occurs the NDR bit value is transferred to the DR bit 1 TPC pulse output Sequential output of up to 16 bit patterns is possible by writing new output data to NDRA...

Page 425: ...are match event occurs Figure 11 3 shows the timing of these operations for the case of normal output in groups 2 and 3 triggered by compare match A Figure 11 3 Timing of Transfer of Next Data Register Contents and Output Example ø TCNT GRA Compare match A signal NDRB PBDR TP to TP 8 15 N N n m m N 1 n n 413 www DataSheet4U com ...

Page 426: ...nterrupt in TIER The DMAC can also be set up to transfer data to the next data register Set the initial output values in the DR bits of the input output port pins to be used for TPC output Set the DDR bits of the input output port pins to be used for TPC output to 1 Set the NDER bits of the pins to be used for TPC output to 1 Select the ITU compare match event to be used as the TPC output trigger ...

Page 427: ...terrupt H F8 is written in PBDDR and NDERB and bits G3CMS1 G3CMS0 G2CMS1 and G2CMS0 are set in TPCR to select compare match in the ITU channel set up in step 1 as the output trigger Output data H 80 is written in NDRB The timer counter in this ITU channel is started When compare match A occurs the NDRB contents are transferred to PBDR and output The compare match input capture A IMFA interrupt ser...

Page 428: ...rgin in GRA Select the counter clock source with bits TPSC2 to TPSC0 in TCR Select the counter clear source with bits CCLR1 and CCLR0 Enable the IMFA interrupt in TIER The DMAC can also be set up to transfer data to the next data register Set the initial output values in the DR bits of the input output port pins to be used for TPC output Set the DDR bits of the input output port pins to be used fo...

Page 429: ...r period is set in GRB The non overlap margin is set in GRA The IMIEA bit is set to 1 in TIER to enable IMFA interrupts This operation example is described below Bits G3NOV and G2NOV are set to 1 in TPMR to select non overlapping output Output data H 95 is written in NDRB The timer counter in this ITU channel is started When compare match B occurs outputs change from in TPCR to select compare matc...

Page 430: ... compare match If GRA functions as an input capture register in the ITU channel selected in TPCR TPC output will be triggered by the input capture signal Figure 11 8 shows the timing Figure 11 8 TPC Output Triggering by Input Capture Example ø TIOC pin Input capture signal NDR DR N N M 418 www DataSheet4U com ...

Page 431: ...which the output trigger event will not occur 11 4 2 Note on Non Overlapping Output During non overlapping operation the transfer of NDR bit values to DR bits takes place as follows 1 NDR bits are always transferred to DR bits at compare match A 2 At compare match B NDR bits are transferred only if their value is 0 Bits are not transferred if their value is 1 Figure 11 9 illustrates the non overla...

Page 432: ... the next data in NDR or by having the IMFA interrupt activate the DMAC The next data must be written before the next compare match B occurs Figure 11 10 shows the timing relationships Figure 11 10 Non Overlapping Operation and NDR Write Timing Compare match A Compare match B NDR write NDR NDR write DR 0 1 output 0 1 output 0 output 0 output Do not write to NDR in this interval Do not write to NDR...

Page 433: ...eatures WDT features are listed below Selection of eight counter clock sources ø 2 ø 32 ø 64 ø 128 ø 256 ø 512 ø 2048 or ø 4096 Interval timer option Timer counter overflow generates a reset signal or interrupt The reset signal is generated in watchdog timer operation An interval timer interrupt is generated in interval timer operation Watchdog timer reset signal resets the entire chip internally ...

Page 434: ... External output of the watchdog timer reset signal Note Open drain output ø 2 ø 32 ø 64 ø 128 ø 256 ø 512 ø 2048 ø 4096 TCNT TCSR RSTCSR Reset control Interrupt signal Reset internal external interval timer Interrupt control Overflow Clock Clock selector Read write control Internal data bus Internal clock sources Legend TCNT TCSR RSTCSR Timer counter Timer control status register Reset control st...

Page 435: ...ion R W Initial Value H FFA8 H FFA8 Timer control status register TCSR R W 3 H 18 H FFA9 Timer counter TCNT R W H 00 H FFAA H FFAB Reset control status register RSTCSR R W 3 H 3F Notes 1 Lower 16 bits of the address 2 Write word data starting at this address 3 Only 0 can be written in bit 7 to clear the flag 423 www DataSheet4U com ...

Page 436: ...elected by bits CKS2 to CKS0 in TCSR When the count overflows changes from H FF to H 00 the OVF bit is set to 1 in TCSR TCNT is initialized to H 00 by a reset and when the TME bit is cleared to 0 Note TCNT is write protected by a password For details see section 12 2 4 Notes on Register Access Bit Initial value Read Write 7 0 R W 6 0 R W 5 0 R W 4 0 R W 3 0 R W 0 0 R W 2 0 R W 1 0 R W 424 www Data...

Page 437: ...n their previous values Notes 1 TCSR differs from other registers in being more difficult to write For details see section 12 2 4 Notes on Register Access 2 Only 0 can be written to clear the flag Bit Initial value Read Write 7 OVF 0 R W 6 WT IT 0 R W 5 TME 0 R W 4 1 3 1 0 CKS0 0 R W 2 CKS2 0 R W 1 CKS1 0 R W Overflow flag Status flag indicating overflow Clock select These bits select the TCNT clo...

Page 438: ... interrupt request when TCNT overflows If used as a watchdog timer the WDT generates a reset signal when TCNT overflows Bit 6 WT IT Description 0 Interval timer requests interval timer interrupts Initial value 1 Watchdog timer generates a reset signal Bit 5 Timer Enable TME Selects whether TCNT runs or is halted When WT IT 1 clear the SYSCR software standby bit SSBY to 0 then set the TME to 1 When...

Page 439: ...overflow and controls external output of the reset signal Bits 7 and 6 are initialized by input of a reset signal at the RES pin They are not initialized by reset signals generated by watchdog timer overflow Notes 1 RSTCSR differs from other registers in being more difficult to write For details see section 12 2 4 Notes on Register Access 2 Only 0 can be written in bit 7 to clear the flag Bit Init...

Page 440: ...0 by reset signal input at RES pin Initial value Cleared by reading WRST when WRST 1 then writing 0 in WRST 1 Setting condition Set when TCNT overflow generates a reset signal during watchdog timer operation Bit 6 Reset Output Enable RSTOE Enables or disables external output at the RESO pin of the reset signal generated if TCNT overflows during watchdog timer operation Bit 6 RSTOE Description 0 Re...

Page 441: ...uctions Figure 12 2 shows the format of data written to TCNT and TCSR TCNT and TCSR both have the same write address The write data must be contained in the lower byte of the written word The upper byte must contain H 5A password for TCNT or H A5 password for TCSR This transfers the write data from the lower byte to TCNT or TCSR Figure 12 2 Format of Data Written to TCNT and TCSR 15 8 7 0 H 5A Wri...

Page 442: ... data Writing this word transfers a write data value into the RSTOE bit Figure 12 3 Format of Data Written to RSTCSR Reading TCNT TCSR and RSTCSR These registers are read like other registers Byte access instructions can be used The read addresses are H FFA8 for TCSR H FFA9 for TCNT and H FFAB for RSTCSR as listed in table 12 3 Table 12 3 Read Addresses of TCNT TCSR and RSTCSR Address Register H F...

Page 443: ...The watchdog reset signal can be externally output from the RESO pin to reset external system devices The reset signal is output externally for 132 states External output can be enabled or disabled by the RSTOE bit in RSTCSR A watchdog reset has the same vector as a reset generated by input at the RES pin Software can distinguish a RES reset from a watchdog reset by checking the WRST bit in RSTCSR...

Page 444: ...R An interval timer interrupt request is generated at each TCNT overflow This function can be used to generate interval timer interrupts at regular intervals Figure 12 5 Interval Timer Operation TCNT count value Time t Interval timer interrupt Interval timer interrupt Interval timer interrupt Interval timer interrupt WT 0 TME 1 IT H FF H 00 432 www DataSheet4U com ...

Page 445: ...lag in TCSR The OVF flag is set to 1 when TCNT overflows At the same time a reset signal is generated in watchdog timer operation or an interval timer interrupt is generated in interval timer operation Figure 12 6 Timing of Setting of OVF ø TCNT Overflow signal OVF H FF H 00 433 www DataSheet4U com ...

Page 446: ...ng The WRST bit is set to 1 when TCNT overflows and OVF is set to 1 At the same time an internal reset signal is generated for the entire chip This internal reset signal clears OVF to 0 but the WRST bit remains set to 1 The reset routine must therefore clear the WRST bit Figure 12 7 Timing of Setting of WRST Bit and Internal Reset ø TCNT Overflow signal OVF WRST H FF H 00 WDT internal reset 434 ww...

Page 447: ...clock pulse is generated during the T3 state of a write cycle to TCNT the write takes priority and the timer count is not incremented See figure 12 8 Figure 12 8 Contention between TCNT Write and Increment Changing CKS2 to CKS0 Values Halt TCNT by clearing the TME bit to 0 in TCSR before changing the values of bits CKS2 to CKS0 ø TCNT TCNT N M Counter write data T3 T2 T1 Write cycle CPU writes to ...

Page 448: ...card For details see section 14 Smart Card Interface 13 1 1 Features SCI features are listed below Selection of asynchronous or synchronous mode for serial communication a Asynchronous mode Serial data communication is synchronized one character at a time The SCI can communicate with a universal asynchronous receiver transmitter UART asynchronous communication interface adapter ACIA or other chip ...

Page 449: ...simultaneously The transmitting and receiving sections are both double buffered so serial data can be transmitted and received continuously Built in baud rate generator with selectable bit rates Selectable transmit receive clock sources internal clock from baud rate generator or external clock from the SCK pin Four types of interrupts Transmit data empty transmit end receive data full and receive ...

Page 450: ...l data bus Transmit receive control Baud rate generator ø ø 4 ø 16 ø 64 Clock Parity generate Parity check TEI TXI RXI ERI Legend External clock RSR RDR TSR TDR SMR SCR SSR BRR Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register 439 www DataSheet4U com ...

Page 451: ...ynchronous or synchronous mode specify the data format and bit rate and control the transmitter and receiver sections Table 13 2 Registers Channel Address 1 Name Abbreviation R W Initial Value 0 H FFB0 Serial mode register SMR R W H 00 H FFB1 Bit rate register BRR R W H FF H FFB2 Serial control register SCR R W H 00 H FFB3 Transmit data register TDR R W H FF H FFB4 Serial status register SSR R W 2...

Page 452: ... 2 Receive Data Register RDR RDR is the register that stores received serial data When the SCI finishes receiving 1 byte of serial data it transfers the received data from RSR into RDR for storage RSR is then ready to receive the next data This double buffering allows data to be received continuously RDR is a read only register Its contents cannot be modified by the CPU RDR is initialized to H 00 ...

Page 453: ... cannot read or write TSR directly 13 2 4 Transmit Data Register TDR TDR is an 8 bit register that stores data for serial transmission When the SCI detects that TSR is empty it moves transmit data written in TDR from TDR into TSR and starts serial transmission Continuous serial transmission is possible by writing the next transmit data in TDR during serial transmission from TSR The CPU can always ...

Page 454: ...R W 6 CHR 0 R W 5 PE 0 R W 4 O E 0 R W 3 STOP 0 R W 0 CKS0 0 R W 2 MP 0 R W 1 CKS1 0 R W Communication mode Selects asynchronous or synchronous mode Clock select 1 0 These bits select the baud rate generator s clock source Character length Selects character length in asynchronous mode Parity enable Selects whether a parity bit is added Parity mode Selects even or odd parity Stop bit length Selects...

Page 455: ... transmitted Bit 5 Parity Enable PE In asynchronous mode this bit enables or disables the addition of a parity bit to transmit data and the checking of the parity bit in receive data In synchronous mode the parity bit is neither added nor checked regardless of the PE setting Bit 5 PE Description 0 Parity bit not added or checked Initial value 1 Parity bit added and checked Note When PE is set to 1...

Page 456: ...mit data makes an odd number of 1s in the transmitted character and parity bit combined Receive data must have an odd number of 1s in the received character and parity bit combined Bit 3 Stop Bit Length STOP Selects one or two stop bits in asynchronous mode This setting is used only in asynchronous mode In synchronous mode no stop bit is added so the STOP bit setting is ignored Bit 3 STOP Descript...

Page 457: ... 3 3 Multiprocessor Communication Bit 2 MP Description 0 Multiprocessor function disabled Initial value 1 Multiprocessor format selected Bits 1 and 0 Clock Select 1 and 0 CKS1 0 These bits select the clock source of the on chip baud rate generator Four clock sources are available ø ø 4 ø 16 and ø 64 For the relationship between the clock source bit rate register setting and baud rate see section 1...

Page 458: ...0 R W 3 MPIE 0 R W 0 CKE0 0 R W 2 TEIE 0 R W 1 CKE1 0 R W Transmit interrupt enable Enables or disables transmit data empty interrupts TXI Clock enable 1 0 These bits select the SCI clock source Receive interrupt enable Enables or disables receive data full interrupts RXI and receive error interrupts ERI Transmit enable Enables or disables the transmitter Receive enable Enables or disables the rec...

Page 459: ...om RSR to RDR also enables or disables the receive error interrupt ERI Bit 6 RIE Description 0 Receive data full RXI and receive error ERI interrupt requests are disabled Initial value 1 Receive data full RXI and receive error ERI interrupt requests are enabled Note RXI and ERI interrupt requests can be cleared by reading the value 1 from the RDRF FER PER or ORER flag then clearing it to 0 or by c...

Page 460: ...n SMR The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0 Bit 3 MPIE Description 0 Multiprocessor interrupts are disabled normal receive operation Initial value Clearing conditions The MPIE bit is cleared to 0 MPB 1 in received data 1 Multiprocessor interrupts are enabled Receive data full interrupts RXI receive error interrupts ERI and setting of the RDRF FER and OR...

Page 461: ... internally clocked CKE1 0 The CKE0 setting is ignored in synchronous mode or when an external clock source is selected CKE1 1 Select the SCI operating mode in SMR before setting the CKE1 and CKE0 bits For further details on selection of the SCI clock source see table 13 9 in section 13 3 Operation Bit 1 Bit 0 CKE1 CKE0 Description 0 0 Asynchronous mode Internal clock SCK pin available for generic...

Page 462: ...an be written in TDR Multiprocessor bit transfer Value of multi processor bit to be transmitted Receive data register full Status flag indicating that data has been received and stored in RDR Overrun error Status flag indicating detection of a receive overrun error Framing error Status flag indicating detection of a receive framing error Parity error Status flag indicating detection of a receive p...

Page 463: ...ting conditions The chip is reset or enters standby mode The TE bit in SCR is cleared to 0 TDR contents are loaded into TSR so new data can be written in TDR Bit 6 Receive Data Register Full RDRF Indicates that RDR contains new receive data Bit 6 RDRF Description 0 RDR does not contain new receive data Initial value Clearing conditions The chip is reset or enters standby mode Software reads RDRF w...

Page 464: ...ing is also disabled Bit 4 Framing Error FER Indicates that data reception ended abnormally due to a framing error in asynchronous mode Bit 4 FER Description 0 Receiving is in progress or has ended normally Initial value 1 Clearing conditions The chip is reset or enters standby mode Software reads FER while it is set to 1 then writes 0 1 A receive framing error occurred 2 Setting condition The sto...

Page 465: ...r occurs the SCI transfers the receive data into RDR but does not set the RDRF flag Serial receiving cannot continue while the PER flag is set to 1 In synchronous mode serial transmitting is also disabled Bit 2 Transmit End TEND Indicates that when the last bit of a serial character was transmitted TDR did not contain new transmit data so transmission has ended The TEND flag is a read only bit and...

Page 466: ...en a multiprocessor format is not selected or when the SCI is not transmitting Bit 0 MPBT Description 0 Multiprocessor bit value in transmit data is 0 Initial value 1 Multiprocessor bit value in transmit data is 1 13 2 8 Bit Rate Register BRR BRR is an 8 bit register that together with the CKS1 and CKS0 bits in SMR that select the baud rate generator clock source determines the serial communicatio...

Page 467: ... 6 6 99 0 6 2 48 0 7 0 0 9 2 34 19200 0 2 8 51 0 2 13 78 0 3 0 0 4 2 34 31250 0 1 0 0 1 4 86 0 1 22 88 0 2 0 38400 0 1 18 62 0 1 14 67 0 1 0 ø MHz 3 6864 4 4 9152 5 Bit Rate Error Error Error Error bits s n N n N n N n N 110 2 64 0 70 2 70 0 03 2 86 0 31 2 88 0 25 150 1 191 0 1 207 0 16 1 255 0 2 64 0 16 300 1 95 0 1 103 0 16 1 127 0 1 129 0 16 600 0 191 0 0 207 0 16 0 255 0 1 64 0 16 1200 0 95 0 ...

Page 468: ...0 0 25 0 16 19200 0 9 2 34 0 9 0 0 11 0 0 12 0 16 31250 0 5 0 0 5 2 40 0 6 5 33 0 7 0 38400 0 4 2 34 0 4 0 0 5 0 0 6 6 99 ø MHz 9 8304 10 12 12 288 Bit Rate Error Error Error Error bits s n N n N n N n N 110 2 174 0 26 2 177 0 25 2 212 0 03 2 217 0 08 150 2 127 0 2 129 0 16 2 155 0 16 2 159 0 300 1 255 0 2 64 0 16 2 77 0 16 2 79 0 600 1 127 0 1 129 0 16 1 155 0 16 1 159 0 1200 0 255 0 1 64 0 16 1 ...

Page 469: ...03 0 16 2400 0 168 0 16 0 181 0 16 0 191 0 0 207 0 16 4800 0 84 0 43 0 90 0 16 0 95 0 0 103 0 16 9600 0 41 0 76 0 45 0 93 0 47 0 0 51 0 16 19200 0 20 0 76 0 22 0 93 0 23 0 0 25 0 16 31250 0 12 0 00 0 13 0 0 14 1 70 0 15 0 38400 0 10 3 82 0 10 3 57 0 11 0 0 12 0 16 Table 13 3 Examples of Bit Rates and BRR Settings in Asynchronous Mode cont ø MHz 18 Bit Rate Error bits s n N 110 3 79 0 12 150 2 233 ...

Page 470: ... 4 0 9 0 19 0 24 0 39 0 44 250 k 0 1 0 3 0 7 0 9 0 12 0 15 0 17 500 k 0 0 0 1 0 3 0 4 0 7 0 8 1 M 0 0 0 1 0 3 0 4 2 M 0 0 0 1 2 5 M 0 0 4 M 0 0 Note Settings with an error of 1 or less are recommended Legend Blank No setting available Setting possible but error occurs Continuous transmit receive not possible The BRR setting is calculated as follows Asynchronous mode N 106 1 Synchronous mode N 106 ...

Page 471: ...SMR Settings n Clock Source CKS1 CKS0 0 ø 0 0 1 ø 4 0 1 2 ø 16 1 0 3 ø 64 1 1 The bit rate error in asynchronous mode is calculated as follows Error 1 100 ø 106 N 1 B 64 22n 1 460 www DataSheet4U com ...

Page 472: ...requencies Asynchronous Mode Settings ø MHz Maximum Bit Rate bits s n N 2 62500 0 0 2 097152 65536 0 0 2 4576 76800 0 0 3 93750 0 0 3 6864 115200 0 0 4 125000 0 0 4 9152 153600 0 0 5 156250 0 0 6 187500 0 0 6 144 192000 0 0 7 3728 230400 0 0 8 250000 0 0 9 8304 307200 0 0 10 312500 0 0 12 375000 0 0 12 288 384000 0 0 14 437500 0 0 14 7456 460800 0 0 16 500000 0 0 17 2032 537600 0 0 18 562500 0 0 4...

Page 473: ...4576 0 6144 38400 3 0 7500 46875 3 6864 0 9216 57600 4 1 0000 62500 4 9152 1 2288 76800 5 1 2500 78125 6 1 5000 93750 6 144 1 5360 96000 7 3728 1 8432 115200 8 2 0000 125000 9 8304 2 4576 153600 10 2 5000 156250 12 3 0000 187500 12 288 3 0720 192000 14 3 5000 218750 14 7456 3 6864 230400 16 4 0000 250000 17 2032 4 3008 268800 18 4 5000 281250 462 www DataSheet4U com ...

Page 474: ...onous Mode ø MHz External Input Clock MHz Maximum Bit Rate bits s 2 0 3333 333333 3 4 0 6667 666666 7 6 1 0000 1000000 0 8 1 3333 1333333 3 10 1 6667 1666666 7 12 2 0000 2000000 0 14 2 3333 2333333 3 16 2 6667 2666666 7 18 3 0000 3000000 0 463 www DataSheet4U com ...

Page 475: ...rors parity errors overrun errors and the break state An internal or external clock can be selected as the SCI clock source When an internal clock is selected the SCI operates using the on chip baud rate generator and can output a serial clock signal with a frequency matching the bit rate When an external clock is selected the external clock input must have a frequency 16 times the bit rate The on...

Page 476: ... 0 7 bit data 1 bit 0 1 1 1 2 bits 1 Synchronous 8 bit data Absent None mode Table 13 9 SMR and SCR Settings and SCI Clock Source Selection SMR SCR Settings Bit 7 Bit 1 Bit 0 C A CKE1 CKE0 Mode Clock Source SCK Pin Function 0 0 0 Asynchronous mode Internal SCI does not use the SCK pin 0 0 1 Outputs a clock with frequency matching the bit rate 0 1 0 External 0 1 1 1 0 0 Synchronous mode Internal Ou...

Page 477: ...n the mark high state The SCI monitors the line and starts serial communication when the line goes to the space low state indicating a start bit One serial character consists of a start bit low data LSB first parity bit high or low and stop bit high in that order When receiving in asynchronous mode the SCI synchronizes at the falling edge of the start bit The SCI samples each data bit on the eight...

Page 478: ...it data 7 bit data 7 bit data 7 bit data 7 bit data 8 bit data 8 bit data 7 bit data 7 bit data S S S S S S S S S S S S STOP STOP P STOP P STOP STOP STOP STOP STOP STOP STOP STOP P P MPB STOP STOP STOP MPB MPB MPB STOP STOP Legend S STOP P MPB Start bit Stop bit Parity bit Multiprocessor bit CHR PE MP STOP SMR Settings 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1...

Page 479: ... 3 Phase Relationship between Output Clock and Serial Data Asynchronous Mode Transmitting and Receiving Data SCI Initialization Asynchronous Mode Before transmitting or receiving clear the TE and RE bits to 0 in SCR then initialize the SCI as follows When changing the communication mode or format always clear the TE and RE bits to 0 before following the procedure given below Clearing TE to 0 sets ...

Page 480: ...d MPIE bits as necessary 4 1 bit interval elapsed Wait Wait for at least the interval required to transmit or receive 1 bit then set the TE or RE bit to 1 in SCR Set the RIE TIE TEIE and MPIE bits as necessary Setting the TE or RE bit enables the SCI to use the TxD or RxD pin Start of initialization Set CKE1 and CKE0 bits in SCR leaving TE and RE bits cleared to 0 Select the clock source in SCR Cl...

Page 481: ...E flag is 1 then write transmit data in TDR and clear the TDRE flag to 0 Read TEND flag in SSR TEND 1 No Yes Output break signal No Yes Clear TE bit to 0 in SCR 4 1 2 3 4 Clear DR bit to 0 set DDR bit to 1 Initialize To continue transmitting serial data after checking that the TDRE flag is 1 indicating that data can be written write data in TDR then clear the TDRE flag to 0 When the DMAC is activa...

Page 482: ...bits are output Mark state Output of 1 bits continues until the start bit of the next transmit data The SCI checks the TDRE flag when it outputs the stop bit If the TDRE flag is 0 the SCI loads new data from TDR into TSR outputs the stop bit then begins serial transmission of the next frame If the TDRE flag is 1 the SCI sets the TEND flag to 1 in SSR outputs the stop bit then continues output of 1...

Page 483: ... SSR to identify the error After executing the necessary error handling clear the ORER PER and FER flags all to 0 Receiving cannot resume if any of the ORER PER and FER flags remains set to 1 When a framing error occurs the RxD pin can be read to detect the break state SCI status check and receive data read read SSR check that RDRF is set to 1 then read receive data from RDR and clear the RDRF fla...

Page 484: ...Serial Data 2 No No No No Yes Yes Yes Yes Framing error handling PER 1 ORER 1 Overrun error handling FER 1 Break Error handling Parity error handling Clear ORER PER and FER flags to 0 in SSR Clear RE bit to 0 in SCR End 3 473 www DataSheet4U com ...

Page 485: ...RDR If one of the checks fails receive error the SCI operates as indicated in table 13 11 Note When a receive error occurs further receiving is disabled In receiving the RDRF flag is not set to 1 Be sure to clear the error flags to 0 When the RDRF flag is set to 1 if the RIE bit is set to 1 in SCR a receive data full interrupt RXI is requested If the ORER PER or FER flag is set to 1 and the RIE bi...

Page 486: ...mmunicate as data with the multiprocessor bit set to 1 Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0 Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1 When they receive data with the multiprocessor bit set to 1 receiving processors compare the data with their IDs The receiving processor with a matchin...

Page 487: ...rocessors using Multiprocessor Format Sending Data H AA to Receiving Processor A Transmitting processor Receiving processor A Serial communication line Receiving processor B Receiving processor C Receiving processor D ID 01 ID 02 ID 03 ID 04 Serial data H 01 H AA MPB 1 MPB 0 ID sending cycle receiving processor address Data sending cycle data sent to receiving processor specified by ID Legend MPB ...

Page 488: ...ically SCI status check and transmit data write read SSR check that the TDRE flag is 1 then write transmit data in TDR Also set the MPBT flag to 0 or 1 in SSR Finally clear the TDRE flag to 0 To continue transmitting serial data after checking that the TDRE flag is 1 indicating that data can be written write data in TDR then clear the TDRE flag to 0 When the DMAC is activated by a transmit data em...

Page 489: ...he start bit of the next transmit data The SCI checks the TDRE flag when it outputs the stop bit If the TDRE flag is 0 the SCI loads data from TDR into TSR outputs the stop bit then begins serial transmission of the next frame If the TDRE flag is 1 the SCI sets the TEND flag in SSR to 1 outputs the stop bit then continues output of 1 bits in the mark state If the TEIE bit is set to 1 in SCR a tran...

Page 490: ... and ID check read SSR check that the RDRF flag is set to 1 then read data from RDR and compare with the processor s own ID If the ID does not match set the MPIE bit to 1 again and clear the RDRF flag to 0 If the ID matches clear the RDRF flag to 0 SCI status check and data receiving read SSR check that the RDRF flag is set to 1 then read data from RDR Receive error handling and break detection if...

Page 491: ...Receiving Multiprocessor Serial Data 2 No No Yes No Yes Yes Error handling ORER 1 Overrun error handling FER 1 Break Framing error handling Clear ORER PER and FER flags to 0 in SSR Clear RE bit to 0 in SCR End 5 480 www DataSheet4U com ...

Page 492: ...MPIE 0 MPB detection MPIE 0 RXI handler reads RDR data and clears RDRF flag to 0 Not own ID so MPIE bit is set to 1 again No RXI request RDR not updated a Own ID does not match data 1 Start bit 0 D0 D1 D7 1 Stop bit 1 Data ID2 MPB Start bit 0 D0 D1 D7 0 Stop bit 1 Data data2 MPB 1 Idle mark state MPIE RDRF RDR value ID2 RXI request multiprocessor interrupt RXI interrupt handler reads RDR data and ...

Page 493: ...receives data by synchronizing with the rise of the serial clock Communication Format The data length is fixed at 8 bits No parity bit or multiprocessor bit can be added Clock An internal clock generated by the on chip baud rate generator or an external clock input from the SCK pin can be selected by clearing or setting the CKE1 bit in SCR See table 13 9 When the SCI operates on an internal clock ...

Page 494: ...E and RE bits to 0 in SCR 1 bit interval elapsed Start transmitting or receiving No Yes 1 2 3 4 Select the clock source in SCR Clear the RIE TIE TEIE MPIE TE and RE bits to 0 Select the communication format in SMR Write the value corresponding to the bit rate in BRR This step is not necessary when an external clock is used 1 2 Set RIE TIE TEIE MPIE CKE1 and CKE0 bits in SCR leaving TE and RE bits ...

Page 495: ...tting TE bit to 1 output 1 from frame one transmission is possible SCI status check and transmit data write read SSR check that the TDRE flag is 1 then write transmit data in TDR and clear the TDRE flag to 0 Read TEND flag in SSR No Yes 1 2 3 Initialize Clear TE bit to 0 in SCR To continue transmitting serial data after checking that the TDRE flag is 1 indicating that data can be written write dat...

Page 496: ... clock pulses If an external clock source is selected the SCI outputs data in synchronization with the input clock Data is output from the TxD pin in order from LSB bit 0 to MSB bit 7 The SCI checks the TDRE flag when it outputs the MSB bit 7 If the TDRE flag is 0 the SCI loads data from TDR into TSR and begins serial transmission of the next frame If the TDRE flag is 1 the SCI sets the TEND flag ...

Page 497: ...17 Example of SCI Transmit Operation Transmit direction Serial clock Serial data TDRE TEND Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TXI interrupt handler writes data in TDR and clears TDRE flag to 0 TXI request TEI request 1 frame TXI request 486 www DataSheet4U com ...

Page 498: ...ata function of the RxD pin is selected automatically Receive error handling if a receive error occurs read the ORER flag in SSR then after executing the necessary error handling clear the ORER flag to 0 Neither transmitting nor receiving can resume while the ORER flag remains set to 1 SCI status check and receive data read read SSR check that the RDRF flag is set to 1 then read receive data from ...

Page 499: ...ansferred from RSR to RDR If this check passes the RDRF flag is set to 1 and the received data is stored in RDR If the check does not pass receive error the SCI operates as indicated in table 13 11 After setting the RDRF flag to 1 if the RIE bit is set to 1 in SCR the SCI requests a receive data full interrupt RXI If the ORER flag is set to 1 and the RIE bit in SCR is also set to 1 the SCI request...

Page 500: ...igure 13 20 shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates the procedure to follow Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RXI request Receive direction RDRF ORER RXI interrupt handler reads data in RDR and clears RDRF flag to 0 Overrun error ERI request 1 frame RXI request 489 www DataSheet4U com ...

Page 501: ...ed from 0 to 1 can also be given by the TXI interrupt Receive error handling if a receive error occurs read the ORER flag in SSR then after executing the neces sary error handling clear the ORER flag to 0 Neither transmitting nor receiving can resume while the ORER flag remains set to 1 SCI status check and receive data read read SSR check that the RDRF flag is 1 then read receive data from RDR an...

Page 502: ...can activate the DMAC to transfer data Data transfer by the DMAC automatically clears the TDRE flag to 0 The TEI interrupt request cannot activate the DMAC The RXI interrupt is requested when the RDRF flag is set to 1 in SSR The ERI interrupt is requested when the ORER PER or FER flag is set to 1 in SSR The RXI interrupt request can activate the DMAC to transfer data Data transfer by the DMAC auto...

Page 503: ...flag is set to 1 Simultaneous Multiple Receive Errors Table 13 13 indicates the state of SSR status flags when multiple receive errors occur simultaneously When an overrun error occurs the RSR contents are not transferred to RDR so receive data is lost Table 13 13 SSR Status Flags and Transfer of Receive Data Receive Data Transfer RDRF ORER FER PER RSR RDR Receive Errors 1 1 0 0 Overrun error 0 0 ...

Page 504: ...re both be set to 1 beforehand To send a break signal during serial transmission clear the DR bit to 0 then clear the TE bit to 0 When the TE bit is cleared to 0 the transmitter is initialized regardless of its current state so the TxD pin becomes an output port outputting the value 0 Receive Error Flags and Transmitter Operation Synchronous Mode Only When a receive error flag ORER PER or FER is s...

Page 505: ...L 9 to 12 F Absolute deviation of clock frequency From equation 1 if F 0 and D 0 5 the receive margin is 46 875 as given by equation 2 D 0 5 F 0 M 0 5 1 2 16 100 46 875 2 This is a theoretical value A reasonable margin to allow in system designs is 20 to 30 Internal base clock Receive data RxD Synchronization sampling timing Data sampling timing 0 7 15 0 7 15 0 D0 D1 8 clocks 16 clocks Start bit M...

Page 506: ... an external clock after clearing SSR of TDRE maintain the space between each frame of the lead of the transmission clock start up edge at five states or more see Figure 13 22 This condition is also needed for continuous transmission If it is not fulfilled operational error will occur Figure 13 22 Serial Clock Transmission Example Ensure that t 5 states SCK TDRE TXD t t Continuous transmission X0 ...

Page 507: ...he H8 3048 Series are listed below Asynchronous communication Data length 8 bits Parity bits generated and checked Error signal output in receive mode parity error Error signal detect and automatic data retransmit in transmit mode Supports both direct convention and inverse convention Built in baud rate generator with selectable bit rates Three types of interrupts Transmit data empty receive data ...

Page 508: ...eceive control RDR TSR RSR Bus interface SSR SCR SMR TDR Legend SCMR RSR RDR TSR TDR SMR SCR SSR BRR Smart card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register ø ø 4 ø 16 ø 64 TXI Clock Parity generate Parity check RxD0 TxD0 SCK0 RXI ERI 498 www DataSheet4...

Page 509: ...R and RDR have their normal serial communication interface functions as described in section 13 Serial Communication Interface Table 14 2 Registers Address 1 Name Abbreviation R W Initial Value H FFB0 Serial mode register SMR R W H 00 H FFB1 Bit rate register BRR R W H FF H FFB2 Serial control register SCR R W H 00 H FFB3 Transmit data register TDR R W H FF H FFB4 Serial status register SSR R W 2 ...

Page 510: ...DIR Selects the serial parallel conversion format Bit 3 SDIR Description 0 TDR contents are transmitted LSB first Initial value Received data is stored LSB first in RDR 1 TDR contents are transmitted MSB first Received data is stored MSB first in RDR Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 SDIR 0 R W 0 SMIF 0 R W 2 SINV 0 R W 1 1 Reserved bits Smart card data transfer direction Selects the ...

Page 511: ...it 0 Smart Card Interface Mode Select SMIF Enables the smart card interface function Bit 0 SMIF Description 0 Smart card interface function is disabled Initial value 1 Smart card interface function is enabled 14 2 2 Serial Status Register SSR The function of SSR bit 4 is modified in the smart card interface This change also causes a modification to the setting conditions for bit 2 TEND Bit Initial...

Page 512: ...ror signal was sampled Note Clearing the TE bit to 0 in SCR does not affect the ERS flag which retains its previous value Bits 3 to 0 These bits operate as in normal serial communication For details see section 13 Serial Communication Interface The setting conditions for transmit end TEND bit 2 however are modified as follows Bit 2 TEND Description 0 Transmission is in progress Clearing conditions...

Page 513: ...mode comprises serial control register bit 1 and bit 0 Bit 7 GM Description 0 Using the regular smart card interface mode The TEND flag is set 12 5 etu after the beginning of the start bit Initial value Clock output on off control only 1 Using the GSM mode smart card interface mode The TEND flag is set 11 0 etu after the beginning of the start bit Clock output on off and fixed high fixed low contr...

Page 514: ...g of the normal clock output and specify a fixed high level or fixed low level for the clock output SMR SCR Bit 7 Bit 1 Bit 0 GM CKE1 CKE0 Description 0 0 0 The internal clock SCK0 pin functions as an I O port Initial value 0 0 1 The internal clock SCK0 pin functions as the clock output 1 0 0 The internal clock SCK0 pin is fixed at low level output 1 0 1 The internal clock SCK0 pin functions as th...

Page 515: ...y asynchronous communication is supported There is no synchronous communication function 14 3 2 Pin Connections Figure 14 2 shows a pin connection diagram for the smart card interface In communication with a smart card data is transmitted and received over the same signal line The TxD0 and RxD0 pins should both be connected to this line The data transmission line should be pulled up to VCC through...

Page 516: ...o request retransmission In transmit mode the error signal is sampled and the same data is retransmitted if the error signal is low Figure 14 3 Smart Card Interface Data Format H8 3048 Series Chip Card processing device Smart card TxD0 RxD0 SCK0 Px port I O CLK RST Data line VCC Clock line Reset line Ds Parity error D0 D1 D2 D3 Output from transmitting device Output from receiving device D4 D5 D6 ...

Page 517: ...stor 4 The receiving device performs a parity check If there is no parity error the receiving device waits to receive the next data If a parity error is present the receiving device outputs a low error signal DE to request retransmission of the data After outputting the error signal for a designated interval the receiving device returns the signal line to the high impedance state The signal line i...

Page 518: ... GSM mode set the GM bit to 1 Clear the O E bit to 0 if the smart card uses the direct convention Set the O E bit to 1 if the smart card uses the inverse convention Bits CKS1 and CKS0 select the clock source of the built in baud rate generator See section 14 3 5 Clock Bit Rate Register BRR Settings This register sets the bit rate Equations for calculating the setting are given in section 14 3 5 Cl...

Page 519: ...vention SDIR SINV O E 1 In the inverse convention state A corresponds to the logic level 1 and state Z to the logic level 0 Characters are transmitted and received MSB first In the example above the first character data is H 3F Following the even parity rule designated for smart cards the parity bit logic level is 0 corresponding to state Z In the H8 3048 Series the SINV bit inverts only the data ...

Page 520: ...setting 0 N 255 B Bit rate bits s ø System clock frequency MHz n See table 14 4 Table 14 4 n Values of CKS1 and CKS0 Settings n CKS1 CKS0 0 0 0 1 0 1 2 1 0 3 1 1 Note If the gear function is used to divide the system clock frequency use the divided frequency to calculate the bit rate The equation above applies directly to 1 1 frequency division Table 14 5 Bit Rates bits s for Different BRR Setting...

Page 521: ...0 14 2848 16 00 18 00 Bit s N Error N Error N Error N Error N Error N Error N Error 9600 0 0 00 1 30 00 1 25 00 1 8 99 1 0 00 1 12 01 2 15 99 Table 14 7 Maximum Bit Rates for Various Frequencies Smart Card Interface ø MHz Maximum Bit Rate bits s N n 7 1424 9600 0 0 10 13441 0 0 10 7136 14400 0 0 13 17473 0 0 14 2848 19200 0 0 16 21505 0 0 18 24194 0 0 The bit rate error is calculated from the foll...

Page 522: ... 0 in the TIE RIE TE RE MPIE TEIE and CKE1 bits If bit CKE0 is set to 1 a serial clock will be output from the SCK0 pin 7 Wait for at least the interval required to transmit or receive one bit then set the TIE RIE TE and RE bits as necessary in SCR Do not set TE and RE both to 1 except when performing a loop back test Transmitting Serial Data The transmitting procedure in smart card mode is differ...

Page 523: ...ure 14 6 If the TXI interrupt activates the DMAC the number of bytes designated in the DMAC can be transmitted automatically including automatic retransmit For details see Interrupt Operations and Data Transfer by DMAC in this section Figure 14 4 Transmit Flowchart Example FER ERS 0 TEND 1 FER ERS 0 TEND 1 All data transmitted Initialize Write data in TDR and clear TDRE flag to 0 in SSR Clear TE b...

Page 524: ...n case of normal transmission TEND flag is set In case of transmit error ERS flag is set Steps 2 and 3 above are repeated until the TEND flag is set Data 1 Note When the ERS flag is set it should be cleared until transfer of the last bit D7 in LSB first transmission D0 in MSB first transmission of the next transfer data to be transmitted has been completed I O data Guard GM 1 GM 0 TXI TEND interru...

Page 525: ...et carry out the necessary error handling then clear both the ORER and PER flags to 0 3 Check that the RDRF flag is set to 1 Repeat steps 2 and 3 until this check passes 4 Read receive data from RDR 5 To continue receiving data clear the RDRF flag to 0 and return to step 2 6 To terminate receiving clear the RE bit to 0 Figure 14 7 Receive Flowchart Example 515 ORER 0 and PER 0 RDRF 1 All data rece...

Page 526: ...ize the smart card interface clearing RE to 0 and setting TE to 1 Completion of receive operations is indicated by the RDRF PER or ORER flag To switch from transmit mode to receive mode check that transmitting operations have completed then initialize the smart card interface clearing TE to 0 and setting RE to 1 Completion of transmit operations can be verified from the TEND flag Fixing Clock Outp...

Page 527: ...MAC will therefore automatically transmit the designated number of bytes including retransmission when an error occurs When an error occurs the ERS flag is not cleared automatically so the RIE bit should be set to 1 to enable the error to generate an ERI request and the ERI interrupt handler should clear ERS When using the DMAC to transmit or receive first set up and enable the DMAC then make SCI ...

Page 528: ...r the software standby state 2 Set the CKE1 bit in SCR to the value for the fixed output state at the start of software standby the current P94 pin state 3 Set smart card interface mode and output the clock Clock signal generation is started with the normal duty cycle Figure 14 9 Procedure for Stopping and Restarting the Clock Use the following procedure to secure the clock duty cycle after poweri...

Page 529: ...uency In receiving the SCI synchronizes internally with the fall of the start bit which it samples on the base clock Receive data is latched at the rising edge of the 186th base clock pulse See figure 14 10 Figure 14 10 Receive Data Sampling Timing in Smart Card Mode 372 clocks 186 clocks 185 185 Internal base clock Receive data RxD Synchronization sampling timing Data sampling timing 0 D1 D0 371 ...

Page 530: ... F 1 F 100 M Receive margin N Ratio of clock frequency to bit rate N 372 D Clock duty cycle D 0 to 1 0 L Frame length L 10 F Absolute deviation of clock frequency From this equation if F 0 and D 0 5 the receive margin is as follows D 0 5 F 0 M 0 5 1 2 372 100 49 866 1 2N D 0 5 N 520 www DataSheet4U com ...

Page 531: ... flag is not set in SSR 4 If an error is not detected when the parity bit is checked receiving operations are assumed to have ended normally and the RDRF bit is automatically set to 1 in SSR If the RIE bit in SCR is set to the enable state an RXI interrupt is requested If RXI is enabled as a DMA transfer activation source the RDR contents can be read automatically When the DMAC reads the RDR data ...

Page 532: ...et in SSR 9 If no error signal is returned from the receiving device transmission of the frame including retransmission is assumed to be complete and the TEND bit is set to 1 in SSR If the TIE bit in SCR is set to the enable state a TXI interrupt is requested If TXI is enabled as a DMA transfer activation source the next data can be written in TDR automatically When the DMAC writes data in TDR it ...

Page 533: ...analog voltage conversion range can be programmed by input of an analog reference voltage at the VREF pin High speed conversion Conversion time maximum 7 4 µs per channel with 18 MHz system clock Two conversion modes Single mode A D conversion of one channel Scan mode continuous conversion on one to four channels Four 16 bit data registers A D conversion results are transferred for storage into da...

Page 534: ... ADCR Successive approximations register 10 bit D A AV V AV CC REF SS Analog multi plexer AN AN AN AN AN AN AN AN 0 1 2 3 4 5 6 7 Sample and hold circuit Comparator Control circuit ADTRG ø 8 ø 16 ADI Legend ADCR ADCSR ADDRA ADDRB ADDRC ADDRD A D control register A D control status register A D data register A A D data register B A D data register C A D data register D 524 www DataSheet4U com ...

Page 535: ...g power supply pin AVCC Input Analog power supply Analog ground pin AVSS Input Analog ground and reference voltage Reference voltage pin VREF Input Analog reference voltage Analog input pin 0 AN0 Input Group 0 analog inputs Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Group 1 analog inputs Analog input pin 5 AN5 Input Analog in...

Page 536: ...data register B high ADDRBH R H 00 H FFE3 A D data register B low ADDRBL R H 00 H FFE4 A D data register C high ADDRCH R H 00 H FFE5 A D data register C low ADDRCL R H 00 H FFE6 A D data register D high ADDRDH R H 00 H FFE7 A D data register D low ADDRDL R H 00 H FFE8 A D control status register ADCSR R W 2 H 00 H FFE9 A D control register ADCR R W H 7E Notes 1 Lower 16 bits of the address 2 Only ...

Page 537: ...analog input channels and A D data registers The CPU can always read and write the A D data registers The upper byte can be read directly but the lower byte is read through a temporary register TEMP For details see section 15 3 CPU Interface The A D data registers are initialized to H 0000 by a reset and in standby mode Table 15 3 Analog Input Channels and A D Data Registers Analog Input Channel G...

Page 538: ...E 0 R W 5 ADST 0 R W 4 SCAN 0 R W 3 CKS 0 R W 0 CH0 0 R W 2 CH2 0 R W 1 CH1 0 R W Note Only 0 can be written to clear the flag A D end flag Indicates end of A D conversion A D interrupt enable Enables and disables A D end interrupts A D start Starts or stops A D conversion Scan mode Selects single mode or scan mode Clock select Selects the A D conversion time Channel select 2 to 0 These bits selec...

Page 539: ...A D end interrupt request ADI is disabled Initial value 1 A D end interrupt request ADI is enabled Bit 5 A D Start ADST Starts or stops A D conversion The ADST bit remains set to 1 during A D conversion It can also be set to 1 by external trigger input at the ADTRG pin Bit 5 ADST Description 0 A D conversion is stopped Initial value 1 Single mode A D conversion starts ADST is automatically cleared...

Page 540: ...ching the conversion time Bit 3 CKS Description 0 Conversion time 266 states maximum Initial value 1 Conversion time 134 states maximum Bits 2 to 0 Channel Select 2 to 0 CH2 to CH0 These bits and the SCAN bit select the analog input channels Clear the ADST bit to 0 before changing the channel selection Group Selection Channel Selection Description CH2 CH1 CH0 Single Mode Scan Mode 0 0 0 AN0 Initia...

Page 541: ...bles external triggering of A D conversion Bit 7 TRGE Description 0 A D conversion cannot be externally triggered Initial value 1 A D conversion starts at the falling edge of the external trigger signal ADTRG Bits 6 to 0 Reserved Read only bits always read as 1 Bit Initial value Read Write 7 TRGE 0 R W 6 1 5 1 4 1 3 1 0 1 2 1 1 1 Trigger enable Enables or disables external triggering of A D conver...

Page 542: ...P Next when the lower byte is read the TEMP contents are transferred to the CPU When reading an A D data register always read the upper byte before the lower byte It is possible to read only the upper byte but if only the lower byte is read incorrect data may be obtained Figure 15 2 shows the data flow for access to an A D data register Figure 15 2 A D Data Register Access Operation Reading H AA40...

Page 543: ...After making the necessary changes set the ADST bit to 1 to start A D conversion again The ADST bit can be set at the same time as the mode or channel is changed Typical operations when channel 1 AN1 is selected in single mode are described next Figure 15 3 shows a timing diagram for this example 1 Single mode is selected SCAN 0 input channel AN1 is selected CH2 CH1 0 CH0 1 the A D interrupt is en...

Page 544: ...e Idle A D conversion 1 A D conversion 2 Idle Read conversion result A D conversion result 1 Read conversion result A D conversion result 2 Note Vertical arrows indicate instructions executed by software 0 1 2 3 A D conversion starts ADDRA ADDRB ADDRC ADDRD State of channel 1 AN State of channel 2 AN State of channel 3 AN Idle 534 www DataSheet4U com ...

Page 545: ...nnel in the group The ADST bit can be set at the same time as the mode or channel selection is changed Typical operations when three channels in group 0 AN0 to AN2 are selected in scan mode are described next Figure 15 4 shows a timing diagram for this example 1 Scan mode is selected SCAN 1 scan group 0 is selected CH2 0 analog input channels AN0 to AN2 are selected CH1 1 CH0 0 and A D conversion ...

Page 546: ...dle A D conversion 2 Idle A D conversion 5 Idle A D conversion 3 Idle Idle Transfer A D conversion result 1 A D conversion result 4 A D conversion result 2 A D conversion result 3 1 2 A D conversion time Notes 2 1 ADDRA ADDRB ADDRC ADDRD State of channel 1 AN State of channel 2 AN State of channel 3 AN Vertical arrows indicate instructions executed by software Data currently being converted is ign...

Page 547: ...ength of tD varies depending on the timing of the write access to ADCSR The total conversion time therefore varies within the ranges indicated in table 15 4 In scan mode the values given in table 15 4 apply to the first conversion In the second and subsequent conversions the conversion time is fixed at 256 states when CKS 0 or 128 states when CKS 1 Figure 15 5 A D Conversion Timing ø Address bus W...

Page 548: ... conversion can be externally triggered When the TRGE bit is set to 1 in ADCR external trigger input is enabled at the ADTRG pin A high to low transition at the ADTRG pin sets the ADST bit to 1 in ADCSR starting A D conversion Other operations in both single and scan modes are the same as if the ADST bit had been set to 1 by software Figure 15 6 shows the timing Figure 15 6 External Trigger Input ...

Page 549: ...C 0 3V 2 AVCC VREF ANn AVSS VSS N 0 to 7 Note Restriction for the ZTATTM version only The S Mask version of ZTATTM the Flash Memory version and Mask ROM version can be used regularly without restriction Failure to observe points 1 2 3 and 4 above may degrade chip reliability 5 Note on Board Design In board layout separate the digital circuits from the analog circuits as much as possible Particular...

Page 550: ...values input to the analog input pins AN0 to AN7 will be smoothed which may give rise to error Error can also occur if A D conversion is frequently performed in scan mode so that the current that charges and discharges the capacitor in the sample and hold circuit of the A D converter becomes greater than that input to the analog input pins via input impedance Rin The circuit constants should there...

Page 551: ...ge value 0000000000 to 0000000001 figure 15 10 Full scale error Deviation from ideal A D conversion characteristic of analog input voltage required to raise digital output from 1111111110 to 1111111111 figure 15 10 Quantization error Intrinsic error of the A D converter 1 2 LSB figure 15 9 Nonlinearity error Deviation from ideal A D conversion characteristic in range from zero volts to full scale ...

Page 552: ...A D Converter Accuracy Definitions 1 111 110 101 100 011 010 001 000 1 8 2 8 3 8 4 8 5 8 6 8 7 8 FS Quantization error Analog input voltage Digital output Ideal A D conversion characteristic 542 www DataSheet4U com ...

Page 553: ...impedance of the signal source is not a problem A large external capacitor however acts as a low pass filter This may make it impossible to track analog signals with high dv dt e g a variation of 5 mV µs figure 15 11 To convert high speed analog signals or to use scan mode insert a low impedance buffer 9 Effect on Absolute Accuracy Attaching an external capacitor creates a coupling with ground so ...

Page 554: ...15 11 Analog Input Circuit Example Equivalent circuit of A D converter H8 3048 Series 20 pF Cin 15 pF 10 kΩ Up to 10 kΩ Low pass filter Up to 0 1 µF Sensor output impedance Sensor input 544 www DataSheet4U com ...

Page 555: ...t voltage 0 V to VREF D A outputs can be sustained in software standby mode 16 1 2 Block Diagram Figure 16 1 shows a block diagram of the D A converter Figure 16 1 D A Converter Block Diagram DADR0 DADR1 DACR DASTCR V AV DA DA AV REF CC SS 0 1 Legend DACR DADR0 DADR1 DASTCR 8 bit D A Module data bus Bus interface On chip data bus Control circuit D A control register D A data register 0 D A data re...

Page 556: ...annel 0 Analog output pin 1 DA1 Output Analog output channel 1 Reference voltage input pin VREF Input Analog reference voltage 16 1 4 Register Configuration Table 16 2 summarizes the D A converter s registers Table 16 2 D A Converter Registers Address Name Abbreviation R W Initial Value H FFDC D A data register 0 DADR0 R W H 00 H FFDD D A data register 1 DADR1 R W H 00 H FFDE D A control register ...

Page 557: ... in standby mode 16 2 2 D A Control Register DACR DACR is an 8 bit readable writable register that controls the operation of the D A converter DACR is initialized to H 1F by a reset and in standby mode Bit Initial value Read Write 7 0 R W 6 0 R W 5 0 R W 4 0 R W 3 0 R W 2 0 R W 1 0 R W 0 0 R W Bit Initial value Read Write 7 DAOE1 0 R W 6 DAOE0 0 R W 5 DAE 0 R W 4 1 3 1 2 1 1 1 0 1 D A output enabl...

Page 558: ...rolled together in channels 0 and 1 Output of the conversion results is always controlled independently by DAOE0 and DAOE1 Bit 7 Bit 6 Bit 5 DAOE1 DAOE0 DAE Description 0 0 D A conversion is disabled in channels 0 and 1 0 1 0 D A conversion is enabled in channel 0 D A conversion is disabled in channel 1 0 1 1 D A conversion is enabled in channels 0 and 1 1 0 0 D A conversion is disabled in channel...

Page 559: ...ode Bits 7 to 1 Reserved Read only bits always read as 1 Bit 0 D A Standby Enable DASTE Enables or disables D A output in software standby mode Bit 0 DASTE Description 0 D A output is disabled in software standby mode Initial value 1 D A output is enabled in software standby mode Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 0 DASTE 0 R W 2 1 1 1 Reserved bits D A standby enable Enables or disa...

Page 560: ...0 becomes an output pin The converted result is output after the conversion time The output value is DADR0 contents 256 VREF Output of this conversion result continues until the value in DADR0 is modified or the DAOE0 bit is cleared to 0 3 If the DADR0 value is modified conversion starts immediately and the result is output after the conversion time 4 When the DAOE0 bit is cleared to 0 DA0 becomes...

Page 561: ...ld prior to the transition to software standby mode When D A output is enabled in software standby mode the reference supply current is the same as during normal operation 16 5 Usage Notes When using an D A converter note the following 1 VCC AVCC 0 3V 2 AVCC VREF ANn AVSS VSS N 0 to 7 Note Restriction for the ZTATTM version only The S Mask version of ZTATTM the Flash Memory version and Mask ROM ve...

Page 562: ...f the H8 3045 and H8 3044 are assigned to addresses H FF710 to H FFF0F in modes 1 2 5 and 7 and to addresses H FFF710 to H FFFF0F in modes 3 4 and 6 The RAM enable bit RAME in the system control register SYSCR can enable or disable the on chip RAM 17 1 1 Block Diagram Figure 17 1 shows a block diagram of the on chip RAM Figure 17 1 RAM Block Diagram H FEF10 H FEF12 H FFF0E H FEF11 H FEF13 H FFF0F ...

Page 563: ...rolled by SYSCR Table 17 1 gives the address and initial value of SYSCR Table 17 1 System Control Register Address Name Abbreviation R W Initial Value H FFF2 System control register SYSCR R W H 0B Note Lower 16 bits of the address 554 www DataSheet4U com ...

Page 564: ... chip RAM The RAME bit is initialized at the rising edge of the input at the RES pin It is not initialized in software standby mode Bit 0 RAME Description 0 On chip RAM is disabled 1 On chip RAM is enabled Initial value Bit Initial value Read Write 7 SSBY 0 R W 6 STS2 0 R W 5 STS1 0 R W 4 STS0 0 R W 3 UE 1 R W 2 NMIEG 0 R W 1 1 0 RAME 1 R W Software standby Standby timer select 2 to 0 User bit ena...

Page 565: ... In modes 1 to 6 expanded modes when the RAME bit is cleared to 0 the off chip address space is accessed In mode 7 single chip mode when the RAME bit is cleared to 0 the on chip RAM is not accessed read access always results in H FF data and write access is ignored Since the on chip RAM is connected to the CPU by an internal 16 bit data bus it can be written and read by word access It can also be ...

Page 566: ... Mode MD2 MD1 MD0 On Chip ROM Mode 1 1 Mbyte expanded mode with on chip ROM disabled 0 0 1 Mode 2 1 Mbyte expanded mode with on chip ROM disabled 0 1 0 Mode 3 16 Mbyte expanded mode with on chip ROM disabled 0 1 1 Mode 4 16 Mbyte expanded mode with on chip ROM disabled 1 0 0 Mode 5 1 Mbyte expanded mode with on chip ROM enabled 1 0 1 Enabled Mode 6 16 Mbyte expanded mode with on chip ROM enabled 1...

Page 567: ... diagram of the ROM Figure 18 1 ROM Block Diagram H8 3048 Mode 7 H 0000 H 0002 H 1FFFE H 0001 H 0003 H 1FFFF On chip data bus upper 8 bits On chip data bus lower 8 bits On chip ROM Even addresses Odd addresses Bus interface 558 www DataSheet4U com ...

Page 568: ...using a general purpose PROM programmer with a socket adapter to convert to 32 pins Table 18 3 lists the socket adapter for each package option Figure 18 2 shows the pin assignments of the socket adapter Figure 18 3 shows a memory map in PROM mode Table 18 3 Socket Adapter Preliminary Microcontroller Package Socket Adapter H8 3048 100 pin QFP FP 100B HS3042ESHS1H 100 pin TQFP TFP 100B HS3042ESNS1H...

Page 569: ... EO EO EA EA EA EA EA EA EA EA EA OE EA EA EA EA EA CE V V PROM Socket HN27C101 32 Pins 1 26 3 2 31 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 32 16 Legend V EO to EO EA to EA OE CE PGM Programming voltage 12 5 V Data input output Address input Output enable Chip enable Program PP CC SS PP Note Pins not shown in this diagram should be left open This figure shows pin assignme...

Page 570: ...Figure 18 3 H8 3048 Memory Map in PROM Mode On chip PROM H 00000 H 00000 H 1FFFF H 1FFFF Address in MCU mode Address in PROM mode 561 www DataSheet4U com ...

Page 571: ...t supported Do not select page programming mode A PROM programmer that supports only page programming mode cannot be used When selecting a PROM programmer check that it supports a byte at a time high speed programming mode Be sure to set the address range to H 00000 to H 1FFFF 18 3 1 Programming and Verification An efficient high speed programming procedure can be used to program and verify PROM d...

Page 572: ...e V 6 0 V 0 25 V V 12 5 V 0 3 V CC PP Address 0 PW Verification OK Program with t 0 2n ms OPW Last address Set read mode V 5 0 V 0 25 V V V CC PP CC All addresses read End Fail n 25 Address 1 address No Yes No Yes No No Program with t 0 2 ms 5 n 0 n 1 n Yes Yes 563 www DataSheet4U com ...

Page 573: ...IH 2 4 VCC 0 3 V voltage EA16 to EA0 OE CE PGM Input low EO7 to EO0 VIL 0 3 0 8 V voltage EA16 to EA0 OE CE PGM Output high EO7 to EO0 VOH 2 4 V IOH 200 µA voltage Output low EO7 to EO0 VOL 0 45 V IOL 1 6 mA voltage Input leakage EO7 to EO0 ILI 2 µA Vin 5 25 V 0 5 V current EA16 to EA0 OE CE PGM VCC current ICC 40 mA VPP current IPP 40 mA 564 www DataSheet4U com ...

Page 574: ...2 µs Programming pulse width tPW 0 19 0 20 0 21 ms PGM pulse width for overwrite tOPW 3 0 19 5 25 ms programming VCC setup time tVCS 2 µs CE setup time tCES 2 µs Data output delay time tOE 0 150 ns Notes 1 Input pulse level 0 8 V to 2 2 V Input rise time and fall time 20 ns Timing reference levels 1 0 V and 2 0 V for input 0 8 V and 2 0 V for output 2 tDF is defined at the point where the output i...

Page 575: ...fy Timing Address Data VPP VCC CE PGM OE VPP VCC VCC VCC Program Verify Input data Output data tAS tDS tVPS tVCS tCES tPW tOPW tDH tOES tOE tDF tAH Note t is defined by the value given in the flowchart OPW 1 566 www DataSheet4U com ...

Page 576: ...PP will be 12 5 V Before programming check that the chip is correctly mounted in the PROM programmer Overcurrent damage to the chip can result if the index marks on the PROM programmer socket adapter and chip are not correctly aligned Don t touch the socket adapter or chip while programming Touching either of these can cause contact faults and write errors Select the programming mode carefully The...

Page 577: ...cedure Figure 18 6 Recommended Screening Procedure If a series of programming errors occurs while the same PROM programmer is in use stop programming and check the PROM programmer and socket adapter for defects Please inform Hitachi of any abnormal conditions noted during or after programming or in screening of program data after high temperature baking Install Program chip and verify programmed d...

Page 578: ...ctrons stored in the floating gate to tunnel out After erasure the threshold voltage drops A memory cell is read like an EPROM cell by driving the gate to the high level and detecting the drain current which depends on the threshold voltage Erasing must be done carefully because if a memory cell is overerased its threshold voltage may become negative causing the cell to operate incorrectly Section...

Page 579: ...ry area Mode 2 0 1 0 External memory area Mode 3 0 1 1 External memory area Mode 4 1 0 0 External memory area Mode 5 1 0 1 On chip flash memory area Mode 6 1 1 0 On chip flash memory area Mode 7 1 1 1 On chip flash memory area 18 4 3 Features Features of the flash memory are listed below Five flash memory operating modes The flash memory has five operating modes program mode program verify mode er...

Page 580: ...8 3048F aligns its bit rate automatically to the host bit rate 9600 bps 4800 bps and 2400 bps Flash memory emulation by RAM Part of the RAM area can be overlapped onto flash memory to emulate flash memory updates in real time PROM mode As an alternative to on board programming the flash memory can be programmed and erased in PROM mode using a general purpose PROM programmer Protect modes Flash mem...

Page 581: ... H 1FFFE H 00001 H 00003 H 00005 H 1FFFD H 1FFFF MD2 MD1 MD0 Internal data bus upper Internal data bus lower Bus interface and control section Operating mode On chip flash memory 128 kbytes Upper byte even address Lower byte odd address Legend FLMCR EBR1 EBR2 Flash memory control register Erase block register 1 Erase block register 2 8 8 572 www DataSheet4U com ...

Page 582: ...a input The transmit data and receive data pins are used in boot mode 18 4 6 Register Configuration The flash memory is controlled by the registers listed in table 18 10 Table 18 10 Flash Memory Registers Address Name Abbreviation R W Initial Value H FF40 Flash memory control FLMCR R W 2 H 00 1 register H FF42 Erase block register 1 EBR1 R W 2 H 00 1 H FF43 Erase block register 2 EBR2 R W 2 H 00 1...

Page 583: ...al value R W 7 0 VPP EV 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R R W R W R W R W R W PV E P Reserved bits Erase mode Designates transition to or exit from erase mode Program mode Designates transition to or exit from program mode Program verify mode Designates transition to or exit from program verify mode Erase verify mode Designates transition to or exit from erase verify mode Programming power Status flag...

Page 584: ...ltage exceeding VH is applied to the VPP pin The flash memory can be written and erased Hardware Protect Disabled is displayed Note For correct write and erase functions the setting should be VPP 12 0 V to 0 6 V 11 4 V to 12 6 V Bit 6 VPP Enable VPPE Disables or enables 12 V application to the VPP pin After this bit is set it is necessary to wait for at least 5 µs for the internal power supply to ...

Page 585: ...on 0 Exit from erase mode Initial value 1 Transition to erase mode Bit 0 Program Mode P 1 2 Selects transition to or exit from program mode Bit 0 P Description 0 Exit from program mode Initial value 1 Transition to program mode Notes 1 Do not set two or more of these bits simultaneously Do not turn off power supply VCC VPP while a bit is set 2 For each bit setting procedure follow the algorithm de...

Page 586: ...erased Figure 18 8 shows a block map Note The initial value is H 00 in modes 5 6 and 7 on chip flash memory enabled In modes 1 2 3 and 4 on chip flash memory disabled this register cannot be modified and is always read as H FF Bits 7 to 0 Large Block 7 to 0 LB7 to LB0 These bits select large blocks LB7 to LB0 to be programmed and erased Bits 7 to 0 LB7 to LB0 Description 0 Block LB7 to LB0 is not ...

Page 587: ...erased Figure 18 8 shows a block map Note The initial value is H 00 in modes 5 6 and 7 on chip flash memory enabled In modes 1 2 3 and 4 on chip flash memory disabled this register cannot be modified and is always read as H FF Bits 7 to 0 Small Block 7 to 0 SB7 to SB0 These bits select small blocks SB7 to SB0 to be programmed and erased Bits 7 to 0 SB7 to SB0 Description 0 Block SB7 to SB0 is not ...

Page 588: ...FF H 1FC00 H 1FDFF H 1FE00 H 1FFFF 16 kbytes 16 kbytes 16 kbytes 16 kbytes 16 kbytes 16 kbytes 16 kbytes 12 kbytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes Large block area 124 kbytes Small block area 4 kbytes H 00000 H 03FFF H 04000 H 07FFF H 08000 H 0BFFF H 0C000 H 0FFFF H 10000 H 13FFF H 14000 H 17FFF H 18000 H 1BFFF H 1C000 H 1F1FF H 1F200 H 1F3FF H 1F400...

Page 589: ...d error protection 1 is in effect Setting conditions Flash memory was read 2 while being programmed or erased including vector or instruction fetch but not including reading of a RAM area overlapped onto flash memory A hardware exception handling sequence other than a reset trace exception invalid instruction trap instruction or zero divide exception was executed just before programming or erasing...

Page 590: ... to 0 RAM2 to RAM0 These bits are used with bit 3 to reassign an area to RAM see table 18 11 They are initialized by a reset and in hardware standby mode They are not initialized in software standby mode Table 18 11 RAM Area Reassignment Bit 3 Bit 2 Bit 1 Bit 0 RAM Area RAMS RAM2 RAM1 RAM0 H FFF000 to H FFF1FF 0 0 1 0 1 0 1 H 01F000 to H 01F1FF 1 0 0 0 H 01F200 to H 01F3FF 1 0 0 1 H 01F400 to H 01...

Page 591: ... on the host machine which may be a personal computer Serial communication interface 1 SCI1 is used in asynchronous mode see figure 18 9 If the H8 3048F is placed in boot mode after it comes out of reset a built in boot program is activated This program starts by measuring the low period of data transmitted from the host and setting the bit rate register BRR accordingly The H8 3048F s built in ser...

Page 592: ...transmitted to indicate completion 5 On receiving one byte from H8 3048F to indicate completion of bit rate adjustment the host confirms regular reception then transmits one byte of H 55 H8 3048F transmits H AA to indicate regular reception 6 After H8 3048F receives H 55 it branches to boot program area H FFF300 to H FFFEFF 7 When H8 3048F branches to boot program area H FFF300 to H FFFEFF it conf...

Page 593: ...the SCI operate normally set the host s bit rate to a value 2400 4800 or 9600 bps 1 Table 18 13 lists typical host bit rates and indicates the clock frequency ranges over which the H8 3048F can align its bit rate automatically Boot mode should be used within these frequency ranges 2 Table 18 13 System Clock Frequencies Permitting Automatic Bit Rate Alignment by H8 3048F System Clock Frequencies Pe...

Page 594: ...s been programmed into the flash memory if all data are not H FF all flash memory blocks are erased Boot mode is for use when user program mode is unavailable e g the first time on board programming is performed or if the update program activated in user program mode is accidentally erased 3 Interrupts cannot be used while the flash memory is being programmed or erased User program transfer area H...

Page 595: ...f the 12 V applied to the MD2 pin and the VPP pin is erased then reset is erased 1 However please note the following When transferring from boot mode to regular mode VPP 12 V MD2 12 V before transfer the erase must be carried out by the reset input personal computer internal boot mode RES pin After VPP interrupt erase reset The time needed until reset vector lead is flash memory read setup tFRS 2 ...

Page 596: ...and cutting VPP refer to 18 10 section 4 of Programming and Erasing Flash Memory 18 6 2 User Program Mode When set to user program mode the H8 3048F can erase and program its flash memory by executing a user program On board updates of the on chip flash memory can be carried out by providing on board circuits for supplying VPP and data and storing an update program in part of the program area To s...

Page 597: ...the on board update program into RAM 4 Following a branch to the program in RAM the on board update program is executed VPPE bit in FLMCR is set to update flash memory Wait 5 to 10µs to stabilize internal power supply Update program is executed 5 After the on board update ends clear the VPPE bit then a branch is made to the updated user application program and this program is executed After cleari...

Page 598: ...and erasing of the flash memory must be stored and executed in on chip RAM or in external memory A description of each mode is given below with recommended flowcharts and sample programs for programming and erasing High reliability programming and erasing algorithms are used which double the programming or erase processing time for each step Section 18 10 Flash Memory Programming and Erasing Preca...

Page 599: ...ting program mode set up the watchdog timer so as to prevent overprogramming 18 7 2 Program Verify Mode In program verify mode after data has been programmed in program mode the data is read to check that it has been programmed correctly After the programming time has elapsed exit programming mode clear the P bit to 0 and select program verify mode set the PV bit to 1 In program verify mode a prog...

Page 600: ... block register set bit of block to be programmed to 1 Wait z µs V E PP Clear bit Clear erase block register clear bit of programmed block to 0 V E PP Clear bit Set V E bit V E bit 1 in FLMCR PP Clear erase block register clear bit of block to be programmed to 0 PP Notes 1 Write the data to be programmed using a byte transfer instruction 2 Set the watchdog timer overflow interval by setting CKS2 a...

Page 601: ...can be calculated as indicated under table 18 14 FLMCR EQU FFFF40 EBR1 EQU FFFF42 EBR2 EQU FFFF43 TCSR EQU FFFFA8 PRGM MOV W 0001 R0 Program verify fail count MOV W g R1 Set program loop counter MOV W 4140 R4 MOV B R4L FLMCR 8 Set VPPE bit LOOP0 DEC W 1 R1 BPL LOOP0 MOV B R0H MOV B R0H EBR 8 Set EBR MOV B R3H ER2 Dummy write MOV W a E4 Set initial program loop counter value PRGMS MOV W A579 R4 Sta...

Page 602: ... voltage stress or impairing the reliability of programmed data To erase flash memory before starting to erase first place all memory data in all blocks to be erased in the programmed state program all memory data to H 00 If all memory data is not in the programmed state follow the sequence described later to program the memory data to zero To select the flash memory areas to be erased first set t...

Page 603: ...y voltage to the memory cells at the latched address If the flash memory is read in this state the data at the latched address will be read After the dummy write wait 2 µs before reading If the read data has been successfully erased perform the dummy write wait 2 µs and erase verify for the next address If the read data has not been erased select erase mode again and repeat the same erase and eras...

Page 604: ...ock to 0 End of block erase Clear EV bit Erase error n N n 5 Erase verify ends Erasing ends n 1 Double the erase time x 2 x n Wait z µs V E PP Set bit bit 1 in FLMCR V E PP Clear bit V E PP Clear bit Wait x ms V E PP Wait tVS2 µs Clear erase block register clear bit of block to be erased to 0 Notes 1 Program all addresses to be erased by following the prewrite flowchart 2 Set the watchdog timer ov...

Page 605: ...ogramming error Address 1 address OK Yes Set erase block register set bit of block to be erased to 1 Wait z µs n 1 V E PP Clear bit Clear erase block register clear bit of block to be erased to 0 V E PP Set bit bit 1 in FLMCR V E PP Clear erase block register clear bit of block to be erased to 0 Clear VPPE bit Notes 1 Use a byte transfer instruction 2 Set the watchdog timer overflow interval by se...

Page 606: ...ss of block to be erased MOV L BLKSTR 32 ER1 ER1 top address of block to be erased MOV L BLKEND 32 ER2 ER2 last address of block to be erased Execute prewrite PREWRT MOV W g R4 Set wait counter MOV W 4140 R6 MOV B R6L FLMCR 8 Set VPPE bit LOOPR0 DEC W 1 R4 BPL LOOPR0 SET EBR1 or EBR2 bit of block to be erased MOV B R5H MOV B R5H EBR Set EBR PREWRN SUB B R0H R0H R0 prewrite verify fail count MOV W ...

Page 607: ...op address of block to be erased MOV W d E4 Set initial erase loop counter value ERASE CMP W 025A R0 R0 H 025A erase verify fail count 603 BEQ ABEND2 If R0 H 025A branch to ABEND2 INC W 1 R0 Erase verify fail count 1 R0 MOV W E4 R4 MOV W f R5 Start watchdog timer MOV W R5 TCSR 16 MOV B 42 R5H Set E bit MOV B R5H FLMCR 8 LOOPE PUSH L ER5 POP L ER5 PUSH L ER5 POP L ER5 PUSH L ER5 POP L ER5 DEC W 1 R...

Page 608: ... verify address 1 R3 CMP W 0004 R0 BGE KEEP Erase executed 4 times SHLL W E4 Double erase loop counter value KEEP BRA ERASE Erase again OKEND MOV W 4000 R5 MOV B R5H FLMCR 8 Clear EV bit MOV W 0000 R5 MOV W R5 EBR1 16 Clear EBR1 and EBR2 MOV B R5L FLMCR 8 Clear VPPE bit One block erased ABEND1 MOV W 0000 R5 MOV W R5 EBR1 16 Clear EBR1 and EBR2 MOV B R5L FLMCR 8 Clear VPPE bit Programming error ABE...

Page 609: ...No Yes Yes No No Yes No Yes No good OK Erasing ends All erased blocks verified Erase verify next block Yes No Yes V E PP Clear bit Clear erase block registers clear bits of blocks to be erased to 0 n 4 Wait tVS2 µs Wait z µs V E PP Clear bit PP PP Set V E bit V E bit 1 in FLMCR Double the erase time x 2 x Notes 1 Program all addresses to be erased by following the prewrite flowchart 2 Set the watc...

Page 610: ...g for erasing specific blocks are shown next Example to erase blocks LB2 SB7 and SB0 R6 is set as follows MOV W 0481 R6 MOV W R6 EBR1 The values of a c d e f g and h in the program depend on the clock frequency They can be calculated as indicated in tables 18 14 and 18 15 For RAMSTR in the program substitute the starting destination address in RAM to be used when this program is moved from flash m...

Page 611: ... 08 R1L BCC BC0 BTST R1L R0H BNE PREWRT BRA PWADD1 BC0 BTST R1L R0L Test R1 th bit in R0 BNE PREWRT If R1 th bit in R0 is 1 branch to PREWRT PWADD1 INC B R1L R1L 1 R1L MOV L ER2 ER3 Dummy increment ER2 BRA PRETST Execute prewrite PREWRT MOV L ER2 ER3 ER3 prewrite starting address MOV L ER2 ER4 ER4 top address of next block MOV W g E5 Wait counter MOV W 4140 R5 MOV B R5L FLMCR 8 Set VPPE bit LOOPR0...

Page 612: ...alue BRA PREWRS Prewrite again PWVFOK INC L 1 ER3 Address 1 ER3 CMP L ER4 ER3 Last address BEQ PWADD2 BRA PREW PWADD2 INC B R1L Used to test R1L 1 th bit in R0 BRA PRETST Branch to PRETST Execute erase ERASES MOV W R6 EBR1 16 Set EBR1 EBR2 SUB W E6 E6 E6 erase verify fail count MOV W d E0 Set initial erase loop counter value ERASE MOV W f R5 MOV W R5 TCSR 16 Start watchdog timer MOV W E0 E1 Set er...

Page 613: ...R1 BNE ERSEVF BRA ADD01 BC1 BTST R1L R0L Test R1 th bit in R0L EBR2 BNE ERSEVF If R1 th bit in R0 is 1 branch to ERSEVF ADD01 INC B R1L R1L 1 R1L MOV L ER2 ER3 Dummy increment R2 BRA EBRTST ERSEVF MOV L ER2 ER3 ER3 top address of block to be erase verified MOV L ER2 ER4 ER4 top address of next block EVR2 MOV B FF R5H MOV B R5H ER3 Dummy write MOV W h R5 R5 erase verify loop counter LOOPDW DEC W 1 ...

Page 614: ... DATA L 00008000 8000 LB2 DATA L 0000C000 C000 LB3 DATA L 00010000 10000 LB4 DATA L 00014000 14000 LB5 DATA L 00018000 18000 LB6 DATA L 0001C000 1C000 LB7 DATA L 0001F000 1F000 SB0 DATA L 0001F200 1F200 SB1 DATA L 0001F400 1F400 SB2 DATA L 0001F600 1F600 SB3 DATA L 0001F800 1F800 SB4 DATA L 0001FA00 1FA00 SB5 DATA L 0001FC00 1FC00 SB6 DATA L 0001FE00 1FE00 SB7 DATA L 00020000 20000 FLASH AREA END ...

Page 615: ...t write at pre write at erase Formula a f to h f a f 10 to h f 10 Examples for 16 MHz a f 25 40 H 0028 b f 7 11 2 H 000C c f 7 11 2 H 000C d f 947 1515 2 H 05EC e f 7 11 2 H 000C g f 9 14 4 H 000F h f 4 6 4 H 0007 Table 18 15 Watchdog Timer Overflow Interval Settings Variable Clock Frequency f 10 MHz frequency 16 MHz H A57F 2 MHz frequency 10 MHz H A57E 1 MHz frequency 2 MHz H A57D Note The watchd...

Page 616: ... program 18 7 8 Protect Modes Flash memory can be protected from programming and erasing by software or hardware methods These two protection modes are described below Software Protection Prevents transitions to program mode and erase mode even if the P or E bit is set in the flash memory control register FLMCR Details are as follows Function Protection Description Program Erase Verify 1 Block Ind...

Page 617: ...rasing of flash memory FLER 1 the FLMCR EBR1 and EBR2 settings are preserved but programming or erasing is aborted immediately This type of protection can be cleared only by a reset or hardware standby Notes 1 Program verify erase verify and prewrite verify modes 2 All blocks are erase disabled It is not possible to specify individual blocks 3 For details see section 18 10 Flash Memory Programming...

Page 618: ...otection from damage to flash memory To prevent abnormal operations when programming voltage VPP is applied follow the programming and erasing algorithms correctly and keep microcontroller operations under constant internal and external supervision using the watchdog timer for example If a transition to error protect mode occurs the flash memory may contain incorrect data due to errors in P 1 or E...

Page 619: ... result might be a program runaway If NMI input occurred during boot program execution the normal boot mode sequence could not be executed NMI input is also disabled in the error protect state while the P or E bit remains set in the flash memory control register FLMCR NMI requests should be disabled externally whenever VPP is applied Notes 1 The disabled state lasts until the branch to the boot pr...

Page 620: ...ea and the original RAM area H FFF000 to H FFF1FF Table 18 16 indicates how to reassign RAM RAM Control Register RAMCR Note Bit 7 and bits 3 to 0 are initialized by a reset and in hardware standby mode They are not initialized in software standby mode Table 18 16 RAM Area Reassignment Bit 3 Bit 2 Bit 1 Bit 0 RAM Area RAMS RAM2 RAM1 RAM0 H FFF000 to H FFF1FF 0 0 1 0 1 0 1 H 01F000 to H 01F1FF 1 0 0...

Page 621: ...of the update data clear the RAM overlap by clearing the RAMS bit 5 Program the data written in RAM addresses H FFF000 to H FFF1FF into the flash memory area Notes 1 When part of RAM H FFF000 to H FFF1FF is overlapped onto a small block area in flash memory the overlapped flash memory area cannot be accessed Access is enabled when the overlap is cleared 2 When the RAMS bit is set to 1 all flash me...

Page 622: ...ut also in PROM mode using a general purpose PROM programmer Table 18 17 indicates how to select PROM mode Be sure to use the indicated socket adapter in PROM mode Table 18 17 Selecting PROM Mode Pins Setting Mode pins MD2 MD1 MD0 Low P80 P81 and P92 STBY and HWR High P50 P51 and P82 RES Power on reset circuit XTAL and EXTAL Oscillator circuit 613 www DataSheet4U com ...

Page 623: ...Package Socket Adapter HD64F3048F 100 pin plastic QFP FP 100B HS3048ESHF1H HD64F3048VF HD64F3048TF 100 pin plastic TQFP TFP 100B HS3048ESNF1H HD64F3048VTF Figure 18 21 Memory Map in PROM Mode Note The FP 100B and TFP 100B pin pitch is only 0 5 mm Use an appropriate tool when inserting the device in the IC socket and removing it For example the tool listed in table 18 19 can be used Table 18 19 Man...

Page 624: ...No RESO NMI P63 P60 P83 P30 P31 P32 P33 P34 P35 P36 P37 P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 P20 P21 P22 P23 P24 P25 P26 P27 P50 P51 P82 STBY HWR MD0 MD1 MD2 P80 P81 AVCC VREF VCC AVSS VSS RES EXTAL XTAL NC OPEN Power on reset circuit Oscillator circuit Legend VPP I O7 to I O0 A16 to A 0 OE CE WE Programming power supply Data input output Address input Output enable Chip enable Write enable Not...

Page 625: ...e automatically Table 18 20 Operating Mode Selection in PROM Mode Pins Mode VPP VCC CE OE WE I O7 to I O0 A16 to A0 Read Read VCC VCC L L H Data output Address input Output VCC VCC L H H High impedance disable Standby VCC VCC H X X High impedance Read VPP VCC L L H Data output Output VPP VCC L H H High impedance disable Standby VPP VCC H X X High impedance Write VPP VCC L H L Data input Legend L L...

Page 626: ... H 20 Erase verify 2 Write EA H A0 Read X EVD Auto erase setup 2 Write X H 30 Write X H 30 auto erase Program setup 2 Write X H 40 Write PA PD program Program verify 2 Write X H C0 Read X PVD Reset 2 Write X H FF Write X H FF PA Program address EA Erase verify address RA Read address PD Program data PVD Program verify output data EVD Erase verify output data 617 www DataSheet4U com ...

Page 627: ...ut sacrificing the reliability of programmed data Figure 18 23 shows the basic high speed high reliability programming flowchart Tables 18 22 and 18 23 list the electrical characteristics during programming Figure 18 23 High Speed High Reliability Programming Start Set VPP 12 0 V 0 6 V Address 0 n 0 Program command Program setup command n 1 n Wait 25 µs Program verify command Wait 6 µs Address 1 a...

Page 628: ...ic high speed high reliability erasing flowchart Tables 18 22 and 18 23 list the electrical characteristics during programming Figure 18 24 High Speed High Reliability Erasing Start Program 0 to all bits Address 0 n 0 Wait 10 ms Erase setup erase command n 1 n Erase verify command Wait 6 µs Address 1 address Verification Last address End Fail n 3000 No good No Yes OK Yes No Note Follow the high sp...

Page 629: ...200 µA voltage Output low I O7 to I O0 VOL 0 45 V IOL 1 6 mA voltage Input leakage I O7 to I O0 ILI 2 µA VIN 0 to VCC V current A16 to A0 OE CE WE VCC current Read ICC 40 80 mA Program ICC 40 80 mA Erase ICC 40 80 mA VPP current Read IPP 200 µA VPP 5 0 V 10 20 mA VPP 12 6 V Program IPP 20 40 mA Erase IPP 20 40 mA Note For details on absolute maximum ratings see section 21 1 Using an LSI in excess ...

Page 630: ...H 20 ns high time OE setup time before tOEWS 0 ns command write OE setup time before verify tOERS 6 µs Verify access time tVA 500 ns OE setup time before status tOEPS 120 ns polling Status polling access time tSPA 120 ns Program wait time tPPW 25 ns Erase wait time tET 9 11 ms Output disable time tDF 0 40 ns Total auto erase time tAET 0 5 30 s Note CE OE and WE should be high during transitions of...

Page 631: ...EPS tAET tWEH tDS tDH tDS tDH tSPA tDF 7 0 6 tVPH tVPS tCEH tCES tOEWS tWEP tCEH tCES tCWC tWEP tDS tDH tDS tDH tAS tAH tPPW tCES tWEH tCEH tWEP tOERS tDH tDS tVA tDF Command in Command in Data in Command in Command in Valid data out Valid data out Data in Program setup Program Program verify Valid address Address 5 0 V 12 V 5 0 V VCC VPP CE OE WE I O I O to I O 7 0 6 Note Program verify data outp...

Page 632: ...ify Valid address Command in Command in Command in Valid data out tVPS tVPH tAS tAH tOEWS tCWC tCES tWEP tCEH tDH tDS tWEH tDS tDH tDS tDH tVA tDF tCES tWEP tCEH tCES tET tWEP tCEH tOERS Note Erase verify data output values may be intermediate between 1 and 0 if erasing is insufficient 623 www DataSheet4U com ...

Page 633: ...e of VCC when the microcontroller is in a stable condition Shut off VPP before VCC again while the microcontroller is in a stable condition If VPP is turned on or off while VCC is not within its rated voltage range VCC 2 7 to 5 5 V since microcontroller operation is unstable and flash memory protection is not functioning the flash memory may be programmed or erased by mistake This can occur even i...

Page 634: ...ly when the P E and VPPE bits in FLMCR are cleared Be sure that these bits are not set by mistaken access to FLMCR Figure 18 28 Power On and Power Off Timing Boot Mode tosc1 12 0 6 V min 0 µs tMDS min 0µs 12 0 6 V 0 to Vcc V 0 to Vcc V 2 7 to 5 5 V VppE set VppE cleared min 10 ø min 0 µs 0 to Vcc V 0 to Vcc V tFRS tVPS ø VCC VPP MD2 RES VPPE bit Programming erasing possible Period during which fla...

Page 635: ...MDS 0 to Vcc V 2 2 Programming erasing possible Period during which flash memory access is prohibited Period during which flash memory can be rewritten Execution of program in flash memory prohibited and data reads other than verify operations prohibited tVPS 5 to 10 µs 1 The level of the mode pins MD2 to MD0 must be fixed from power on to power off by pulling the pins up or down 2 www DataSheet4U...

Page 636: ...ory access is prohibited Period during which flash memory can be rewritten Execution of program in flash memory prohibited and data reads other than verify operations prohibited 1 2 Notes When entering boot mode or making a transition from boot mode to another mode mode switching must be carried out by means of RES input The pin output states change during this switchover interval the interval dur...

Page 637: ...is applied during watchdog timer reset output while the RESO pin is low overcurrent flow will permanently destroy the reset output circuit The watchdog timers reset output enable bit RSTOE should not be set to 1 If a pull up resistor is externally attached to the VPP RESO pin a diode is necessary to prevent reverse current from flowing to VCC when VPP is applied figure 18 31 7 If the watchdog time...

Page 638: ...n to prevent the maximum rating from being exceeded c The maximum rated voltage is based on the potential of the VSS pin If the potential of this pin oscillates due to current fluctuations etc the voltage of the VPP and mode MD2 pins may reciprocally exceed the maximum rated voltage Careful attention must therefore be paid to stabilizing the reference potential Note When the user system s 12 V pow...

Page 639: ...n 12 V is applied Note In normal operation if the mode MD2 pin to which 12 V is applied is to be set to 0 it should be pulled down with a resistor A sample circuit is shown figure 18 32 Figure 18 32 Example of Mounting Board Design Connection to Adapter Board When VPP Pin and Mode Pin Settings Are 1 630 VPP H8 3048F MD2 0 01 µF 1 0 µF VCC VCC 0 01 µF 1 0 µF 12 V 12 V mode pin Adapter board User sy...

Page 640: ...p voltage may not yet have reached the programming voltage range of 12 0 V 0 6 V Do not actually program or erase the flash memory until Vpp has reached the programming voltage range The programming voltage range for programming and erasing flash memory is 12 0 V 0 6 V 11 4 V to 12 6 V Programming and erasing cannot be performed correctly outside this range When not programming or erasing the flas...

Page 641: ...t sizes of ROM This applies to ordering through an EPROM and through electrical data transfer Figure 18 33 Masked ROM Addresses and Data 632 HD6433048 ROM 128 kbytes Address H 00000 1FFFF H 00000 Note Program H FF to all addresses in these areas H 1FFFF HD6433047 ROM 96 kbytes Address H 00000 17FFF H 00000 Not used Not used Not used H 17FFF H 18000 H 1FFFF HD6433045 ROM 64 kbytes Address H 00000 0...

Page 642: ...division ratio 2 Notes 1 Usage of the ø pin differs depending on the chip operating mode and the PSTOP bit setting in the module standby control register MSTCR For details see section 20 7 System Clock Output Disabling Function 2 The division ratio of the frequency divider can be changed dynamically during operation The clock output at the ø pin also changes when the division ratio is changed The ...

Page 643: ...quency f MHz Value 2 2 f 4 4 f 8 8 f 10 10 f 13 13 f 16 16 f 18 Rd For products 1 k 500 200 0 0 0 0 Ω listed below HD64F3048 1 k 1 k 500 200 100 0 Note A crystal resonator between 2 MHz and 18 MHz between 2 MHz and 16 MHz for the flash memory version can be used If the chip is to be operated at less than 2 MHz the on chip frequency divider should be used A crystal resonator of less than 2 MHz cann...

Page 644: ...ed the following points should be noted Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation See figure 19 4 When the board is designed the crystal resonator and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins Figure 19 4 Example of Incorrect Board Design XTAL EXTAL CL2 CL1 H8 3048 S...

Page 645: ...tance should not exceed 10 pF If the stray capacitance at the XTAL pin exceeds 10 pF in configuration a use configuration b instead and hold the clock high in standby mode Figure 19 5 External Clock Input Examples EXTAL XTAL EXTAL XTAL 74HC04 External clock input Open External clock input a XTAL pin left open b Complementary clock input at XTAL pin 636 www DataSheet4U com ...

Page 646: ...ystem must remain reset with the reset signal low during tDEXT while the clock output is unstable Table 19 3 Clock Timing VCC 2 7 V to 5 5 V VCC 5 0 V 10 Item Symbol Min Max Min Max Unit Test Conditions External clock input tEXL 40 20 ns Figure 19 6 low pulse width External clock input tEXH 40 20 ns high pulse width External clock rise tEXr 10 5 ns time External clock fall tEXf 10 5 ns time Clock ...

Page 647: ... Timing Figure 19 7 External Clock Output Settling Delay Timing 638 EXTAL tEXr tEXf VCC 0 7 0 3 V tEXH tEXL VCC 0 5 VCC STBY EXTAL ø internal or external RES tDEXT Note tDEXT includes 10 tcyc of RES tRESW 2 7 V VIH www DataSheet4U com ...

Page 648: ...to the frequency division ratio The system clock generated by the frequency divider can be output at the ø pin 19 5 1 Register Configuration Table 19 4 summarizes the frequency division register Table 19 4 Frequency Division Register Address Name Abbreviation R W Initial Value H FF5D Division control register DIVCR R W H FC Note The lower 16 bits of the address are shown 19 5 2 Division Control Re...

Page 649: ...eration range specified for the clock cycle time tcyc in the AC electrical characteristics Note that øMIN 1 MHz Avoid settings that give system clock frequencies less than 1 MHz All on chip module operations are based on ø Note that the timing of timer operations serial communication and other time dependent processing differs before and after any change in the division ratio The waiting time for ...

Page 650: ... following three modes Sleep mode Software standby mode Hardware standby mode The module standby function can halt on chip supporting modules independently of the power down state The modules that can be halted are the ITU SCI0 SCI1 DMAC refresh controller and A D converter Table 20 1 indicates the methods of entering and exiting the power down modes and module standby mode and gives the status of...

Page 651: ... and and and impedance impedance RES mode reset reset reset reset reset reset reset Module Corresponding Active Active Halted 2 Halted 2 Halted 2 Halted 2 Halted 2 Halted 2 Active High STBY standby bit set to 1 in and and and and and and impedance 2 RES MSTCR reset held 1 reset reset reset reset Clear MSTCR bit to 0 4 Notes 1 RTCNT and bits 7 and 6 of RTMCSR are initialized Other bits and register...

Page 652: ...er 16 bits of the address 20 2 1 System Control Register SYSCR SYSCR is an 8 bit readable writable register Bit 7 SSBY and bits 6 to 4 STS2 to STS0 control the power down state For information on the other SYSCR bits see section 3 3 System Control Register SYSCR Bit Initial value Read Write 7 SSBY 0 R W 6 STS2 0 R W 5 STS1 0 R W 4 STS0 0 R W 3 UE 1 R W 0 RAME 1 R W 2 NMIEG 0 R W 1 1 Software stand...

Page 653: ...ength of time the CPU and on chip supporting modules wait for the clock to settle when software standby mode is exited by an external interrupt If the clock is generated by a crystal resonator set these bits according to the clock frequency so that the waiting time will be at least 7 ms See table 20 3 If an external clock is used any setting is permitted Bit 6 Bit 5 Bit 4 STS2 STS1 STS0 Descriptio...

Page 654: ...ock Stop PSTOP Enables or disables output of the system clock ø Bit 1 PSTOP Description 0 System clock output is enabled Initial value 1 System clock output is disabled Bit 6 Reserved Read only bit always read as 1 Bit 5 Module Standby 5 MSTOP5 Selects whether to place the ITU in standby Bit 5 MSTOP5 Description 0 ITU operates normally Initial value 1 ITU is in standby state Bit Initial value Read...

Page 655: ...lects whether to place the DMAC in standby Bit 2 MSTOP2 Description 0 DMAC operates normally Initial value 1 DMAC is in standby state Bit 1 Module Standby 1 MSTOP1 Selects whether to place the refresh controller in standby Bit 1 MSTOP1 Description 0 Refresh controller operates normally Initial value 1 Refresh controller is in standby state Bit 0 Module Standby 0 MSTOP0 Selects whether to place the...

Page 656: ... remain halted 20 3 2 Exit from Sleep Mode Sleep mode is exited by an interrupt or by input at the RES or STBY pin Exit by Interrupt An interrupt terminates sleep mode and causes a transition to the interrupt exception handling state Sleep mode is not exited by an interrupt source in an on chip supporting module if the interrupt is disabled in the on chip supporting module Sleep mode is not exited...

Page 657: ...l interrupt at the NMI IRQ0 IRQ1 or IRQ2 pin or by input at the RES or STBY pin Exit by Interrupt When an NMI IRQ0 IRQ1 or IRQ2 interrupt request signal is received the clock oscillator begins operating After the oscillator settling time selected by bits STS2 to STS0 in SYSCR stable clock signals are supplied to the entire chip software standby mode ends and interrupt exception handling begins Sof...

Page 658: ... 1 02 1 4 1 6 2 0 2 7 4 0 8 2 16 4 ms 0 0 1 16384 states 1 8 2 0 2 7 3 3 4 1 5 5 8 2 16 4 32 8 0 1 0 32768 states 3 6 4 1 5 5 6 6 8 2 10 9 16 4 32 8 65 5 0 1 1 65536 states 7 3 8 2 10 9 13 1 16 4 21 8 32 8 65 5 131 1 1 0 0 131072 states 14 6 16 4 21 8 26 2 32 8 43 7 65 5 131 1 262 1 1 0 1 1024 states 0 11 0 13 0 17 0 20 0 26 0 34 0 51 1 0 2 0 1 1 Illegal setting 1 0 0 0 0 8192 states 1 8 2 0 2 7 3...

Page 659: ...o 1 then the SLEEP instruction is executed to enter software standby mode Software standby mode is exited at the next rising edge of the NMI signal Figure 20 1 NMI Timing for Software Standby Mode Example 20 4 5 Note The I O ports retain their existing states in software standby mode If a port is in the high output state its output current is not reduced ø NMI NMIEG SSBY NMI interrupt handler NMIE...

Page 660: ...changed during hardware standby mode 20 5 2 Exit from Hardware Standby Mode Hardware standby mode is exited by inputs at the STBY and RES pins While RES is low when STBY goes high the clock oscillator starts running RES should be held low long enough for the clock oscillator to settle When RES goes high reset exception handling begins followed by a transition to the program execution state 20 5 3 ...

Page 661: ...ipheral Module Interrupt When MSTCR is set to 1 prevent module interrupt in advance When an on chip supporting module is placed in standby by the module standby function its registers are initialized Pin States Pins used by an on chip supporting module lose their module functions when the module is placed in module standby What happens after that depends on the particular pin For details see secti...

Page 662: ...utput of the system clock is enabled Table 20 4 indicates the state of the ø pin in various operating states Figure 20 3 Starting and Stopping of System Clock Output Table 20 4 ø Pin State in Various Operating States Operating State PSTOP 0 PSTOP 1 Hardware standby High impedance High impedance Software standby Always high High impedance Sleep mode System clock output High impedance Normal operati...

Page 663: ...to VCC 0 3 V HD6433048 HD6433047 HD6433045 HD6433044 HD64F3048 0 3 to 13 0 V Input voltage port 7 Vin 0 3 to AVCC 0 3 V Reference voltage VREF 0 3 to AVCC 0 3 V Analog power supply voltage AVCC 0 3 to 7 0 V Analog input voltage VAN 0 3 to AVCC 0 3 V Operating temperature Topr Regular specifications 20 to 75 C Wide range specifications 40 to 85 C Storage temperature Tstg 55 to 125 C Caution Permane...

Page 664: ... RES STBY VIH VCC 0 7 VCC 0 3 V voltage NMI MD2 to MD0 EXTAL VCC 0 7 VCC 0 3 V Port 7 2 0 AVCC 0 3 V Ports 1 2 3 2 0 VCC 0 3 V 4 5 6 9 P83 P84 PB4 to PB7 Input low RES STBY VIL 0 3 0 5 V voltage MD2 to MD0 NMI EXTAL 0 3 0 8 V ports 1 2 3 4 5 6 7 9 P83 P84 PB4 to PB7 All output pins VOH VCC 0 5 V IOH 200 µA except RESO 3 5 V IOH 1 mA Output low All output pins VOL 0 4 V IOL 1 6 mA voltage except RE...

Page 665: ...f 18 MHz Sleep mode 35 50 mA f 16 MHz 40 55 mA f 18 MHz 20 25 mA f 16 MHz 25 27 mA f 18 MHz 0 01 5 0 µA Ta 50 C 20 0 µA 50 C Ta Notes 1 If the A D and D A converters are not used do not leave the AVCC AVSS and VREF pins open Connect AVCC and VREF to VCC and connect AVSS to VSS 2 Current dissipation values are for VIHmin VCC 0 5 V and VILmax 0 5 V with all output pins unloaded and the on chip pull ...

Page 666: ...ng A D AICC 1 2 2 0 mA supply current conversion During A D 1 2 2 0 mA and D A conversion Idle 0 01 5 0 µA DASTE 0 Reference During A D AICC 0 3 0 6 mA VREF 5 0 V current conversion During A D 1 3 3 0 mA and D A conversion Idle 0 01 5 0 µA DASTE 0 RAM standby voltage VRAM 2 0 V Note If the A D and D A converters are not used do not leave the AVCC AVSS and VREF pins open Connect AVCC and VREF to VC...

Page 667: ... MD2 to MD0 0 3 VCC 0 2 V VCC 4 0 V 0 8 V VCC 4 0 V to 5 5 V All output pins VOH VCC 0 5 V IOH 200 µA except RESO VCC 1 0 V IOH 1 mA Output low All output pins VOL 0 4 V IOL 1 6 mA voltage except RESO Ports 1 2 1 0 V VCC 4 V 5 and B IOL 5 mA 4 V VCC 5 5 V IOL 10 mA RESO 0 4 V IOL 1 6 mA Input leakage STBY NMI IIN 1 0 µA VIN 0 5 to current RES VCC 0 5 V MD2 to MD0 Port 7 1 0 µA VIN 0 5 to AVCC 0 5 ...

Page 668: ...f 8 MHz standby mode 5 3 0 V 5 5 V 7 20 mA 13 MHz 3 3 V 5 5 V VCC 3 15 V to 5 5 V Standby 0 01 5 0 µA Ta 50 C mode 3 20 0 µA 50 C Ta Notes 1 If the A D and D A converters are not used do not leave the AVCC AVSS and VREF pins open Connect AVCC and VREF to VCC and connect AVSS to VSS 2 Current dissipation values are for VIHmin VCC 0 5 V and VILmax 0 5 V with all output pins unloaded and the on chip ...

Page 669: ...0 V 1 2 mA AVCC 5 0 V Idle 0 01 5 0 µA DASTE 0 AICC 0 2 0 4 mA VREF 3 0 V 0 3 mA VREF 5 0 V 0 8 2 0 mA VREF 3 0 V 1 3 mA VREF 5 0 V Idle 0 01 5 0 µA DASTE 0 RAM standby voltage VRAM 2 0 V Note If the A D and D A converters are not used do not leave the AVCC AVSS and VREF pins open Connect AVCC and VREF to VCC and connect AVSS to VSS During A D conversion During A D and D A conversion Analog power ...

Page 670: ...IOL 80 mA low current total ports 1 2 5 and B Total of all output pins 120 mA including the above Permissible output All output pins IOH 2 0 mA high current per pin Permissible output Total of all output pins ΣIOH 40 mA high current total Notes 1 To protect chip reliability do not exceed the output current values in table 21 3 2 When driving a darlington pair or LED always insert a current limitin...

Page 671: ...Figure 21 1 Darlington Pair Drive Circuit Example Figure 21 2 LED Drive Circuit Example H8 3048 Series Ports 1 2 5 and B LED 600 Ω H8 3048 Series Port 2 kΩ Darlington pair 663 www DataSheet4U com ...

Page 672: ...S AVSS 0 V ø 1 MHz to 18 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Condition A Condition B Condition C 8 MHz 13 MHz 16 MHz 18 MHz Item Symbol Min Max Min Max Min Max Min Max Unit Clock cycle time tCYC 125 1000 76 9 1000 62 5 1000 55 5 1000 ns Clock pulse low width tCL 40 20 20 17 Clock pulse high width tCH 40 20 20 17 Clock rise time tCR 20 15 10 10 Clock...

Page 673: ... C 8 MHz 13 MHz 16 MHz 18 MHz Item Symbol Min Max Min Max Min Max Min Max Unit Write data delay time tWDD 75 75 60 55 ns Write data setup time 1 tWDS1 60 20 15 10 Write data setup time 2 tWDS2 5 10 5 10 Write data hold time tWDH 25 15 20 20 Read data access tACC1 120 60 60 50 time 1 Read data access tACC2 240 140 120 105 time 2 Read data access tACC3 70 30 30 20 time 3 Read data access tACC4 180 1...

Page 674: ...C 53 ns tWSW2 1 5 tCYC 26 ns tACC3 1 0 tCYC 47 ns tPCH 1 0 tCYC 32 ns tACC4 2 0 tCYC 54 ns At 16 MHz the times below depend as indicated on the clock cycle time tACC1 1 5 tCYC 34 ns tWSW1 1 0 tCYC 28 ns tACC2 2 5 tCYC 37 ns tWSW2 1 5 tCYC 29 ns tACC3 1 0 tCYC 33 ns tPCH 1 0 tCYC 28 ns tACC4 2 0 tCYC 30 ns At 18 MHz the times below depend as indicated on the clock cycle time tACC1 1 5 tCYC 34 ns tW...

Page 675: ...cations Ta 40 C to 85 C wide range specifications Condition A Condition B Condition C 8 MHz 13 MHz 16 MHz 18 MHz Item Symbol Min Max Min Max Min Max Min Max Unit RAS delay time 1 tRAD1 60 50 30 30 ns RAS delay time 2 tRAD2 60 50 30 30 RAS delay time 3 tRAD3 60 50 30 30 Row address hold time tRAH 25 20 15 15 RAS precharge time tRP 85 55 45 40 CAS to RAS precharge tCRP 85 55 45 40 time CAS pulse wid...

Page 676: ... 19 ns tCAC 1 0 tCYC 47 ns tRAC 2 0 tCYC 74 ns tCSR 0 5 tCYC 29 ns tRP tCRP 1 0 tCYC 22 ns At 16 MHz the times below depend as indicated on the clock cycle time tRAH 0 5 tCYC 17 ns tCAC 1 0 tCYC 33 ns tRAC 2 0 tCYC 40 ns tCSR 0 5 tCYC 17 ns tRP tCRP 1 0 tCYC 18 ns At 18 MHz the times below depend as indicated on the clock cycle time tRAH 0 5 tCYC 13 ns tCAC 1 0 tCYC 31 ns tRAC 2 0 tCYC 41 ns tCSR ...

Page 677: ... Condition B Condition C 8 MHz 13 MHz 16 MHz 18 MHz Item Symbol Min Max Min Max Min Max Min Max Unit RES setup time tRESS 200 200 200 200 ns Figure 21 18 RES pulse width tRESW 10 10 10 10 tCYC Mode programming tMDS 200 200 200 200 ns setup time RESO output delay tRESD 100 100 100 100 ns Figure 21 19 time RESO output pulse tRESOW 132 132 132 132 tCYC width NMI setup time tNMIS 200 200 150 150 ns Fi...

Page 678: ...8 MHz 13 MHz 16 MHz 18 MHz Item Symbol Min Max Min Max Min Max Min Max Unit DMAC DREQ setup tDRQS 40 40 30 30 ns Figure 21 30 time DREQ hold tDRQH 10 10 10 10 time TEND delay tTED1 100 100 50 50 Figure 21 28 time 1 Figure 21 29 TEND delay tTED2 100 100 50 50 time 2 ITU Timer output tTOCD 100 100 100 100 ns Figure 21 24 delay time Timer input tTICS 50 50 50 50 setup time Timer clock tTCKS 50 50 50 ...

Page 679: ... wide range specifications Condition A Condition B Condition C 8 MHz 13 MHz 16 MHz 18 MHz Item Symbol Min Max Min Max Min Max Min Max Unit SCI Transmit data tTXD 100 100 100 100 ns Figure 21 27 delay time Receive data tRXS 100 100 100 100 setup time synchronous Clock input tRXH 100 100 100 100 Clock output 0 0 0 0 Output data tPWD 100 100 100 100 ns Figure 21 23 delay time Input data tPRS 50 50 50...

Page 680: ... 0 V ø 1 MHz to 18 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Condition A Condition B Condition C 8 MHz 13 MHz 16 MHz 18 MHz Item Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit Resolution 10 10 10 10 10 10 10 10 10 10 10 10 bits Conversion time 16 8 10 4 8 4 7 5 µs Analog input 20 20 20 20 pF capacitance 10 1 10 1 10 3 10 3 kΩ 5 2 5 2 5 4 5 4 Nonline...

Page 681: ...a 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Condition C VCC 5 0 V 10 AVCC 5 0 V 10 VREF 4 5 V to AVCC VSS AVSS 0 V ø 1 MHz to 18 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Condition A Condition B Condition C 8 MHz 13 MHz 16 MHz 18 MHz Item Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit Resolution 8 8 8 8 8 8 8 8 8 ...

Page 682: ...2 to MD0 EXTAL VCC 0 7 VCC 0 3 V Port 7 2 0 AVCC 0 3 V Ports 1 2 3 2 0 VCC 0 3 V 4 5 6 9 P83 P84 PB4 to PB7 Input low RES STBY VIL 0 3 0 5 V voltage MD2 to MD0 NMI EXTAL 0 3 0 8 V ports 1 2 3 4 5 6 7 9 P83 P84 PB4 to PB7 All output pins VOH VCC 0 5 V IOH 200 µA 3 5 V IOH 1 mA Output low All output pins VOL 0 4 V IOL 1 6 mA voltage except RESO Ports 1 2 1 0 V IOL 10 mA 5 and B RESO 0 4 V IOL 2 6 mA...

Page 683: ...eep mode 35 50 mA f 16 MHz 20 25 mA f 16 MHz 0 01 5 0 µA Ta 50 C 20 0 µA 50 C Ta Notes 1 If the A D and D A converters are not used do not leave the AVCC AVSS and VREF pins open Connect AVCC and VREF to VCC and connect AVSS to VSS 2 Current dissipation values are for VIHmin VCC 0 5 V and VILmax 0 5 V with all output pins unloaded and the on chip pull up transistors in the off state 3 The values ar...

Page 684: ...g A D 1 2 2 0 mA and D A conversion Idle 0 01 5 0 µA DASTE 0 Reference During A D AICC 0 3 0 6 mA VREF 5 0 V current conversion During A D 1 3 3 0 mA and D A conversion Idle 0 01 5 0 µA DASTE 0 VPP pin Read output IPP 10 µA VPP 5 0 V current 10 20 mA VPP 12 6 V Program 20 40 mA execution Erase 20 40 mA RAM standby voltage VRAM 2 0 V Note If the A D and D A converters are not used do not leave the ...

Page 685: ... P83 P84 PB4 to PB7 Input low RES STBY VIL 0 3 VCC 0 1 V voltage MD2 to MD0 0 3 VCC 0 2 V VCC 4 0 V 0 8 V VCC 4 0 V to 5 5 V All output pins VOH VCC 0 5 V IOH 200 µA VCC 1 0 V IOH 1 mA Output low All output pins VOL 0 4 V IOL 1 6 mA voltage except RESO Ports 1 2 1 0 V VCC 4 V 5 and B IOL 5 mA 4 V VCC 5 5 V IOL 10 mA RESO 0 4 V IOL 1 6 mA Note If the A D and D A converters are not used do not leave...

Page 686: ...0 5 to current RES MD1 VCC 0 5 V MD0 MD2 10 0 µA Vin 0 5 to VCC 0 5 V MD2 50 0 µA Vin VCC 0 5 to 12 6 V Port 7 1 0 µA Vin 0 5 to AVCC 0 5 V Ports 1 2 ITS1 1 0 µA Vin 0 5 to 3 4 5 6 VCC 0 5 V 8 to B RESO 10 0 µA Input pull up Ports 2 IP 10 300 µA VCC 2 7 V to current 4 and 5 5 5 V Vin 0 V NMI Cin 50 pF All input pins 15 except NMI Note If the A D and D A converters are not used do not leave the AVC...

Page 687: ... open Connect AVCC and VREF to VCC and connect AVSS to VSS 2 Current dissipation values are for VIHmin VCC 0 5 V and VILmax 0 5 V with all output pins unloaded and the on chip pull up transistors in the off state 3 The values are for VRAM VCC 2 7 V VIHmin VCC 0 9 and VILmax 0 3 V 4 ICC depends on VCC and f as follows ICCmax 3 0 mA 0 75 mA MHz V VCC f normal mode ICCmax 3 0 mA 0 55 mA MHz V VCC f s...

Page 688: ...CC 0 2 0 4 mA VREF 3 0 V 0 3 mA VREF 5 0 V 0 8 2 0 mA VREF 3 0 V 1 3 mA VREF 5 0 V Idle 0 01 5 0 µA DASTE 0 VPP pin Read output IPP 10 µA VPP 5 0 V current 10 20 mA Program 20 40 mA VPP 12 6 V execution Erase 20 40 mA RAM standby voltage VRAM 2 0 V Note If the A D and D A converters are not used do not leave the AVCC AVSS and VREF pins open Connect AVCC and VREF to VCC and connect AVSS to VSS 680 ...

Page 689: ...IOL 80 mA low current total ports 1 2 5 and B Total of all output pins 120 mA including the above Permissible output All output pins IOH 2 0 mA high current per pin Permissible output Total of all output pins ΣIOH 40 mA high current total Notes 1 To protect chip reliability do not exceed the output current values in table 21 11 2 When driving a darlington pair or LED always insert a current limiti...

Page 690: ...Figure 21 4 Darlington Pair Drive Circuit Example Figure 21 5 LED Drive Circuit Example 682 H8 3048 Series Ports 1 2 5 and B LED 600 Ω H8 3048 Series Port 2 kΩ Darlington pair www DataSheet4U com ...

Page 691: ...MHz to 16 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Condition A Condition C 8 MHz 16 MHz Test Item Symbol Min Max Min Max Unit Conditions Clock cycle time tCYC 125 1000 62 5 1000 ns Figure 21 7 Clock pulse low width tCL 40 20 Figure 21 8 Clock pulse high width tCH 40 20 Clock rise time tCR 20 10 Clock fall time tCF 20 10 Address delay time tAD 60 30 Addre...

Page 692: ...ime 1 tACC1 120 60 Read data access time 2 tACC2 240 120 Read data access time 3 tACC3 70 30 Read data access time 4 tACC4 180 95 Precharge time tPCH 85 45 Wait setup time tWTS 40 25 ns Figure 21 9 Wait hold time tWTH 10 5 Bus request setup time tBRQS 40 40 ns Figure 21 21 Bus acknowledge delay time 1 tBACD1 60 30 Bus acknowledge delay time 2 tBACD2 60 30 Bus floating time tBZD 70 40 Note At 8 MHz...

Page 693: ... tRAD2 60 30 to RAS delay time 3 tRAD3 60 30 Figure 21 16 Row address hold time tRAH 25 15 RAS precharge time tRP 85 45 CAS to RAS precharge time tCRP 85 45 CAS pulse width tCAS 100 40 RAS access time tRAC 160 85 Address access time tAA 105 55 CAS access time tCAC 50 30 Write data setup time 3 tWDS3 50 15 CAS setup time tCSR 20 15 Read strobe delay time tRSD 60 30 Note At 8 MHz the times below dep...

Page 694: ...Symbol Min Max Min Max Unit Conditions RES setup time tRESS 200 200 ns Figure 21 18 RES pulse width tRESW 10 10 tCYC Mode programming tMDS 200 200 ns setup time RESO output delay tRESD 100 100 ns Figure 21 19 time RESO output pulse width tRESOW 132 132 tCYC NMI setup time tNMIS 200 150 ns Figure 21 20 NMI IRQ5 to IRQ0 NMI hold time tNMIH 10 10 NMI IRQ5 to IRQ0 Interrupt pulse width tNMIW 200 200 N...

Page 695: ...in Max Min Max Unit Conditions DMAC DREQ setup time tDRQS 40 30 ns Figure 21 30 DREQ hold time tDRQH 10 10 TEND delay time 1 tTED1 100 50 Figure 21 28 TEND delay time 2 tTED2 100 50 Figure 21 29 ITU Timer output delay time tTOCD 100 100 ns Figure 21 24 Timer input setup time tTICS 50 50 Timer clock input setup time tTCKS 50 50 Figure 21 25 Timer clock Single edge tTCKWH 1 5 1 5 tCYC pulse width Bo...

Page 696: ...C 8 MHz 16 MHz Test Item Symbol Min Max Min Max Unit Conditions SCI Transmit data tTXD 100 100 ns Figure 21 27 delay time Receive data tRXS 100 100 setup time synchronous Receive data Clock input tRXH 100 100 hold time Clock output tRXH 0 0 synchronous Ports Output data tPWD 100 100 ns Figure 21 23 and delay time TPC Input data tPRS 50 50 setup time Input data tPRH 50 50 hold time Figure 21 6 Outp...

Page 697: ...z Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Condition A Condition C 8 MHz 16 MHz Item Min Typ Max Min Typ Max Unit Resolution 10 10 10 10 10 10 bits Conversion time 16 8 8 4 µs Analog input capacitance 20 20 pF Permissible signal source 10 1 10 3 kΩ impedance 5 2 5 4 Nonlinearity error 6 0 3 0 LSB Offset error 4 0 2 0 LSB Full scale error 4 0 2 0 LSB Quantiza...

Page 698: ... to 85 C wide range specifications Condition C VCC 5 0 V 10 AVCC 5 0 V 10 VREF 4 5 V to AVCC VSS AVSS 0 V ø 1 MHz to 16 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Condition A Condition C 8 MHz 16 MHz Test Item Min Typ Max Min Typ Max Unit Conditions Resolution 8 8 8 8 8 8 Bits Conversion time 10 10 µs 20 pF capacitive load Absolute accuracy 2 0 3 0 1 0 1 5...

Page 699: ...in Typ Max Unit Test Conditions Programming time 1 tP 50 1000 µs Erase time 1 tE 1 30 s Erase program cycle NWEC 100 time Verify setup time 1 1 tVS1 4 µs Verify setup time 2 1 tVS2 2 µs Flash memory read tFRS 50 µs VCC 4 5 V setup time 2 100 µs VCC 4 5 V Notes 1 To specify each time follow the appropriate algorithm 2 Before reading the flash memory wait at least for the read setup time after clear...

Page 700: ...re 21 7 shows the timing of the external two state access cycle Basic bus cycle three state access Figure 21 8 shows the timing of the external three state access cycle Basic bus cycle three state access with one wait state Figure 21 9 shows the timing of the external three state access cycle with one wait state inserted 692 www DataSheet4U com ...

Page 701: ...tCYC tCH tCL tAD tCF tCR tAS1 tAS1 tASD tACC3 tASD tACC3 tACC1 tASD tAS1 tWDD tWDS1 tWSW1 tSD tAH tPCH tSD tAH tPCH tRDH tRDS tPCH tSD tAH tWDH ø A23 to A0 CS to CS AS RD read D15 to D0 read HWR LWR write D15 to D0 write 3 0 tcyc 693 www DataSheet4U com ...

Page 702: ...Figure 21 8 Basic Bus Cycle Three State Access T1 T2 T3 tACC4 tACC4 tACC2 tWSW2 tWSD tAS2 tWDS2 ø A23 to A0 AS RD read D15 to D0 read HWR LWR write D15 to D0 write tRDS 694 www DataSheet4U com ...

Page 703: ...Figure 21 9 Basic Bus Cycle Three State Access with One Wait State T1 T2 TW T3 tWTS tWTS tWTH ø A23 to A0 AS RD read D15 to D0 read HWR LWR write D15 to D0 write WAIT tWTH 695 www DataSheet4U com ...

Page 704: ...Figures 21 16 and 21 17 show the pseudo static RAM bus timing in each operating mode Figure 21 10 DRAM Bus Timing Read Write Three State Access 2WE Mode ø A9 to A1 AS CS RAS RD CAS HWR UW LWR LW read HWR UW LWR LW write RFSH D15 to D0 read D15 to D0 write T1 T2 T3 tAD tAD tRAH tRAD1 tAS1 tASD tAS1 tRAC tASD tAA tCAC tRAD3 tRP tSD tCRP tSD tWDH tRDS tRDH tWDS3 tCAS 3 696 www DataSheet4U com ...

Page 705: ...ree State Access 2WE Mode Figure 21 12 DRAM Bus Timing Self Refresh Mode 2WE Mode ø A9 to A1 AS CS3 RAS RD CAS HWR UW LWR LW RFSH T1 T2 T3 tASD tCSR tASD tRAD2 tRAD2 tCSR tRAD3 tSD tRAD3 tSD ø CS RAS RD CAS RFSH tCSR tCSR 3 697 www DataSheet4U com ...

Page 706: ... Access 2CAS Mode T1 T2 T3 tAD tAD tRAH tRAD1 tAS1 tASD tAS1 tAA tRAC tASD tCAC tWDS3 tRDS tWDH tRDH tSD tSD tRAD3 tCRP tRP tCAS RFSH ø A9 to A1 AS CS RAS HWR UCAS LWR LCAS RD WE read RD WE write D15 to D0 read write D15 to D0 3 698 www DataSheet4U com ...

Page 707: ... Access 2CAS Mode Figure 21 15 DRAM Bus Timing Self Refresh Mode 2CAS Mode ø A9 to A1 AS CS RAS RD WE HWR UCAS LWR LCAS RFSH T1 T2 T3 tASD tCSR tASD tRAD2 tRAD2 tCSR tRAD3 tSD tRAD3 tSD 3 tCSR tCSR UCAS ø CS RAS HWR LWR RFSH LCAS 3 699 www DataSheet4U com ...

Page 708: ...PSRAM Bus Timing Refresh Cycle Three State Access ø A23 to A0 AS CS3 RD read D15 to D0 read HWR LWR write D15 to D0 write RFSH tAD T2 T3 tRAD1 tAS1 tRSD tWSD tWDS2 tRAD3 tRP tRDH tSD tRDS tSD T1 ø A23 to A0 AS CS3 HWR LWR RD RFSH T2 T3 T1 tRAD2 tRAD3 700 www DataSheet4U com ...

Page 709: ... Figure 21 19 shows the reset output timing Interrupt input timing Figure 21 20 shows the input timing for NMI and IRQ5 to IRQ0 Bus release mode timing Figure 21 21 shows the bus release mode timing Figure 21 18 Reset Input Timing Figure 21 19 Reset Output Timing ø tRESS tRESS tRESW tMDS RES MD2 to MD0 ø RESO tRESD tRESOW tRESD 701 www DataSheet4U com ...

Page 710: ... Release Mode Timing ø NMI IRQ IRQ E L tNMIS tNMIH tNMIS tNMIH tNMIS tNMIW NMI IRQ j IRQ Edge sensitive IRQ Level sensitive IRQ i 0 to 5 E L i i IRQ j 0 to 2 BREQ BACK ø A23 to A0 AS RD HWR LWR tBRQS tBRQS tBACD1 tBZD tBACD2 tBZD 702 www DataSheet4U com ...

Page 711: ...llator settling timing Figure 21 22 Oscillator Settling Timing 21 4 5 TPC and I O Port Timing Figure 21 23 shows the TPC and I O port timing Figure 21 23 TPC and I O Port Input Output Timing ø VCC STBY RES tOSC1 tOSC1 T1 T2 T3 ø Port 1 to B read Port 1 to 6 8 to B write tPRS tPRH tPWD 703 www DataSheet4U com ...

Page 712: ...ut timing Figure 21 25 shows the ITU external clock input timing Figure 21 24 ITU Input Output Timing Figure 21 25 ITU Clock Input Timing ø Output compare 1 Input capture 2 tTOCD tTICS Notes 1 TIOCA0 to TIOCA4 TIOCB0 to TIOCB4 TOCXA4 TOCXB4 2 TIOCA0 to TIOCA4 TIOCB0 to TIOCB4 ø tTCKS tTCKS tTCKWH tTCKWL TCLKA to TCLKD 704 www DataSheet4U com ...

Page 713: ...I input output timing synchronous mode Figure 21 27 shows the SCI input output timing in synchronous mode Figure 21 26 SCK Input Clock Timing Figure 21 27 SCI Input Output Timing in Synchronous Mode SCK0 SCK1 tSCKW tScyc tSCKr tSCKf tScyc tTXD tRXS tRXH SCK0 SCK1 TxD0 TxD1 transmit data RxD0 RxD1 receive data 705 www DataSheet4U com ...

Page 714: ...DMAC TEND output timing for 3 state access Figure 21 29 shows the DMAC TEND output timing for 3 state access DMAC DREQ input timing Figure 21 30 shows DMAC DREQ input timing Figure 21 28 DMAC TEND Output Timing for 2 State Access Figure 21 29 DMAC TEND Output Timing for 3 State Access T1 T2 tTED1 tTED2 ø TEND T1 T2 T3 tTED1 tTED2 ø TEND 706 www DataSheet4U com ...

Page 715: ...Figure 21 30 DMAC DREQ Input Timing tDRQH tDRQS ø DREQ 707 www DataSheet4U com ...

Page 716: ...CR C C carry flag in CCR disp Displacement Transfer from the operand on the left to the operand on the right or transition from the state on the left to the state on the right Addition of the operands on both sides Subtraction of the operand on the right from the operand on the left Multiplication of the operands on both sides Division of the operand on the left by the operand on the right Logical...

Page 717: ...ol Description Changed according to execution result Undetermined no guaranteed value 0 Cleared to 0 1 Set to 1 Not affected by execution of the instruction Varies depending on conditions described in notes 710 www DataSheet4U com ...

Page 718: ...ERd 2 0 4 MOV B Rs d 16 B Rs8 d 16 ERd 4 0 6 ERd MOV B Rs d 24 B Rs8 d 24 ERd 8 0 10 ERd MOV B Rs ERd B ERd32 1 ERd32 2 0 6 Rs8 ERd MOV B Rs aa 8 B Rs8 aa 8 2 0 4 MOV B Rs aa 16 B Rs8 aa 16 4 0 6 MOV B Rs aa 24 B Rs8 aa 24 6 0 8 MOV W xx 16 Rd W xx 16 Rd16 4 0 4 MOV W Rs Rd W Rs16 Rd16 2 0 2 MOV W ERs Rd W ERs Rd16 2 0 4 MOV W d 16 ERs W d 16 ERs Rd16 4 0 6 Rd MOV W d 24 ERs W d 24 ERs Rd16 8 0 10...

Page 719: ... L d 16 ERs ERd32 6 0 10 ERd MOV L d 24 ERs L d 24 ERs ERd32 10 0 14 ERd MOV L ERs ERd L ERs ERd32 4 0 10 ERs32 4 ERs32 MOV L aa 16 ERd L aa 16 ERd32 6 0 10 MOV L aa 24 ERd L aa 24 ERd32 8 0 12 MOV L ERs ERd L ERs32 ERd 4 0 8 MOV L ERs d 16 L ERs32 d 16 ERd 6 0 10 ERd MOV L ERs d 24 L ERs32 d 24 ERd 10 0 14 ERd MOV L ERs ERd L ERd32 4 ERd32 4 0 10 ERs32 ERd MOV L ERs aa 16 L ERs32 aa 16 6 0 10 MOV...

Page 720: ... xx 16 Rd W Rd16 xx 16 Rd16 4 1 4 ADD W Rs Rd W Rd16 Rs16 Rd16 2 1 2 ADD L xx 32 ERd L ERd32 xx 32 6 2 6 ERd32 ADD L ERs ERd L ERd32 ERs32 2 2 2 ERd32 ADDX B xx 8 Rd B Rd8 xx 8 C Rd8 2 3 2 ADDX B Rs Rd B Rd8 Rs8 C Rd8 2 3 2 ADDS L 1 ERd L ERd32 1 ERd32 2 2 ADDS L 2 ERd L ERd32 2 ERd32 2 2 ADDS L 4 ERd L ERd32 4 ERd32 2 2 INC B Rd B Rd8 1 Rd8 2 2 INC W 1 Rd W Rd16 1 Rd16 2 2 INC W 2 Rd W Rd16 2 Rd1...

Page 721: ...ERd32 2 2 SUBS L 4 ERd L ERd32 4 ERd32 2 2 DEC B Rd B Rd8 1 Rd8 2 2 DEC W 1 Rd W Rd16 1 Rd16 2 2 DEC W 2 Rd W Rd16 2 Rd16 2 2 DEC L 1 ERd L ERd32 1 ERd32 2 2 DEC L 2 ERd L ERd32 2 ERd32 2 2 DAS Rd B Rd8 decimal adjust 2 2 Rd8 MULXU B Rs Rd B Rd8 Rs8 Rd16 2 14 unsigned multiplication MULXU W Rs ERd W Rd16 Rs16 ERd32 2 22 unsigned multiplication MULXS B Rs Rd B Rd8 Rs8 Rd16 4 16 signed multiplicatio...

Page 722: ...d8 Rs8 2 2 CMP W xx 16 Rd W Rd16 xx 16 4 1 4 CMP W Rs Rd W Rd16 Rs16 2 1 2 CMP L xx 32 ERd L ERd32 xx 32 6 2 4 CMP L ERs ERd L ERd32 ERs32 2 2 2 NEG B Rd B 0 Rd8 Rd8 2 2 NEG W Rd W 0 Rd16 Rd16 2 2 NEG L ERd L 0 ERd32 ERd32 2 2 EXTU W Rd W 0 bits 15 to 8 2 0 0 2 of Rd16 EXTU L ERd L 0 bits 31 to 16 2 0 0 2 of ERd32 EXTS W Rd W bit 7 of Rd16 2 0 2 bits 15 to 8 of Rd16 EXTS L ERd L bit 15 of ERd32 2 ...

Page 723: ... 16 Rd W Rd16 xx 16 Rd16 4 0 4 OR W Rs Rd W Rd16 Rs16 Rd16 2 0 2 OR L xx 32 ERd L ERd32 xx 32 ERd32 6 0 6 OR L ERs ERd L ERd32 ERs32 ERd32 4 0 4 XOR B xx 8 Rd B Rd8 xx 8 Rd8 2 0 2 XOR B Rs Rd B Rd8 Rs8 Rd8 2 0 2 XOR W xx 16 Rd W Rd16 xx 16 Rd16 4 0 4 XOR W Rs Rd W Rd16 Rs16 Rd16 2 0 2 XOR L xx 32 ERd L ERd32 xx 32 ERd32 6 0 6 XOR L ERs ERd L ERd32 ERs32 ERd32 4 0 4 NOT B Rd B Rd8 Rd8 2 0 2 NOT W R...

Page 724: ...W 2 0 2 SHLR L ERd L 2 0 2 ROTXL B Rd B 2 0 2 ROTXL W Rd W 2 0 2 ROTXL L ERd L 2 0 2 ROTXR B Rd B 2 0 2 ROTXR W Rd W 2 0 2 ROTXR L ERd L 2 0 2 ROTL B Rd B 2 0 2 ROTL W Rd W 2 0 2 ROTL L ERd L 2 0 2 ROTR B Rd B 2 0 2 ROTR W Rd W 2 0 2 ROTR L ERd L 2 0 2 xx Rn ERn d ERn ERn ERn aa d PC aa Addressing Mode and Instruction Length bytes Normal No of States 1 Advanced Operand Size MSB LSB 0 C C MSB LSB M...

Page 725: ... 8 BCLR Rn aa 8 B Rn8 of aa 8 0 4 8 BNOT xx 3 Rd B xx 3 of Rd8 2 2 xx 3 of Rd8 BNOT xx 3 ERd B xx 3 of ERd 4 8 xx 3 of ERd BNOT xx 3 aa 8 B xx 3 of aa 8 4 8 xx 3 of aa 8 BNOT Rn Rd B Rn8 of Rd8 2 2 Rn8 of Rd8 BNOT Rn ERd B Rn8 of ERd 4 8 Rn8 of ERd BNOT Rn aa 8 B Rn8 of aa 8 4 8 Rn8 of aa 8 BTST xx 3 Rd B xx 3 of Rd8 Z 2 2 BTST xx 3 ERd B xx 3 of ERd Z 4 6 BTST xx 3 aa 8 B xx 3 of aa 8 Z 4 6 BTST ...

Page 726: ... 3 aa 8 B C xx 3 of aa 8 C 4 6 BIAND xx 3 Rd B C xx 3 of Rd8 C 2 2 BIAND xx 3 ERd B C xx 3 of ERd24 C 4 6 BIAND xx 3 aa 8 B C xx 3 of aa 8 C 4 6 BOR xx 3 Rd B C xx 3 of Rd8 C 2 2 BOR xx 3 ERd B C xx 3 of ERd24 C 4 6 BOR xx 3 aa 8 B C xx 3 of aa 8 C 4 6 BIOR xx 3 Rd B C xx 3 of Rd8 C 2 2 BIOR xx 3 ERd B C xx 3 of ERd24 C 4 6 BIOR xx 3 aa 8 B C xx 3 of aa 8 C 4 6 BXOR xx 3 Rd B C xx 3 of Rd8 C 2 2 B...

Page 727: ...LO d 8 C 1 2 4 BCS d 16 BLO d 16 4 6 BNE d 8 Z 0 2 4 BNE d 16 4 6 BEQ d 8 Z 1 2 4 BEQ d 16 4 6 BVC d 8 V 0 2 4 BVC d 16 4 6 BVS d 8 V 1 2 4 BVS d 16 4 6 BPL d 8 N 0 2 4 BPL d 16 4 6 BMI d 8 N 1 2 4 BMI d 16 4 6 BGE d 8 N V 0 2 4 BGE d 16 4 6 BLT d 8 N V 1 2 4 BLT d 16 4 6 BGT d 8 2 4 BGT d 16 4 6 xx Rn ERn d ERn ERn ERn aa d PC aa Addressing Mode and Instruction Length bytes Normal No of States 1 ...

Page 728: ...PC SP 2 6 8 PC PC d 8 BSR d 16 PC SP 4 8 10 PC PC d 16 JSR ERn PC SP 2 6 8 PC ERn JSR aa 24 PC SP 4 8 10 PC aa 24 JSR aa 8 PC SP 2 8 12 PC aa 8 RTS PC SP 2 8 10 Z N V 1 xx Rn ERn d ERn ERn ERn aa d PC aa Addressing Mode and Instruction Length bytes Normal No of States 1 Advanced Operand Size If condition is true then PC PC d else next Branch Condition 721 www DataSheet4U com ...

Page 729: ...W ERs CCR 4 8 ERs32 2 ERs32 LDC aa 16 CCR W aa 16 CCR 6 8 LDC aa 24 CCR W aa 24 CCR 8 10 STC CCR Rd B CCR Rd8 2 2 STC CCR ERd W CCR ERd 4 6 STC CCR d 16 W CCR d 16 ERd 6 8 ERd STC CCR d 24 W CCR d 24 ERd 10 12 ERd STC CCR ERd W ERd32 2 ERd32 4 8 CCR ERd STC CCR aa 16 W CCR aa 16 6 8 STC CCR aa 24 W CCR aa 24 8 10 ANDC xx 8 CCR B CCR xx 8 CCR 2 2 ORC xx 8 CCR B CCR xx 8 CCR 2 2 XORC xx 8 CCR B CCR ...

Page 730: ...hen a carry or borrow occurs at bit 11 otherwise cleared to 0 2 Set to 1 when a carry or borrow occurs at bit 27 otherwise cleared to 0 3 Retains its previous value when the result is zero otherwise cleared to 0 4 Set to 1 when the adjustment produces a carry otherwise retains its previous value 5 The number of states required for execution of an instruction that transfers data in synchronization ...

Page 731: ...L JMP BMI EEPMOV ADDX SUBX BGT JSR BLE MOV ADD ADDX CMP SUBX OR XOR AND MOV Table A 2 Operation Code Map 1 Instruction when most significant bit of BH is 0 Instruction when most significant bit of BH is 1 Instruction code Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 BVS BLT BGE BSR Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table ...

Page 732: ...ation Code Map 2 Instruction code BVS SLEEP BVC BGE Table A 2 3 Table A 2 3 Table A 2 3 ADD MOV SUB CMP BNE AND AND INC EXTU DEC BEQ INC EXTU DEC BCS XOR XOR SHLL SHLR ROTXL ROTXR NOT BLS SUB SUB BRN ADD ADD INC EXTS DEC BLT INC EXTS DEC BLE SHAL SHAR ROTL ROTR NEG BMI 1st byte 2nd byte AH BH AL BL SUB ADDS SHLL SHLR ROTXL ROTXR NOT SHAL SHAR ROTL ROTR NEG 725 www DataSheet4U com ...

Page 733: ... BIXOR BAND BIAND AND BLD BILD BST BIST Table A 2 Operation Code Map 3 Instruction when most significant bit of DH is 0 Instruction when most significant bit of DH is 1 Instruction code 1 1 1 1 2 2 2 2 BOR BIOR BXOR BIXOR BAND BIAND BLD BILD BST BIST Notes 1 2 r is the register designation field aa is the absolute address field 1st byte 2nd byte AH BH AL BL 3rd byte CH DH CL DL 4th byte LDC STC LD...

Page 734: ...of an instruction can be calculated from these two tables as follows Number of states I SI J SJ K SK L SL M SM N SN Examples of Calculation of Number of States Required for Execution Examples Advanced mode stack located in external address space on chip supporting modules accessed with 8 bit bus width external devices accessed in three states with one wait state and 16 bit bus width BSET 0 FFFFC7 ...

Page 735: ...3 State Cycle Memory Bus Bus Access Access Access Access Instruction fetch SI 2 6 3 4 6 2m 2 3 m Branch address read SJ Stack operation SK Byte data access SL 3 2 3 m Word data access SM 6 4 6 2m Internal operation SN 1 Legend m Number of wait states inserted into external device access On Chip Sup porting Module 728 www DataSheet4U com ...

Page 736: ...ADD L ERs ERd 1 ADDS ADDS 1 2 4 ERd 1 ADDX ADDX xx 8 Rd 1 ADDX Rs Rd 1 AND AND B xx 8 Rd 1 AND B Rs Rd 1 AND W xx 16 Rd 2 AND W Rs Rd 1 AND L xx 32 ERd 3 AND L ERs ERd 2 ANDC ANDC xx 8 CCR 1 BAND BAND xx 3 Rd 1 BAND xx 3 ERd 2 1 BAND xx 3 aa 8 2 1 Bcc BRA d 8 BT d 8 2 BRN d 8 BF d 8 2 BHI d 8 2 BLS d 8 2 BCC d 8 BHS d 8 2 BCS d 8 BLO d 8 2 BNE d 8 2 BEQ d 8 2 BVC d 8 2 BVS d 8 2 BPL d 8 2 BMI d 8 ...

Page 737: ...2 BPL d 16 2 2 BMI d 16 2 2 BGE d 16 2 2 BLT d 16 2 2 BGT d 16 2 2 BLE d 16 2 2 BCLR BCLR xx 3 Rd 1 BCLR xx 3 ERd 2 2 BCLR xx 3 aa 8 2 2 BCLR Rn Rd 1 BCLR Rn ERd 2 2 BCLR Rn aa 8 2 2 BIAND BIAND xx 3 Rd 1 BIAND xx 3 ERd 2 1 BIAND xx 3 aa 8 2 1 BILD BILD xx 3 Rd 1 BILD xx 3 ERd 2 1 BILD xx 3 aa 8 2 1 BIOR BIOR xx 8 Rd 1 BIOR xx 8 ERd 2 1 BIOR xx 8 aa 8 2 1 BIST BIST xx 3 Rd 1 BIST xx 3 ERd 2 2 BIST...

Page 738: ...1 BSET xx 3 ERd 2 2 BSET xx 3 aa 8 2 2 BSET Rn Rd 1 BSET Rn ERd 2 2 BSET Rn aa 8 2 2 BSR BSR d 8 Normal 2 1 Advanced 2 2 BSR d 16 Normal 2 1 2 Advanced 2 2 2 BST BST xx 3 Rd 1 BST xx 3 ERd 2 2 BST xx 3 aa 8 2 2 BTST BTST xx 3 Rd 1 BTST xx 3 ERd 2 1 BTST xx 3 aa 8 2 1 BTST Rn Rd 1 BTST Rn ERd 2 1 BTST Rn aa 8 2 1 BXOR BXOR xx 3 Rd 1 BXOR xx 3 ERd 2 1 BXOR xx 3 aa 8 2 1 CMP CMP B xx 8 Rd 1 CMP B Rs ...

Page 739: ...EXTS L ERd 1 EXTU EXTU W Rd 1 EXTU L ERd 1 INC INC B Rd 1 INC W 1 2 Rd 1 INC L 1 2 ERd 1 JMP JMP ERn 2 JMP aa 24 2 2 JMP aa 8 Normal 1 2 1 2 Advanced 2 2 2 JSR JSR ERn Normal 1 2 1 Advanced 2 2 JSR aa 24 Normal 1 2 1 2 Advanced 2 2 2 JSR aa 8 Normal 1 2 1 1 Advanced 2 2 2 LDC LDC xx 8 CCR 1 LDC Rs CCR 1 LDC ERs CCR 2 1 LDC d 16 ERs CCR 3 1 LDC d 24 ERs CCR 5 1 LDC ERs CCR 2 1 2 LDC aa 16 CCR 3 1 L...

Page 740: ...1 2 MOV B Rs aa 8 1 1 MOV B Rs aa 16 2 1 MOV B Rs aa 24 3 1 MOV W xx 16 Rd 2 MOV W Rs Rd 1 MOV W ERs Rd 1 1 MOV W d 16 ERs Rd 2 1 MOV W d 24 ERs Rd 4 1 MOV W ERs Rd 1 1 2 MOV W aa 16 Rd 2 1 MOV W aa 24 Rd 3 1 MOV W Rs ERd 1 1 MOV W Rs d 16 ERd 2 1 MOV W Rs d 24 ERd 4 1 MOV W Rs ERd 1 1 2 MOV W Rs aa 16 2 1 MOV W Rs aa 24 3 1 MOV L xx 32 ERd 3 MOV L ERs ERd 1 MOV L ERs ERd 2 2 MOV L d 16 ERs ERd 3 ...

Page 741: ...20 NEG NEG B Rd 1 NEG W Rd 1 NEG L ERd 1 NOP NOP 1 NOT NOT B Rd 1 NOT W Rd 1 NOT L ERd 1 OR OR B xx 8 Rd 1 OR B Rs Rd 1 OR W xx 16 Rd 2 OR W Rs Rd 1 OR L xx 32 ERd 3 OR L ERs ERd 2 ORC ORC xx 8 CCR 1 POP POP W Rn 1 1 2 POP L ERn 2 2 2 PUSH PUSH W Rn 1 1 2 PUSH L ERn 2 2 2 ROTL ROTL B Rd 1 ROTL W Rd 1 ROTL L ERd 1 ROTR ROTR B Rd 1 ROTR W Rd 1 ROTR L ERd 1 ROTXL ROTXL B Rd 1 ROTXL W Rd 1 ROTXL L ERd...

Page 742: ...R SHLR B Rd 1 SHLR W Rd 1 SHLR L ERd 1 SLEEP SLEEP 1 STC STC CCR Rd 1 STC CCR ERd 2 1 STC CCR d 16 ERd 3 1 STC CCR d 24 ERd 5 1 STC CCR ERd 2 1 2 STC CCR aa 16 3 1 STC CCR aa 24 4 1 SUB SUB B Rs Rd 1 SUB W xx 16 Rd 2 SUB W Rs Rd 1 SUB L xx 32 ERd 3 SUB L ERs ERd 1 SUBS SUBS 1 2 4 ERd 1 SUBX SUBX xx 8 Rd 1 SUBX Rs Rd 1 TRAPA TRAPA x 2 Normal 2 1 2 4 Advanced 2 2 2 4 XOR XOR B xx 8 Rd 1 XOR B Rs Rd ...

Page 743: ...27 DTCR0A 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode DTE DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A Full address mode H 28 MAR0BR 8 H 29 MAR0BE 8 H 2A MAR0BH 8 H 2B MAR0BL 8 H 2C ETCR0BH 8 H 2D ETCR0BL 8 H 2E IOAR0B 8 H 2F DTCR0B 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode DTME DAID DAIDE TMS DTS2B DTS1B DTS0B Full address mode Legend DMAC DMA controller Continued on nex...

Page 744: ... mode H 38 MAR1BR 8 H 39 MAR1BE 8 H 3A MAR1BH 8 H 3B MAR1BL 8 H 3C ETCR1BH 8 H 3D ETCR1BL 8 H 3E IOAR1B 8 H 3F DTCR1B 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode DTME DAID DAIDE TMS DTS2B DTS1B DTS0B Full address mode H 40 FLMCR 8 VPP VPPE EV PV E P Flash H 41 memory H 42 EBR1 8 LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0 H 43 EBR2 8 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 H 44 H 45 H 46 H 47 H 48 RAMC...

Page 745: ...YNC4 SYNC3 SYNC2 SYNC1 SYNC0 H 62 TMDR 8 MDF FDIR PWM4 PWM3 PWM2 PWM1 PWM0 H 63 TFCR 8 CMD1 CMD0 BFB4 BFA4 BFB3 BFA3 H 64 TCR0 8 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H 65 TIOR0 8 IOB2 IOB1 IOB0 IOA2 IOA1 IOA0 H 66 TIER0 8 OVIE IMIEB IMIEA H 67 TSR0 8 OVF IMFB IMFA H 68 TCNT0H 16 H 69 TCNT0L H 6A GRA0H 16 H 6B GRA0L H 6C GRB0H 16 H 6D GRB0L H 6E TCR1 8 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0...

Page 746: ...A2H 16 H 7F GRA2L H 80 GRB2H 16 H 81 GRB2L H 82 TCR3 8 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H 83 TIOR3 8 IOB2 IOB1 IOB0 IOA2 IOA1 IOA0 H 84 TIER3 8 OVIE IMIEB IMIEA H 85 TSR3 8 OVF IMFB IMFA H 86 TCNT3H 16 H 87 TCNT3L H 88 GRA3H 16 H 89 GRA3L H 8A GRB3H 16 H 8B GRB3L H 8C BRA3H 16 H 8D BRA3L H 8E BRB3H 16 H 8F BRB3L H 90 TOER 8 EXB4 EXA4 EB3 EB4 EA4 EA3 H 91 TOCR 8 XTGD OLS4 OLS3 H 92 TCR4 8 ...

Page 747: ...NDR9 NDR8 8 NDR15 NDR14 NDR13 NDR12 H A5 NDRA 1 8 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 8 NDR7 NDR6 NDR5 NDR4 H A6 NDRB 1 8 8 NDR11 NDR10 NDR9 NDR8 H A7 NDRA 1 8 8 NDR3 NDR2 NDR1 NDR0 H A8 TCSR 2 8 OVF WT IT TME CKS2 CKS1 CKS0 WDT H A9 TCNT 2 8 H AA H AB RSTCSR 3 8 WRST RSTOE H AC RFSHCR 8 SRFMD PSRAME DRAME CAS WE M9 M8 RFSHE RCYCE H AD RTMCSR 8 CMF CMIE CKS2 CKS1 CKS0 H AE RTCNT 8 H AF RTCOR 8...

Page 748: ... P26 P25 P24 P23 P22 P21 P20 Port 2 H C4 P3DDR 8 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port 3 H C5 P4DDR 8 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Port 4 H C6 P3DR 8 P37 P36 P35 P34 P33 P32 P31 P30 Port 3 H C7 P4DR 8 P47 P46 P45 P44 P43 P42 P41 P40 Port 4 H C8 P5DDR 8 P53DDR P52DDR P51DDR P50DDR Port 5 H C9 P6DDR 8 P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR ...

Page 749: ...0 H E4 ADDRCH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H E5 ADDRCL 8 AD1 AD0 H E6 ADDRDH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H E7 ADDRDL 8 AD1 AD0 H E8 ADCSR 8 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 H E9 ADCR 8 TRGE H EA H EB H EC ABWCR 8 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Bus controller H ED ASTCR 8 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 H EE WCR 8 WMS1 WMS0 WC1 WC0 H EF WCER 8 WCE7 WCE6 WCE5 WCE4 WCE3 ...

Page 750: ... Continued from preceding page Data Address Register Bus low Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H FA H FB H FC H FD H FE H FF Bit Names 743 www DataSheet4U com ...

Page 751: ...it settings Read only Write only Read and write R W R W Possible types of access Bit Initial value Read Write 7 1 6 1 5 1 4 STR4 0 R W 3 STR3 0 R W 0 STR0 0 R W 2 STR2 0 R W 1 STR1 0 R W Counter start 0 0 TCNT0 is halted 1 TCNT0 is counting Counter start 3 0 TCNT3 is halted 1 TCNT3 is counting Counter start 1 0 TCNT1 is halted 1 TCNT1 is counting Counter start 2 0 TCNT2 is halted 1 TCNT2 is counti...

Page 752: ...2 R W 16 R W 20 R W 18 R W 31 1 29 1 27 1 25 1 23 R W 17 R W 21 R W 19 R W MAR0AR Source or destination address MAR0AE Bit Initial value Read Write 14 R W 12 R W 10 R W 8 R W 6 R W 0 R W 4 R W 2 R W 15 R W 13 R W 11 R W 9 R W 7 R W 1 R W 5 R W 3 R W MAR0AH MAR0AL Undetermined Undetermined Undetermined 745 www DataSheet4U com ...

Page 753: ...W 4 R W 3 R W 0 R W 2 R W 1 R W Undetermined Transfer counter ETCR0AH Bit Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 R W 2 R W 1 R W Undetermined Initial count ETCR0AL Bit Initial value Read Write 14 R W 12 R W 10 R W 8 R W 6 R W 0 R W 4 R W 2 R W Transfer counter Undetermined 15 R W 13 R W 11 R W 9 R W 7 R W 1 R W 5 R W 3 R W 746 www DataSheet4U com ...

Page 754: ...W 8 R W 6 R W 0 R W 4 R W 2 R W Transfer counter Undetermined 15 R W 13 R W 11 R W 9 R W 7 R W 1 R W 5 R W 3 R W Bit Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 R W 2 R W 1 R W Undetermined Block size counter ETCR0AH Bit Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 R W 2 R W 1 R W Undetermined Initial block size ETCR0AL 747 www DataSheet4U com ...

Page 755: ...ess Register 0A H 26 DMAC0 Bit Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 R W 2 R W 1 R W Short address mode Full address mode Undetermined source or destination address not used 748 www DataSheet4U com ...

Page 756: ...tivation Source Compare match input capture A interrupt from ITU channel 0 Compare match input capture A interrupt from ITU channel 1 Compare match input capture A interrupt from ITU channel 2 Compare match input capture A interrupt from ITU channel 3 SCI0 transmit data empty interrupt SCI0 receive data full interrupt Bit 2 DTS1 0 1 0 1 Bit 1 DTS0 0 1 0 1 0 1 0 Bit 0 Repeat enable Description I O ...

Page 757: ...ansfer select 0A 0 Normal mode 1 Block transfer mode Data transfer select 2A and 1A Set both bits to 1 Data transfer size 0 Byte size transfer 1 Word size transfer Increment Decrement Enable MARA is held fixed MARA is held fixed Decremented 0 1 0 1 0 1 SAID Bit 5 SAIDE Bit 4 Incremented 0 Interrupt request by DTE bit is disabled 1 Interrupt request by DTE bit is enabled If DTSZ 0 MARA is decrement...

Page 758: ...2 R W 16 R W 20 R W 18 R W 31 1 29 1 27 1 25 1 23 R W 17 R W 21 R W 19 R W MAR0BR Source or destination address MAR0BE Bit Initial value Read Write 14 R W 12 R W 10 R W 8 R W 6 R W 0 R W 4 R W 2 R W 15 R W 13 R W 11 R W 9 R W 7 R W 1 R W 5 R W 3 R W MAR0BH MAR0BL Undetermined Undetermined Undetermined 751 www DataSheet4U com ...

Page 759: ... R W 8 R W 6 R W 0 R W 4 R W 2 R W Transfer counter Undetermined 15 R W 13 R W 11 R W 9 R W 7 R W 1 R W 5 R W 3 R W Bit Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 R W 2 R W 1 R W Undetermined Transfer counter ETCR0BH Bit Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 R W 2 R W 1 R W Undetermined Initial count ETCR0BL 752 www DataSheet4U com ...

Page 760: ...W 2 R W Not used Undetermined 15 R W 13 R W 11 R W 9 R W 7 R W 1 R W 5 R W 3 R W Bit Initial value Read Write 14 R W 12 R W 10 R W 8 R W 6 R W 0 R W 4 R W 2 R W Block transfer counter Undetermined 15 R W 13 R W 11 R W 9 R W 7 R W 1 R W 5 R W 3 R W Bit Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 R W 2 R W 1 R W Short address mode Full address mode Undetermined source or destination add...

Page 761: ...e CPU when the DTE bit 0 0 1 Data Transfer Activation Source Compare match input capture A interrupt from ITU channel 0 Compare match input capture A interrupt from ITU channel 1 Compare match input capture A interrupt from ITU channel 2 Compare match input capture A interrupt from ITU channel 3 SCI0 transmit data empty interrupt SCI0 receive data full interrupt Falling edge of input Bit 2 DTS1 0 ...

Page 762: ...ansfer mode Data transfer select 2B to 0B DTS2B 0 1 Normal Mode Auto request burst mode Not available Auto request cycle steal mode Not available Not available Not available Falling edge of Bit 2 DTS1B 0 1 0 1 Bit 1 DTS0B 0 1 0 1 0 1 Bit 0 0 Low level input at 1 Data Transfer Activation Source Block Transfer Mode Compare match input capture A from ITU channel 0 Compare match input capture A from I...

Page 763: ...6 R W 20 R W 18 R W 31 1 29 1 27 1 25 1 23 R W 17 R W 21 R W 19 R W MAR1AR MAR1AE Bit Initial value Read Write 14 R W 12 R W 10 R W 8 R W 6 R W 0 R W 4 R W 2 R W 15 R W 13 R W 11 R W 9 R W 7 R W 1 R W 5 R W 3 R W MAR1AH MAR1AL Undetermined Undetermined Undetermined Note Bit functions are the same as for DMAC0 756 www DataSheet4U com ...

Page 764: ...W 5 R W 3 R W Note Bit functions are the same as for DMAC0 Undetermined Bit Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 R W 2 R W 1 R W Undetermined Bit Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 R W 2 R W 1 R W Undetermined ETCR1AH ETCR1AL Bit Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 R W 2 R W 1 R W Undetermined Note Bit functions are the same as for DMA...

Page 765: ... W 6 DTSZ 0 R W 5 SAID 0 R W 4 SAIDE 0 R W 3 DTIE 0 R W 0 DTS0A 0 R W 2 DTS2A 0 R W 1 DTS1A 0 R W Note Bit functions are the same as for DMAC0 Bit Initial value Read Write 30 1 28 1 26 1 24 1 22 R W 16 R W 20 R W 18 R W 31 1 29 1 27 1 25 1 23 R W 17 R W 21 R W 19 R W MAR1BR MAR1BE Bit Initial value Read Write 14 R W 12 R W 10 R W 8 R W 6 R W 0 R W 4 R W 2 R W 15 R W 13 R W 11 R W 9 R W 7 R W 1 R W...

Page 766: ...W 5 R W 3 R W Note Bit functions are the same as for DMAC0 Undetermined Bit Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 R W 2 R W 1 R W Undetermined Bit Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 R W 2 R W 1 R W Undetermined ETCR1BH ETCR1BL Bit Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 R W 2 R W 1 R W Undetermined Note Bit functions are the same as for DMA...

Page 767: ...ad Write 7 DTE 0 R W 6 DTSZ 0 R W 5 DTID 0 R W 4 RPE 0 R W 3 DTIE 0 R W 0 DTS0 0 R W 2 DTS2 0 R W 1 DTS1 0 R W Bit Initial value Read Write 7 DTME 0 R W 6 0 R W 5 DAID 0 R W 4 DAIDE 0 R W 3 TMS 0 R W 0 DTS0B 0 R W 2 DTS2B 0 R W 1 DTS1B 0 R W Note Bit functions are the same as for DMAC0 760 www DataSheet4U com ...

Page 768: ...ial value Transition to program verify mode Erase verify mode 0 1 Exit from erase verify mode Initial value Transition to erase verify mode 0 1 VPP pin 12 V power supply is disabled Initial value VPP pin 12 V power supply is enabled V enable PP Programming power 0 1 Cleared when 12 V is not applied to V Initial value Set when 12 V is applied to V PP PP PP Note The initial value is H 00 in modes 5 ...

Page 769: ...n chip flash memory enabled In modes 1 2 3 and 4 on chip flash memory disabled this register cannot be modified and is always read as H FF Bit Initial value R W 7 0 SB7 6 5 4 3 2 1 0 0 0 0 0 0 R W R W R W R W 0 0 SB6 SB5 SB4 SB3 SB2 SB1 SB0 R W R W R W R W Small block 7 to 0 0 1 Block SB7 to SB0 is not selected Initial value Block SB7 to SB0 is selected Note The initial value is H 00 in modes 5 6 ...

Page 770: ... Bit 0 RAM 0 1 0 0 1 0 1 0 1 0 1 H FFF000 to H FFF1FF H 01F000 to H 01F1FF H 01F200 to H 01F3FF H 01F400 to H 01F5FF H 01F600 to H 01F7FF H 01F800 to H 01F9FF H 01FA00 to H 01FBFF H 01FC00 to H 01FDFF H 01FE00 to H 01FFFF 0 1 0 1 0 1 1 Flash memory error 0 1 Flash memory is not write erase protected Initial value is not in error protect mode Flash memory is write erase protected is in error protec...

Page 771: ... 5 1 4 1 3 1 0 DASTE 0 R W 2 1 1 1 D A standby enable 0 D A output is disabled in software standby mode 1 D A output is enabled in software standby mode Bit Initial value Read Write 7 1 6 1 5 1 3 1 0 DIV0 0 R W 2 1 1 DIV1 0 R W Divide 1 and 0 DIV1 Frequency Division Ratio DIV0 Bit 0 Bit 1 0 1 1 1 1 2 1 4 1 8 0 0 1 1 7 1 764 www DataSheet4U com ...

Page 772: ...perates normally Initial value 1 SCI1 is in standby state Module standby 1 0 Refresh controller operates normally Initial value 1 Refresh controller is in standby state Module standby 2 0 DMAC operates normally Initial value 1 DMAC is in standby state Module standby 4 0 SCI0 operates normally Initial value 1 SCI0 is in standby state Module standby 5 0 ITU operates normally Initial value 1 ITU is i...

Page 773: ...s counting Counter start 1 0 TCNT1 is halted 1 TCNT1 is counting Counter start 2 0 TCNT2 is halted 1 TCNT2 is counting Counter start 4 0 TCNT4 is halted 1 TCNT4 is counting Bit Initial value Read Write 7 CS7E 0 R W 6 CS6E 0 R W 5 CS5E 0 R W 4 CS4E 0 R W 3 1 0 1 2 1 1 1 Chip select 7 to 4 enable n 7 to 4 Output of chip select signal CSn is disabled Initial value Output of chip select signal CSn is ...

Page 774: ...NC2 0 R W 1 SYNC1 0 R W Timer sync 0 0 TCNT0 operates independently 1 TCNT0 is synchronized Timer sync 3 0 TCNT3 operates independently 1 TCNT3 is synchronized Timer sync 1 0 TCNT1 operates independently 1 TCNT1 is synchronized Timer sync 2 0 TCNT2 operates independently 1 TCNT2 is synchronized Timer sync 4 0 TCNT4 operates independently 1 TCNT4 is synchronized 767 www DataSheet4U com ...

Page 775: ...el 3 operates in PWM mode PWM mode 1 0 Channel 1 operates normally 1 Channel 1 operates in PWM mode PWM mode 2 0 Channel 2 operates normally 1 Channel 2 operates in PWM mode PWM mode 4 0 Channel 4 operates normally 1 Channel 4 operates in PWM mode Flag direction 0 OVF is set to 1 in TSR2 when TCNT2 overflows or underflows 1 OVF is set to 1 in TSR2 when TCNT2 overflows Phase counting mode flag 0 Ch...

Page 776: ...GRB4 operates normally 1 GRB4 is buffered by BRB4 Buffer mode B3 0 GRB3 operates normally 1 GRB3 is buffered by BRB3 Buffer mode A4 0 GRA4 operates normally 1 GRA4 is buffered by BRA4 Combination mode 1 and 0 Channels 3 and 4 operate normally Channels 3 and 4 operate together in complementary PWM mode Channels 3 and 4 operate together in reset synchronized PWM mode Bit 5 0 1 Bit 4 0 1 0 1 Operatin...

Page 777: ...n with other synchronized timers Bit 6 0 1 Bit 5 0 0 1 TCNT Clear Source CCLR1 CCLR0 TCNT is cleared by GRA compare match or input capture 1 Rising edges counted Both edges counted Bit 4 0 1 Bit 3 0 Counted Edges of External Clock CKEG1 CKEG0 Falling edges counted 1 TPSC2 1 TCNT Clock Source Internal clock ø Internal clock ø 2 Internal clock ø 4 Internal clock ø 8 External clock A TCLKA input Exte...

Page 778: ... 1 output at GRA compare match Output toggles at GRA compare match GRA captures rising edge of input GRA captures falling edge of input GRA captures both edges of input I O control B2 to B0 IOB2 1 GRB Function GRB is an output compare register GRB is an input capture register IOB1 0 1 0 1 Bit 5 IOB0 0 1 0 1 0 1 Bit 4 0 1 0 Bit 6 No output at compare match 0 output at GRB compare match 1 output at ...

Page 779: ... interrupt requested by IMFA flag is disabled 1 IMIA interrupt requested by IMFA flag is enabled Input capture compare match interrupt enable B 0 IMIB interrupt requested by IMFB flag is disabled 1 IMIB interrupt requested by IMFB flag is enabled Overflow interrupt enable 0 OVI interrupt requested by OVF flag is disabled 1 OVI interrupt requested by OVF flag is enabled 772 www DataSheet4U com ...

Page 780: ...ure signal when GRA functions as an input capture register Input capture compare match flag B 0 Clearing condition Read IMFB when IMFB 1 then write 0 in IMFB 1 Setting conditions TCNT GRB when GRB functions as an output compare register TCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register 0 Clearing condition Read OVF when OVF 1 then write 0 i...

Page 781: ...ite 14 1 R W 12 1 R W 10 1 R W 8 1 R W 6 1 R W 0 1 R W 4 1 R W 2 1 R W Output compare or input capture register 15 1 R W 13 1 R W 11 1 R W 9 1 R W 7 1 R W 1 1 R W 5 1 R W 3 1 R W Bit Initial value Read Write 14 1 R W 12 1 R W 10 1 R W 8 1 R W 6 1 R W 0 1 R W 4 1 R W 2 1 R W Output compare or input capture register 15 1 R W 13 1 R W 11 1 R W 9 1 R W 7 1 R W 1 1 R W 5 1 R W 3 1 R W Bit Initial value...

Page 782: ...0 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 0 IMIEA 0 R W 2 OVIE 0 R W 1 IMIEB 0 R W Note Bit functions are the same as for ITU0 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 0 IMFA 0 R W 2 OVF 0 R W 1 IMFB 0 R W Notes Bit functions are the same as for ITU0 Only 0 can be written to clear the flag Bit Initial value Read Write 14 0 R W 12 0 R W 10 0 R W 8 0 R W 6 0 R W 0 0 R W 4 0 R W 2 0 ...

Page 783: ... for ITU0 Bit Initial value Read Write 14 1 R W 12 1 R W 10 1 R W 8 1 R W 6 1 R W 0 1 R W 4 1 R W 2 1 R W 15 1 R W 13 1 R W 11 1 R W 9 1 R W 7 1 R W 1 1 R W 5 1 R W 3 1 R W Note Bit functions are the same as for ITU0 Bit Initial value Read Write 7 1 6 CCLR1 0 R W 5 CCLR0 0 R W 4 CKEG1 0 R W 3 CKEG0 0 R W 0 TPSC0 0 R W 2 TPSC2 0 R W 1 TPSC1 0 R W Notes Bit functions are the same as for ITU0 When ch...

Page 784: ...Read Write 7 1 6 1 5 1 4 1 3 1 0 IMIEA 0 R W 2 OVIE 0 R W 1 IMIEB 0 R W Note Bit functions are the same as for ITU0 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 0 IMFA 0 R W 2 OVF 0 R W 1 IMFB 0 R W Note Only 0 can be written to clear the flag Bit functions are the same as for ITU0 Overflow flag Clearing condition Read OVF when OVF 1 then write 0 in OVF Setting condition The TCNT value overflo...

Page 785: ... R W 7 0 R W 1 0 R W 5 0 R W 3 0 R W up down counter up counter 778 Bit Initial value Read Write 14 1 R W 12 1 R W 10 1 R W 8 1 R W 6 1 R W 0 1 R W 4 1 R W 2 1 R W 15 1 R W 13 1 R W 11 1 R W 9 1 R W 7 1 R W 1 1 R W 5 1 R W 3 1 R W Note Bit functions are the same as for ITU0 Bit Initial value Read Write 14 1 R W 12 1 R W 10 1 R W 8 1 R W 6 1 R W 0 1 R W 4 1 R W 2 1 R W 15 1 R W 13 1 R W 11 1 R W 9 ...

Page 786: ... IOA0 0 R W 2 IOA2 0 R W 1 IOA1 0 R W Note Bit functions are the same as for ITU0 779 Bit Initial value Read Write 7 1 6 CCLR1 0 R W 5 CCLR0 0 R W 4 CKEG1 0 R W 3 CKEG0 0 R W 0 TPSC0 0 R W 2 TPSC2 0 R W 1 TPSC1 0 R W Note Bit functions are the same as for ITU0 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 0 IMIEA 0 R W 2 OVIE 0 R W 1 IMIEB 0 R W Note Bit functions are the same as for ITU0 www D...

Page 787: ...al value Read Write 14 1 R W 12 1 R W 10 1 R W 8 1 R W 6 1 R W 0 1 R W 4 1 R W 2 1 R W Output compare or input capture register can be buffered 15 1 R W 13 1 R W 11 1 R W 9 1 R W 7 1 R W 1 1 R W 5 1 R W 3 1 R W Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 0 IMFA 0 R W 2 OVF 0 R W 1 IMFB 0 R W Overflow flag 0 Clearing condition Read OVF when OVF 1 then write 1 in OVF 1 Setting condition TCNT ov...

Page 788: ... 11 1 R W 9 1 R W 7 1 R W 1 1 R W 5 1 R W 3 1 R W 781 Bit Initial value Read Write 14 1 R W 12 1 R W 10 1 R W 8 1 R W 6 1 R W 0 1 R W 4 1 R W 2 1 R W Output compare or input capture register can be buffered 15 1 R W 13 1 R W 11 1 R W 9 1 R W 7 1 R W 1 1 R W 5 1 R W 3 1 R W Bit Initial value Read Write 14 1 R W 12 1 R W 10 1 R W 8 1 R W 6 1 R W 0 1 R W 4 1 R W 2 1 R W Used to buffer GRA 15 1 R W 13...

Page 789: ... to TIOR3 and TFCR settings Master enable TIOCA4 0 TIOCA output is disabled regardless of TIOR4 TMDR and TFCR settings 1 TIOCA is enabled for output according to TIOR4 TMDR and TFCR settings Master enable TIOCB4 0 TIOCB output is disabled regardless of TIOR4 and TFCR settings 1 TIOCB is enabled for output according to TIOR4 and TFCR settings Master enable TOCXA4 0 TOCXA output is disabled regardle...

Page 790: ...ted Output level select 4 0 TIOCA TIOCA and TIOCB outputs are inverted 1 TIOCA TIOCA and TIOCB outputs are not inverted External trigger disable 0 Input capture A in channel 1 is used as an external trigger signal in reset synchronized PWM mode and complementary PWM mode 1 External triggering is disabled XTGD Note When an external trigger occurs bits 5 to 0 in TOER are cleared to 0 disabling ITU o...

Page 791: ...tions are the same as for ITU0 Bit Initial value Read Write 7 1 6 IOB2 0 R W 5 IOB1 0 R W 4 IOB0 0 R W 3 1 0 IOA0 0 R W 2 IOA2 0 R W 1 IOA1 0 R W Note Bit functions are the same as for ITU0 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 0 IMIEA 0 R W 2 OVIE 0 R W 1 IMIEB 0 R W Note Bit functions are the same as for ITU0 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 0 IMFA 0 R W 2 OVF 0 R W 1 ...

Page 792: ...rite 14 1 R W 12 1 R W 10 1 R W 8 1 R W 6 1 R W 0 1 R W 4 1 R W 2 1 R W 15 1 R W 13 1 R W 11 1 R W 9 1 R W 7 1 R W 1 1 R W 5 1 R W 3 1 R W Note Bit functions are the same as for ITU3 Bit Initial value Read Write 14 1 R W 12 1 R W 10 1 R W 8 1 R W 6 1 R W 0 1 R W 4 1 R W 2 1 R W 15 1 R W 13 1 R W 11 1 R W 9 1 R W 7 1 R W 1 1 R W 5 1 R W 3 1 R W Note Bit functions are the same as for ITU3 Bit Initia...

Page 793: ...ontrolled by compare match A and B in the selected ITU channel Group 2 non overlap 0 Normal TPC output in group 2 Output values change at compare match A in the selected ITU channel 1 Non overlapping TPC output in group 2 controlled by compare match A and B in the selected ITU channel Group 1 non overlap 0 Normal TPC output in group 1 Output values change at compare match A in the selected ITU cha...

Page 794: ...h in ITU channel 3 Bit 5 0 1 Bit 4 0 0 1 ITU Channel Selected as Output Trigger G2CMS1 G2CMS0 TPC output group 2 TP to TP is triggered by compare match in ITU channel 1 1 11 11 11 11 8 8 8 8 Group 1 compare match select 1 and 0 TPC output group 1 TP to TP is triggered by compare match in ITU channel 0 TPC output group 1 TP to TP is triggered by compare match in ITU channel 2 TPC output group 1 TP ...

Page 795: ... TPC outputs TP to TP are enabled NDR15 to NDR8 are transferred to PB to PB Bits 7 to 0 0 1 Description NDER15 to NDER8 15 15 8 8 7 7 0 0 Bit Initial value Read Write 7 NDER7 0 R W 6 NDER6 0 R W 5 NDER5 0 R W 4 NDER4 0 R W 3 NDER3 0 R W 0 NDER0 0 R W 2 NDER2 0 R W 1 NDER1 0 R W Next data enable 7 to 0 TPC outputs TP to TP are disabled NDR7 to NDR0 are not transferred to PA to PA TPC outputs TP to ...

Page 796: ...DR10 0 R W 1 NDR9 0 R W Store the next output data for TPC output group 3 Store the next output data for TPC output group 2 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 0 1 2 1 1 1 Bit Initial value Read Write 7 NDR15 0 R W 6 NDR14 0 R W 5 NDR13 0 R W 4 NDR12 0 R W 3 1 0 1 2 1 1 1 Store the next output data for TPC output group 3 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 NDR11 0 R W 0 NDR...

Page 797: ...NDR2 0 R W 1 NDR1 0 R W Store the next output data for TPC output group 1 Store the next output data for TPC output group 0 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 0 1 2 1 1 1 Bit Initial value Read Write 7 NDR7 0 R W 6 NDR6 0 R W 5 NDR5 0 R W 4 NDR4 0 R W 3 1 0 1 2 1 1 1 Store the next output data for TPC output group 1 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 NDR3 0 R W 0 NDR0 0 R...

Page 798: ...OVF 1 Setting condition TCNT changes from H FF to H 00 0 Interval timer requests interval timer interrupts 1 Watchdog timer generates a reset signal Clock select 2 to 0 0 1 ø 2 ø 32 ø 64 ø 128 ø 256 ø 512 ø 2048 0 1 0 1 0 1 0 1 0 1 0 ø 4096 1 Timer enable 0 Timer disabled 1 Timer enabled TCNT is initialized to H 00 and halted TCNT is counting CPU interrupt requests are enabled Note Only 0 can be w...

Page 799: ...ue Read Write 7 WRST 0 R W 6 RSTOE 0 R W 5 1 4 1 3 1 0 1 2 1 1 1 Reset output enable 0 External output of reset signal is disabled 1 External output of reset signal is enabled Watchdog timer reset 0 Clearing condition Reset signal input at RES pin When WRST 1 write 0 after reading WRST flag 1 Setting condition TCNT overflow generates a reset signal Note Only 0 can be written in bit 7 to clear the ...

Page 800: ...h pin enable PSRAM enable DRAM enable 0 Refresh cycles are disabled 1 Refresh cycles are enabled for area 3 Address multiplex mode select 0 8 bit column mode 1 9 bit column mode WE M8 Strobe mode select 0 1 0 2 mode 1 2 mode Can be used as an interval timer DRAM and PSRAM cannot be directly connected PSRAM can be directly connected Illegal setting Bit 6 0 1 Bit 5 0 0 1 RAM Interface PSRAME DRAME D...

Page 801: ... 0 Clearing condition Read CMF when CMF 1 then write 0 in CMF 1 Setting condition RTCNT RTCOR Note Only 0 can be written to clear the flag 0 The CMI interrupt requested by CMF is disabled 1 The CMI interrupt requested by CMF is enabled Clock select 2 to 0 CKS2 Counter Clock Source CKS1 Bit 4 CKS0 Bit 3 Bit 5 0 1 Clock input is disabled ø 2 ø 8 ø 32 ø 128 ø 512 ø 2048 0 1 0 1 0 1 0 1 0 1 0 ø 4096 1...

Page 802: ...AF Refresh controller Bit Initial value Read Write 7 0 R W 6 0 R W 5 0 R W 4 0 R W 3 0 R W 0 0 R W 2 0 R W 1 0 R W Count value Bit Initial value Read Write 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Interval at which RTCNT and compare match are set 795 www DataSheet4U com ...

Page 803: ...or checked 1 Parity bit is added and checked Parity mode 0 Even parity 1 Odd parity Stop bit length Multiprocessor mode 0 Multiprocessor function disabled 1 Multiprocessor format selected 0 One stop bit 1 Two stop bits Character length 0 8 bit data 1 7 bit data Communication mode when using a serial communication interface 0 Asynchronous mode 1 Synchronous mode GSM mode when using a smart card int...

Page 804: ...BRR Bit Rate Register H B1 SCI0 Bit Initial value Read Write 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Serial communication bit rate setting 797 www DataSheet4U com ...

Page 805: ...Asynchronous mode Synchronous mode Asynchronous mode Bit 1 CKE0 0 1 0 1 Bit 0 Receive enable Synchronous mode 0 Multiprocessor interrupts are disabled normal receive operation 1 Multiprocessor interrupts are enabled 0 Receiving is disabled 1 Receiving is enabled Transmit end interrupt enable 0 Transmitting is disabled 1 Transmitting is enabled 0 Transmit end interrupt requests TEI are disabled 1 T...

Page 806: ...TDR Transmit Data Register H B3 SCI0 Bit Initial value Read Write 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Serial transmit data 799 www DataSheet4U com ...

Page 807: ...ce 0 Clearing conditions 1 Setting condition A low error signal is received Reset or transition to standby mode Read ERS when ERS 1 then write 0 in ERS Overrun error 0 Clearing conditions 1 Setting condition Overrun error reception of next serial data ends when RDRF 1 Reset or transition to standby mode Read ORER when ORER 1 then write 0 in ORER Receive data register full 0 Clearing conditions 1 S...

Page 808: ...ction is disabled Initial value 1 Smart card interface function is enabled Smart card data invert 0 Unmodified TDR contents are transmitted Initial value Received data is stored unmodified in RDR 1 Inverted TDR contents are transmitted Received data are inverted before storage in RDR Smart card data transfer direction 0 TDR contents are transmitted LSB first Initial value Received data is stored L...

Page 809: ... 2 MP 0 R W 1 CKS1 0 R W Note Bit functions are the same as for SCI0 A E Bit Initial value Read Write 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Note Bit functions are the same as for SCI0 Bit Initial value Read Write 7 TIE 0 R W 6 RIE 0 R W 5 TE 0 R W 4 RE 0 R W 3 MPIE 0 R W 0 CKE0 0 R W 2 TEIE 0 R W 1 CKE1 0 R W Note Bit functions are the same as for SCI0 802 www DataSheet4U...

Page 810: ... W Note Bit functions are the same as for SCI0 Bit Initial value Read Write 7 TDRE 1 R W 6 RDRF 0 R W 5 ORER 0 R W 4 FER 0 R W 3 PER 0 R W 0 MPBT 0 R W 2 TEND 1 R 1 MPB 0 R Notes Bit functions are the same as for SCI0 Only 0 can be written to clear the flag Bit Initial value Read Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 0 0 R 2 0 R 1 0 R Note Bit functions are the same as for SCI0 803 www DataSheet4U c...

Page 811: ...DDR 1 0 W 0 Port 1 input output select 0 Generic input pin 1 Generic output pin Bit Modes 1 to 4 Initial value Read Write Initial value Read Write Modes 5 to 7 7 P2 DDR 1 0 W 7 6 P2 DDR 1 0 W 6 5 P2 DDR 1 0 W 5 4 P2 DDR 1 0 W 4 3 P2 DDR 1 0 W 3 2 P2 DDR 1 0 W 2 1 P2 DDR 1 0 W 1 0 P2 DDR 1 0 W 0 Port 2 input output select 0 Generic input pin 1 Generic output pin Bit Initial value Read Write 7 P1 0 ...

Page 812: ... for port 2 pins Bit Initial value Read Write 7 P3 DDR 0 W 7 6 P3 DDR 0 W 6 5 P3 DDR 0 W 5 4 P3 DDR 0 W 4 3 P3 DDR 0 W 3 2 P3 DDR 0 W 2 1 P3 DDR 0 W 1 0 P3 DDR 0 W 0 Port 3 input output select 0 Generic input pin 1 Generic output pin Bit Initial value Read Write 7 P4 DDR 0 W 7 6 P4 DDR 0 W 6 5 P4 DDR 0 W 5 4 P4 DDR 0 W 4 3 P4 DDR 0 W 3 2 P4 DDR 0 W 2 1 P4 DDR 0 W 1 0 P4 DDR 0 W 0 Port 4 input outp...

Page 813: ...1 0 P3 0 R W 0 Data for port 3 pins Bit Initial value Read Write 7 P4 0 R W 7 6 P4 0 R W 6 5 P4 0 R W 5 4 P4 0 R W 4 3 P4 0 R W 3 2 P4 0 R W 2 1 P4 0 R W 1 0 P4 0 R W 0 Data for port 4 pins Bit Modes 1 to 4 Initial value Read Write Initial value Read Write Modes 5 to 7 7 1 1 6 1 1 5 1 1 4 1 1 3 P5 DDR 1 0 W 3 2 P5 DDR 1 0 W 2 1 P5 DDR 1 0 W 1 0 P5 DDR 1 0 W 0 Port 5 input output select 0 Generic i...

Page 814: ... P6 DDR 0 W 3 2 P6 DDR 0 W 2 1 P6 DDR 0 W 1 0 P6 DDR 0 W 0 Port 6 input output select 0 Generic input 1 Generic output Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 P5 0 R W 3 2 P5 0 R W 2 1 P5 0 R W 1 0 P5 0 R W 0 Data for port 5 pins Bit Initial value Read Write 7 1 6 P6 0 R W 6 5 P6 0 R W 5 4 P6 0 R W 4 3 P6 0 R W 3 2 P6 0 R W 2 1 P6 0 R W 1 0 P6 0 R W 0 Data for port 6 pins 807 www DataSheet4...

Page 815: ... 0 W 1 0 P8 DD 0 W 0 W 0 4 P8 DDR 1 W 0 W 4 Port 8 input output se Port 8 input output select 0 Generic input 1 Generic output 0 Generic input 1 output CS Bit Initial value Read Write 0 P7 R Note Determined by pins P7 to P7 0 1 P7 R 1 2 P7 R 2 3 P7 R 3 4 P7 R 4 5 P7 R 5 6 P7 R 6 7 P7 R 7 Read the pin levels for port 7 7 0 Bit Initial value Read Write 7 1 6 1 5 1 4 P8 0 R W 4 3 P8 0 R W 3 2 P8 0 R ...

Page 816: ...0 Generic input 1 Generic output Bit Modes 3 4 6 Initial value Read Write Initial value Read Write Modes 1 2 5 7 3 2 1 0 4 7 PA DDR 1 0 W 7 6 PA DDR 0 W 0 W 6 5 PA DDR 0 W 0 W 5 4 PA DDR 0 W 0 W 4 3 PA DDR 0 W 0 W 3 2 PA DDR 0 W 0 W 2 1 PA DDR 0 W 0 W 1 0 PA DDR 0 W 0 W 0 Port A input output select 0 Generic input 1 Generic output Bit Initial value Read Write 7 1 6 1 5 P9 0 R W 4 P9 0 R W 4 3 P9 0...

Page 817: ...6 PA 0 R W 6 7 PA 0 R W 7 Data for port A pins Bit Initial value Read Write 7 PB DDR 0 W 7 6 PB DDR 0 W 6 5 PB DDR 0 W 5 4 PB DDR 0 W 4 3 PB DDR 0 W 3 2 PB DDR 0 W 2 1 PB DDR 0 W 1 0 PB DDR 0 W 0 Port B input output select 0 Generic input 1 Generic output Bit Initial value Read Write 0 PB 0 R W 0 1 PB 0 R W 1 2 PB 0 R W 2 3 PB 0 R W 3 4 PB 0 R W 4 5 PB 0 R W 5 6 PB 0 R W 6 7 PB 0 R W 7 Data for po...

Page 818: ...put pull up transistor is off 1 Input pull up transistor is on Note Valid when the corresponding P2DDR bit is cleared to 0 designating generic input Bit Initial value Read Write 7 P4 PCR 0 R W 7 6 P4 PCR 0 R W 6 5 P4 PCR 0 R W 5 4 P4 PCR 0 R W 4 3 P4 PCR 0 R W 3 2 P4 PCR 0 R W 2 1 P4 PCR 0 R W 1 0 P4 PCR 0 R W 0 Port 4 input pull up MOS control 7 to 0 0 Input pull up transistor is off 1 Input pull...

Page 819: ... Port 5 input pull up MOS control 3 to 0 0 Input pull up transistor is off 1 Input pull up transistor is on Note Valid when the corresponding P5DDR bit is cleared to 0 designating generic input Bit Initial value Read Write 7 0 R W 6 0 R W 5 0 R W 4 0 R W 3 0 R W 0 0 R W 2 0 R W 1 0 R W D A conversion data Bit Initial value Read Write 7 0 R W 6 0 R W 5 0 R W 4 0 R W 3 0 R W 0 0 R W 2 0 R W 1 0 R W ...

Page 820: ...n is disabled in channels 0 and 1 D A conversion is disabled in channel 0 D A conversion is enabled in channel 1 D A conversion is enabled in channels 0 and 1 D A conversion is enabled in channels 0 and 1 Bit 7 DAOE0 0 0 1 Bit 6 DAE 0 1 Bit 5 D A conversion is enabled in channel 0 D A conversion is disabled in channel 1 1 0 D A conversion is enabled in channels 0 and 1 1 Bit Initial value Read Wri...

Page 821: ...data giving an A D conversion result Bit Initial value Read Write 14 AD8 0 R 12 AD6 0 R 10 AD4 0 R 8 AD2 0 R 6 AD0 0 R 0 0 R 4 0 R 2 0 R 15 AD9 0 R 13 AD7 0 R 11 AD5 0 R 9 AD3 0 R 7 AD1 0 R 1 0 R 5 0 R 3 0 R ADDRCH ADDRCL A D conversion data 10 bit data giving an A D conversion result Bit Initial value Read Write 14 AD8 0 R 12 AD6 0 R 10 AD4 0 R 8 AD2 0 R 6 AD0 0 R 0 0 R 4 0 R 2 0 R 15 AD9 0 R 13 ...

Page 822: ...A D Bit Initial value Read Write 7 TRGE 0 R W 6 1 5 1 4 1 3 1 0 1 2 1 1 1 Trigger enable 0 A D conversion cannot be externally triggered 1 A D conversion starts at the fall of the external trigger signal ADTRG 815 www DataSheet4U com ...

Page 823: ...le A D start Clock select Scan mode 0 Clearing condition Read ADF while ADF 1 then write 0 in ADF 1 Setting conditions Single mode Scan mode 0 A D end interrupt request is disabled 1 A D end interrupt request is enabled 0 A D conversion is stopped 1 Single mode Scan mode 0 Single mode 1 Scan mode 0 Conversion time 266 states maximum 1 Conversion time 134 states maximum A D conversion ends A D conv...

Page 824: ...a 7 to 0 bus width control Areas 7 to 0 are 16 bit access areas Areas 7 to 0 are 8 bit access areas Bits 7 to 0 0 1 Bus Width of Access Area ABW7 to ABW0 Bit Initial value Read Write 7 AST7 1 R W 6 AST6 1 R W 5 AST5 1 R W 4 AST4 1 R W 3 AST3 1 R W 0 AST0 1 R W 2 AST2 1 R W 1 AST1 1 R W Area 7 to 0 access state control Areas 7 to 0 are two state access areas Areas 7 to 0 are three state access area...

Page 825: ...ller 1 state inserted 2 states inserted 3 states inserted 0 0 1 1 Wait mode select 1 and 0 WMS1 Wait Mode WMS0 Bit 2 Bit 3 0 1 Programmable wait mode No wait states inserted by wait state controller Pin wait mode 1 Pin auto wait mode 0 0 1 1 Bit Initial value Read Write 7 WCE7 1 R W 6 WCE6 1 R W 5 WCE5 1 R W 4 WCE4 1 R W 3 WCE3 1 R W 0 WCE0 1 R W 2 WCE2 1 R W 1 WCE1 1 R W Wait state controller ena...

Page 826: ...ite 7 1 6 1 5 0 4 0 3 0 0 MDS0 R 2 MDS2 R 1 MDS1 R Note Determined by the state of the mode pins MD to MD Mode select 2 to 0 2 0 MD2 0 Operating mode Mode 1 Mode 2 Mode 3 Bit 2 MD1 0 1 Bit 1 MD0 0 1 0 1 Bit 0 1 Mode 4 Mode 5 Mode 6 Mode 7 0 1 0 1 0 1 819 www DataSheet4U com ...

Page 827: ...ndby Timer Waiting time 8 192 states Waiting time 16 384 states Waiting time 32 768 states Waiting time 65 536 states Waiting time 131 072 states Waiting time 1 024 states Bit 6 STS1 0 1 0 Bit 5 STS0 0 1 0 1 1 Illegal setting 1 Bit 4 RAM enable 0 On chip RAM is disabled 1 On chip RAM is enabled NMI edge select 0 An interrupt is requested at the falling edge of NMI 1 An interrupt is requested at th...

Page 828: ...e bus can be released to an external device 0 Address output 1 Other input output Bit Initial value Read Write 7 0 R W 6 0 R W 5 IRQ5SC 0 R W 4 IRQ4SC 0 R W 3 IRQ3SC 0 R W 2 IRQ2SC 0 R W 1 IRQ1SC 0 R W 0 IRQ0SC 0 R W IRQ to IRQ sense control 0 Interrupts are requested when IRQ to IRQ inputs are low 1 Interrupts are requested by falling edge input at IRQ to IRQ 5 0 5 5 0 0 Bit Initial value Read Wr...

Page 829: ...ng Conditions IRQ5F to IRQ0F Clearing conditions Read IRQnF when IRQnF 1 then write 0 in IRQnF IRQnSC 0 input is high and interrupt exception handling is carried out IRQnSC 1 and IRQn interrupt exception handling is carried out Setting conditions IRQnSC 0 and IRQn input is low IRQnSC 1 and a falling edge is generated in the IRQn input n 5 to 0 IRQn 5 0 Note Only 0 can be written to clear the flag ...

Page 830: ...4 Bit 3 Bit 2 Bit 1 Bit 0 IPRB7 IPRB6 IPRB5 IPRB3 IPRB2 IPRB1 Interrupt ITU ITU DMAC SCI SCI A D source chan chan chan chan con nel 3 nel 4 nel 0 nel 1 verter Bit Initial value Read Write 7 IPRA7 0 R W 6 IPRA6 0 R W 5 IPRA5 0 R W 4 IPRA4 0 R W 3 IPRA3 0 R W 0 IPRA0 0 R W 2 IPRA2 0 R W 1 IPRA1 0 R W Priority level A7 to A0 0 Priority level 0 low priority 1 Priority level 1 high priority Bit Initial...

Page 831: ...m Reset R P1 DDR n Mode 1 to 4 WP1D Q D C Reset R P1 DR n WP1 Q D C RP1 Mode 7 Mode 1 to 6 Internal data bus upper Internal address bus WP1D WP1 RP1 n 0 to 7 Write to P1DDR Write to port 1 Read port 1 P1n External bus released Hardware standby Software standby Mode 7 824 www DataSheet4U com ...

Page 832: ...D C Reset R P2 PCR n WP2P Q D C Mode 7 Mode 1 to 6 Internal data bus upper Internal address bus P2n RP2P RP2 WP2P RP2P WP2D WP2 RP2 n 0 to 7 Write to P2PCR Read P2PCR Write to P2DDR Write to port 2 Read port 2 External bus released Hardware standby Software standby Mode 7 Mode 1 to 4 825 www DataSheet4U com ...

Page 833: ...Q D C Reset R P3 DR n WP3 Q D C RP3 Mode 1 to 6 Internal data bus upper WP3D WP3 RP3 n 0 to 7 Write to P3DDR Write to port 3 Read port 3 Mode 7 Write to external address Mode 7 Hardware standby External bus released Read external address Internal data bus lower 826 www DataSheet4U com ...

Page 834: ...P4 PCR n Q D R C P4 DDR n Q D R C P4 DR n WP4P RP4P WP4D WP4 RP4 n 0 to 7 Write to P4PCR Read P4PCR Write to P4DDR Write to port 4 Read port 4 Write to external address Read external address Internal data bus upper Internal data bus lower 8 bit bus mode Mode 7 Mode 1 to 6 16 bit bus mode 827 www DataSheet4U com ...

Page 835: ... C P5 PCR n Q D R C P5 DDR n Q D R C P5 DR n WP5P RP5P WP5D WP5 RP5 n 0 to 3 Write to P5PCR Read P5PCR Write to P5DDR Write to port 5 Read port 5 Mode 7 Mode 1 to 6 Internal data bus upper Internal address bus External bus released Hardware standby Software standby Mode 7 Mode 1 to 4 828 www DataSheet4U com ...

Page 836: ...Block Diagram Pin P60 WP6D WP6 RP6 Write to P6DDR Write to port 6 Read port 6 RP6 input WP6D Reset Q D R C P6 DDR 0 WP6 Reset Q D R C P6 DR 0 P60 Internal data bus Bus controller WAIT input enable Bus controller WAIT Mode 7 829 www DataSheet4U com ...

Page 837: ...Diagram Pin P61 P61 WP6D WP6 RP6 Write to P6DDR Write to port 6 Read port 6 WP6D Reset Q D R C P6 DDR 1 WP6 Reset Q D R C P6 DR 1 RP6 Internal data bus Bus controller Bus release enable BREQ input Mode 7 830 www DataSheet4U com ...

Page 838: ...Diagram Pin P62 WP6D Reset Q D R C P6 DDR 2 WP6 Reset Q D R C P6 DR 2 RP6 P62 WP6D WP6 RP6 Write to P6DDR Write to port 6 Read port 6 Internal data bus Bus controller Bus release enable BACK output Mode 7 831 www DataSheet4U com ...

Page 839: ...D Q D C Reset R P6 DR n WP6 Q D C RP6 Mode 1 to 6 Internal data bus WP6D WP6 RP6 n 6 to 3 Write to P6DDR Write to port 6 Read port 6 Mode 7 AS output RD output HWR output LWR output External bus released Hardware standby Software standby Mode 7 Mode 7 832 www DataSheet4U com ...

Page 840: ...b Port 7 Block Diagram Pins P76 and P77 P7n RP7 RP7 Read port 7 n 0 to 5 Internal data bus A D converter Analog input Input enable P7n RP7 RP7 Read port 7 n 6 and 7 Internal data bus A D converter Analog input D A converter Analog output Output enable Input enable 833 www DataSheet4U com ...

Page 841: ...gram Pin P80 P80 RP8 WP8D Reset Q D R C P8 DDR 0 WP8 Reset Q D R C P8 DR 0 WP8D WP8 RP8 Write to P8DDR Write to port 8 Read port 8 Internal data bus Refresh controller Output enable output Interrupt controller input RFSH IRQ0 Mode 7 834 www DataSheet4U com ...

Page 842: ...Reset Q D R C P8 DDR n WP8 Reset Q D R C P8 DR n RP8 WP8D WP8 RP8 n 1 to 3 Write to P8DDR Write to port 8 Read port 8 Internal data bus Bus controller output Interrupt controller IRQ IRQ IRQ CS CS CS 1 2 3 1 2 3 input Mode 7 Mode 1 to 6 835 www DataSheet4U com ...

Page 843: ...am Pin P84 P84 WP8D Q D S C P8 DDR 4 WP8 Reset Reset Mode 1 to 4 Q D R C P8 DR 4 RP8 WP8D WP8 RP8 Write to P8DDR Write to port 8 Read port 8 Internal data bus Bus controller output 0 CS Mode 6 7 Mode 1 to 5 R 836 www DataSheet4U com ...

Page 844: ... Port 9 Block Diagram Pin P90 WP9D WP9 RP9 Write to P9DDR Write to port 9 Read port 9 P90 RP9 WP9D Reset Q D R C P9 DDR 0 WP9 Reset Q D R C P9 DR 0 Internal data bus SCI0 Output enable Serial transmit data Guard time 837 www DataSheet4U com ...

Page 845: ...Block Diagram Pin P91 WP9D WP9 RP9 Write to P9DDR Write to port 9 Read port 9 P91 RP9 WP9D Reset Q D R C P9 DDR 1 WP9 Reset Q D R C P9 DR 1 Internal data bus SCI1 Output enable Serial transmit data 838 www DataSheet4U com ...

Page 846: ...Diagram Pins P92 P93 WP9D WP9 RP9 n 2 and 3 Write to P9DDR Write to port 9 Read port 9 P9n WP9D Reset Q D R C P9 DDR n WP9 Reset Q D R C P9 DR n RP9 Internal data bus Input enable Serial receive data SCI 839 www DataSheet4U com ...

Page 847: ... 4 and 5 Write to P9DDR Write to port 9 Read port 9 WP9D Reset Q D R C P9 DDR n WP9 Reset Q D R C P9 DR n RP9 P9n Internal data bus SCI Clock input enable Clock output enable Clock output Clock input Interrupt controller or input IRQ4 IRQ5 840 www DataSheet4U com ...

Page 848: ...PA RPA n 0 and 1 Write to PADDR Write to port A Read port A PAn WPAD Reset Q D R C PA DDR n Reset Q D R C PA DR n RPA WPA Internal data bus TPC output enable TPC Next data Output trigger Output enable Transfer end output DMA controller Counter clock input ITU 841 www DataSheet4U com ...

Page 849: ... 3 Write to PADDR Write to port A Read port A PAn RPA WPA WPAD Reset Q D R C PA DDR n Reset Q D R C PA DR n Internal data bus TPC output enable TPC Next data Output trigger Output enable Compare match output Input capture Counter clock input ITU 842 www DataSheet4U com ...

Page 850: ... standby Software standby External bus released Reset PRA WPA Q D R C PAnDDR Reset Q D R C PAnDR Internal address bus Internal data bus Bus controller TPC ITU Chip select enable TPC output enable Next data Output trigger Output enable Compare match output Input capture Address output enable CS4 CS5 CS6 output 843 www DataSheet4U com ...

Page 851: ...AD Hardware standby Software standby External bus released Reset PRA WPA Q D R C PA7DDR Reset Q D R C PA7DR Internal address bus Internal data bus Bus controller TPC ITU TPC output enable Next data Output trigger Output enable Compare match output Input capture Address output enable 844 www DataSheet4U com ...

Page 852: ...o PB3 PBn WPBD WPB RPB n 0 to 3 Write to PBDDR Write to port B Read port B Reset Q D R C PB DDR n WPBD Reset Q D R C PB DR n WPB RPB Internal data bus TPC output enable TPC Next data Output trigger Output enable Compare match output Input capture ITU 845 www DataSheet4U com ...

Page 853: ... WPBD WPB RPB n 4 and 5 Write to PBDDR Write to port B Read port B WPB RPB Reset Q D R C PB DDR n WPBD Reset Q D R C PB DR n Internal data bus TPC output enable Next data Output trigger Output enable Compare match output TPC ITU 846 www DataSheet4U com ...

Page 854: ...Reset Q D R C PB DDR Q D R C PB DR 6 RPB WPB DMAC DREQ0 input TPC Bus controller WPBD WPB RPB Write to PBDDR Write to port B Read port B TPC output enable Next data Output trigger Chip select enable CS7 outpu Internal data bus 6 PB6 847 www DataSheet4U com ...

Page 855: ...7 WPBD Reset Reset Q D R C PB DDR Q D R C PB DR 7 RPB WPB DMAC TPC WPBD WPB RPB Write to PBDDR Write to port B Read port B TPC output enable Next data Output trigger Internal data bus 7 ADTRG input A D converter DREQ1 input 848 www DataSheet4U com ...

Page 856: ...DR 1 7 T T keep I O port P27 to P20 1 to 4 L T T T A15 to A8 5 6 T T keep T Input port DDR 0 T T A15 to A8 DDR 1 7 T T keep I O port P37 to P30 1 to 6 T T T T D15 to D8 7 T T keep I O port P47 to P40 1 to 6 8 bit bus T T keep keep I O port 16 bit bus T T T T D7 to D0 7 T T keep I O port Legend H High L Low T High impedance state keep Input pins are in the high impedance state output pins maintain ...

Page 857: ... 1 7 T T keep I O port P62 1 to 6 T T keep L I O port BRLE 0 BRLE 0 H or BACK BRLE 1 BRLE 1 7 T T keep I O port P66 to P63 1 to 6 H 3 T T T AS RD HWR LWR 7 T T keep I O port P77 to P70 1 to 7 T T T T Input port P80 1 to 6 T T keep keep I O port RFSHE 0 RFSHE 0 RFSHE 0 RFSH H or RFSH RFSHE 1 RFSHE 1 RFSHE 1 7 T T keep I O port Legend H High L Low T High impedance state keep Input pins are in the hi...

Page 858: ...ess keep keep output otherwise otherwise I O port otherwise 1 2 5 7 T 4 T keep keep 1 I O port PA7 3 4 6 L 4 T T T A20 1 2 5 7 T T keep keep 1 I O port PB7 PB5 to 1 to 7 T T keep keep 1 I O port PB0 PB6 3 4 6 T T H H CS7 CS output CS output CS output keep keep I O port otherwise otherwise otherwise 1 2 5 7 T T keep keep 1 I O port Legend H High L Low T High impedance state keep Input pins are in t...

Page 859: ...impedance state The address bus is initialized to the low output level 0 5 state after the low level of RES is sampled Sampling of RES takes place at the fall of the system clock ø Figure D 1 Reset during Memory Access Reset during T1 State Access to external address ø Address bus CS0 AS RD read access HWR LWR Data bus I O port RES write access write access H 000000 High impedance High impedance H...

Page 860: ...ce state The address bus is initialized to the low output level 0 5 state after the low level of RES is sampled The same timing applies when a reset occurs during a wait state TW Figure D 2 Reset during Memory Access Reset during T2 State ø Address bus CS0 RD read access HWR LWR Data bus I O port RES AS H 000000 High impedance High impedance High impedance Internal reset signal Access to external ...

Page 861: ...pedance state The address bus outputs are held during the T3 state The same timing applies when a reset occurs in the T2 state of an access cycle to a two state access area Figure D 3 Reset during Memory Access Reset during T3 State ø Address bus CS0 RD read access HWR LWR Data bus I O port RES AS High impedance High impedance High impedance Internal reset signal Access to external address T1 T2 T...

Page 862: ... goes low as shown below RES must remain low until STBY goes low minimum delay from STBY low to RES high 0 ns 2 To retain RAM contents with the RAME bit cleared to 0 in SYSCR or when RAM contents do not need to be retained RES does not have to be driven low as in 1 Timing of Recovery from Hardware Standby Mode Drive the RES signal low approximately 100 ns before STBY goes high 855 t1 10tcyc t2 0 n...

Page 863: ... version HD6433048F HD6433048 F 100 pin QFP FP 100B 3 V HD6433048VTF HD6433048 VTF 100 pin TQFP version TFP 100B HD6433048VF HD6433048 VF 100 pin QFP FP 100B Flash 5 V HD64F3048TF HD64F3048TF 100 pin TQFP memory version TFP 100B version HD64F3048F HD64F3048F 100 pin QFP FP 100B 3 V HD64F3048VTF HD64F3048VTF 100 pin TQFP version TFP 100B HD64F3048VF HD64F3048VF 100 pin QFP FP 100B H8 3047 Mask 5 V ...

Page 864: ...100 pin QFP FP 100B 3 V HD6433045VTF HD6433045 VTF 100 pin TQFP version TFP 100B HD6433045VF HD6433045 VF 100 pin QFP FP 100B H8 3044 Mask 5 V HD6433044TF HD6433044 TF 100 pin TQFP ROM version TFP 100B version HD6433044F HD6433044 F 100 pin QFP FP 100B 3 V HD6433044VTF HD6433044 VTF 100 pin TQFP version TFP 100B HD6433044VF HD6433044 VF 100 pin QFP FP 100B Note in mask ROM versions is the ROM code...

Page 865: ... the TFP 100B package dimensions Unit mm Figure G 1 Package Dimensions FP 100B 858 0 10 16 0 0 3 1 0 0 5 0 2 16 0 0 3 3 05 Max 75 51 50 26 1 25 76 100 14 0 8 0 5 0 08 M 0 22 0 05 2 70 0 17 0 05 0 12 0 13 0 12 1 0 0 20 0 04 0 15 0 04 Dimension including the plating thickness Base material dimension www DataSheet4U com ...

Page 866: ...P 100B 859 16 0 0 2 14 0 08 0 10 0 5 0 1 16 0 0 2 0 5 0 10 0 10 1 20 Max 0 17 0 05 0 8 75 51 1 25 76 100 26 50 M 0 22 0 05 1 0 1 00 1 0 0 20 0 04 0 15 0 04 Dimension including the plating thickness Base material dimension www DataSheet4U com ...

Page 867: ...ate 1st Edition January 1995 3nd Edition October 1997 Published by Semiconductor and IC Div Hitachi Ltd Edited by Technical Documentation Center Hitachi Microcomputer System Ltd Copyright Hitachi Ltd 1995 All rights reserved Printed in Japan www DataSheet4U com ...

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