Table 1-3 Pin Functions (cont)
Type
Symbol
Pin No.
I/O
Name and Function
System control
RES
63
Input
Reset input: When driven low, this pin resets
the chip
RESO
10
Output Reset output: Outputs a reset signal to
external devices
(RESO/V
PP
)
Also used as a power supply for on-board
programming of the flash memory version.
STBY
62
Input
Standby: When driven low, this pin forces
a transition to hardware standby mode
BREQ
59
Input
Bus request: Used by an external bus master
to request the bus right
BACK
60
Output Bus request acknowledge: Indicates that the
bus has been granted to an external bus
master
Interrupts
NMI
64
Input
Nonmaskable interrupt: Requests a
nonmaskable interrupt
IRQ
5
to
17, 16,
Input
Interrupt request 5 to 0: Maskable interrupt
IRQ
0
90 to 87
request pins
Address bus
A
23
to A
0
97 to 100, Output Address bus: Outputs address signals
56 to 45,
43 to 36
Data bus
D
15
to D
0
34 to 23,
Input/
Data bus: Bidirectional data bus
21 to 18
output
Bus control
CS
7
to CS
0
8, 97 to 99, Output Chip select: Select signals for areas 7 to 0
88 to 91
AS
69
Output Address strobe: Goes low to indicate valid
address output on the address bus
RD
70
Output Read: Goes low to indicate reading from the
external address space
HWR
71
Output High write: Goes low to indicate writing to the
external address space; indicates valid data on
the upper data bus (D
15
to D
8
).
LWR
72
Output Low write: Goes low to indicate writing to the
external address space; indicates valid data on
the lower data bus (D
7
to D
0
).
WAIT
58
Input
Wait: Requests insertion of wait states in bus
cycles during access to the external address
space
11
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