Hitachi H8/3044, Hardware Manual

Page: 692 / 867

Table 21-12 Bus Timing (cont)
Condition A: V
CC
= 2.7 V to 5.5 V, AV
CC
= 2.7 V to 5.5 V, V
REF
= 2.7 V to AV
CC
,
V
SS
= AV
SS
= 0 V, ø = 1 MHz to 8 MHz, T
a
= –20°C to +75°C (regular
specifications), T
a
= –40°C to +85°C (wide-range specifications)
Condition C: V
CC
= 5.0 V ± 10%, AV
CC
= 5.0 V ± 10%, V
REF
= 4.5 V to AV
CC
,
V
SS
= AV
SS
= 0 V, ø = 1 MHz to 16 MHz, T
a
= –20°C to +75°C (regular
specifications), T
a
= –40°C to +85°C (wide-range specifications)
Condition A Condition C
8 MHz 16 MHz
Test
Item Symbol Min Max Min Max Unit Conditions
Write data delay time t
WDD
— 75 — 60 ns Figure 21-7
Write data setup time 1 t
WDS1
60 — 15 — Figure 21-8
Write data setup time 2 t
WDS2
5 — –5 —
Write data hold time t
WDH
25 — 20 —
Read data access time 1 t
ACC1
*
— 120 — 60
Read data access time 2 t
ACC2
*
— 240 — 120
Read data access time 3 t
ACC3
*
— 70 — 30
Read data access time 4 t
ACC4
*
— 180 — 95
Precharge time t
PCH
*
85 — 45 —
Wait setup time t
WTS
40 — 25 — ns Figure 21-9
Wait hold time t
WTH
10 — 5 —
Bus request setup time t
BRQS
40 — 40 — ns Figure 21-21
Bus acknowledge delay time 1 t
BACD1
— 60 — 30
Bus acknowledge delay time 2 t
BACD2
— 60 — 30
Bus-floating time t
BZD
— 70 — 40
Note: At 8 MHz, the times below depend as indicated on the clock cycle time.
t
ACC1
= 1.5
×
t
CYC
– 68 (ns) t
WSW1
= 1.0
×
t
CYC
– 40 (ns)
t
ACC2
= 2.5
×
t
CYC
– 73 (ns) t
WSW2
= 1.5
×
t
CYC
– 38 (ns)
t
ACC3
= 1.0
×
t
CYC
– 55 (ns) t
PCH
= 1.0
×
t
CYC
– 40 (ns)
t
ACC4
= 2.0
×
t
CYC
– 70 (ns)
At 16 MHz, the times below depend as indicated on the clock cycle time.
t
ACC1
= 1.5
×
t
CYC
– 34 (ns) t
WSW1
= 1.0
×
t
CYC
– 28 (ns)
t
ACC2
= 2.5
×
t
CYC
– 37 (ns) t
WSW2
= 1.5
×
t
CYC
– 29 (ns)
t
ACC3
= 1.0
×
t
CYC
– 33 (ns) t
PCH
= 1.0
×
t
CYC
– 28 (ns)
t
ACC4
= 2.0
×
t
CYC
– 30 (ns)
684
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