Hitachi H8/3044, Hardware Manual

Page: 678 / 867

Table 21-7 Timing of On-Chip Supporting Modules
Condition A: V
CC
= 2.7 V to 5.5 V, AV
CC
= 2.7 V to 5.5 V, V
REF
= 2.7 V to AV
CC
,
V
SS
= AV
SS
= 0 V, ø = 1 MHz to 8 MHz, T
a
= –20°C to +75°C (regular
specifications), T
a
= –40°C to +85°C (wide-range specifications)
Condition B: V
CC
= 3.15 V to 5.5 V, AV
CC
= 3.15 V to 5.5 V, V
REF
= 3.15 V to AV
CC
,
V
SS
= AV
SS
= 0 V, ø = 1 MHz to 13 MHz, T
a
= –20°C to +75°C (regular
specifications), T
a
= –40°C to +85°C (wide-range specifications)
Condition C: V
CC
= 5.0 V ± 10%, AV
CC
= 5.0 V ± 10%, V
REF
= 4.5 V to AV
CC
,
V
SS
= AV
SS
= 0 V, ø = 1 MHz to 18 MHz, T
a
= –20°C to +75°C (regular
specifications), T
a
= –40°C to +85°C (wide-range specifications)
Condition A Condition B Condition C
8 MHz 13 MHz 16 MHz 18 MHz
Item Symbol Min Max Min Max Min Max Min Max Unit
DMAC
DREQ
setup t
DRQS
40 — 40 — 30 — 30 — ns Figure 21-30
time
DREQ
hold t
DRQH
10 — 10 — 10 — 10 —
time
TEND
delay t
TED1
— 100 — 100 — 50 — 50 Figure 21-28,
time 1 Figure 21-29
TEND
delay t
TED2
— 100 — 100 — 50 — 50
time 2
ITU Timer output t
TOCD
— 100 — 100 — 100 — 100 ns Figure 21-24
delay time
Timer input t
TICS
50 — 50 — 50 — 50 —
setup time
Timer clock t
TCKS
50 — 50 — 50 — 50 — Figure 21-25
input setup time
Single t
TCKWH
1.5 — 1.5 — 1.5 — 1.5 — t
CYC
edge
Both t
TCKWL
2.5 — 2.5 — 2.5 — 2.5 —
edges
SCI Asyn- t
SCYC
4 — 4 — 4 — 4 — t
CYC
Figure 21-26
chronous
Syn- t
SCYC
6 — 6 — 6 — 6 —
chronous
Input clock rise t
SCKr
— 1.5 — 1.5 — 1.5 — 1.5
time
Input clock fall t
SCKf
— 1.5 — 1.5 — 1.5 — 1.5
time
Input clock t
SCKW
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t
SCYC
pulse width
Test
Conditions
Timer
clock
pulse
width
Input
clock
cycle
670
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