18.5.2 Erase Block Register 1
Erase block register 1 (EBR1) is an eight-bit register that designates large flash-memory blocks
for programming and erasure. EBR1 is initialized to H'00 by a reset, in the standby modes, when
12 V is applied to V
PP
while the V
PP
E bit is 0, and when 12 V is not applied to V
PP
. When a bit
in EBR1 is set to 1, the corresponding block is selected and can be programmed and erased.
Figure 18-8 shows a block map.
Note:
*
The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled). In modes
1, 2, 3, and 4 (on-chip flash memory disabled), this register cannot be modified and is
always read as H'FF.
Bits 7 to 0—Large Block 7 to 0 (LB7 to LB0): These bits select large blocks (LB7 to LB0) to be
programmed and erased.
Bits 7 to 0
LB7 to LB0
Description
0
Block LB7 to LB0 is not selected
(Initial value)
1
Block LB7 to LB0 is selected
Bit
Initial value
R/W
7
0
LB3
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LB6
LB5
LB4
LB2
LB1
LB0
*
*
*
*
*
*
*
*
LB7
R/W
*
577
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