Table 9-1 Port Functions (cont)
Port
Description
Pins
Mode 1 Mode 2 Mode 3 Mode 4 Mode 5
Mode 6
Mode 7
Port B
PB
5
/TP
13
/
TPC output (TP
13
to TP
8
), ITU input and output (TOCXB
4
, TOCXA
4
,
TOCXB
4
,
TIOCB
4
, TIOCA
4
, TIOCB
3
, TIOCA
3
), and generic input/output
PB
4
/TP
12
/
TOCXA
4
,
PB
3
/TP
11
/TIOCB
4
,
PB
2
/TP
10
/TIOCA
4
,
PB
1
/TP
9
/TIOCB
3
,
PB
0
/TP
8
/TIOCA
3
9.2 Port 1
9.2.1 Overview
Port 1 is an 8-bit input/output port with the pin configuration shown in figure 9-1. The pin
functions differ between the expanded modes with on-chip ROM disabled, expanded modes with
on-chip ROM enabled, and single-chip mode. In modes 1 to 4 (expanded modes with on-chip
ROM disabled), they are address bus output pins (A
7
to A
0
).
In modes 5 and 6 (expanded modes with on-chip ROM enabled), settings in the port 1 data
direction register (P1DDR) can designate pins for address bus output (A
7
to A
0
) or generic input.
In mode 7 (single-chip mode), port 1 is a generic input/output port.
When DRAM is connected to area 3, A
7
to A
0
output row and column addresses in read and write
cycles. For details see section 7, Refresh Controller.
Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
Figure 9-1 Port 1 Pin Configuration
Port 1
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
7
6
5
4
3
2
1
0
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
7
6
5
4
3
2
1
0
Port 1 pins
Mode 7
Modes 1 to 4
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
7
6
5
4
3
2
1
0
Modes 5 and 6
7
6
5
4
3
2
1
0
• 8-bit I/O port
• Can drive LEDs
• PB
3
to PB
0
have Schmitt
inputs
246
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