8.4.8 DMAC Bus Cycle
Figure 8-13 shows an example of the timing of the basic DMAC bus cycle. This example shows a
word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the
DMAC gets the bus from the CPU, after one dead cycle (T
d
), it reads from the source address and
writes to the destination address. During these read and write operations the bus is not released
even if there is another bus request. DMAC cycles comply with bus controller settings in the same
way as CPU cycles.
Figure 8-13 DMA Transfer Bus Timing (Example)
ø
RD
HWR
LWR
T
1
T
2
T
1
T
2
T
d
T
1
T
2
T
1
T
2
T
3
T
1
T
2
T
3
T
1
T
2
T
1
T
2
CPU cycle
DMAC cycle (word transfer)
CPU cycle
Source
address
Destination address
Address
bus
225
www.DataSheet4U.com
