Figure 8-19 Timing of Multiple-Channel Operations
8.4.10 External Bus Requests, Refresh Controller, and DMAC
During a DMA transfer, if the bus right is requested by an external bus request signal (
BREQ
) or
by the refresh controller, the DMAC releases the bus after completing the transfer of the current
byte or word. If there is a transfer request at this point, the DMAC requests the bus right again.
Figure 8-20 shows an example of the timing of insertion of a refresh cycle during a burst transfer
on channel 0.
Figure 8-20 Bus Timing of Refresh Controller and DMAC
ø
RD
T
1
T
2
T
1
T
2
T
d
T
1
T
2
T
1
T
2
T
1
T
2
T
d
T
1
T
2
T
1
T
2
,
DMAC cycle
(channel 1)
CPU
cycle
DMAC cycle
(channel 0A)
CPU
cycle
DMAC cycle
(channel 1)
Address
bus
HWR
LWR
ø
RD
HWR LWR
,
T
1
T
2
T
1
T
2
T
1
T
2
T
1
T
2
T
1
T
2
T
d
T
1
T
2
T
1
T
2
T
1
T
2
DMAC cycle (channel 0)
DMAC cycle (channel 0)
Refresh
cycle
Address
bus
232
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