4-18
888-2586-001
9/15/06
WARNING: Disconnect primary power prior to servicing.
Platinum Z16HD+
Section 4 Overall System Theory
The gate control voltage (Vg) is -18V to turn the amplifier off (or mute), and 0V to turn
the amplifier fully on.
In the Backup FM (using an analog exciter) mode, the variable APC voltage is
applied to the IPA gates for power level control.
This APC Level control line originates on the Life Support Board and is controlled by
the APC loop on the Master Controller Board. APC loop corrections, foldback, or
pressing the RAISE and LOWER controls on the front of the transmitter will vary the
APC voltage raising or lowering transmitter power.
4.4.4.1.3 PA Circuit Continued
The MOSFET outputs are combined in T2, a 1:4 transformer as shown in Figure 4-6.
C19 and C20 fine-match the 50 ohm load impedance at the PA output to the output
impedance of T2. The +52Vdc or VD (Drain Voltage) from the main power supply
enters at location C-1 and is decoupled and filtered by C11, C12, C13, C14, C16, C24,
C29, C30, C33, L1 and L2. A special mention to capacitor C11. It is a 100uF
electrolytic capacitor, that if connected abruptly to the Vd supply, it will create some
arching to the DC connection, that could eventually destroy it. To avoid the formation
of pitting in the DC connection, and still provide a hot-pluggable PA, the Vd line is fully
engaged only after capacitor C11 has been pre-charged. Resistor R14 engages first and
charges capacitor C11 to a minimum voltage of 90% its final value. This timing
happens during the PA plug-in travel. Once the capacitor has been charged, then R14 is
shorted out and the Vd line is allowed to connect solidly to the Vd supply.
The DC voltage reaches the drain of MOSFETs Q1 and Q2 through the center tap of
T2’s primary winding. The advantage of this method is to allow direct DC connection to
the MOSFETs and have an AC RF output through the coax without the need for a
blocking capacitor.
Figure 4-6 PA Simplified Block Diagram
Summary of Contents for Platinum Z16HD+
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