GD32L23x User Manual
631
6:0
USBDAR[6:0]
USBD device address
After bus reset, the address is reset to
0x00. If the enable bit is set, the device will respond on packets
for function address DEV_ADDR
27.7.5.
USBD buffer address register (USBD_BADDR)
Address offset: 0x50
Reset value: 0x0000
This register can be accessed by half-word (16-bit) or word (32-bit)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BAR[12:0]
Reserved
rw
Bits
Fields
Descriptions
15:3
BAR[12:0]
Buffer address
Start address of the allocation buffer(512byte on-chip SRAM), used for buffer
descriptor table, packet memory
2:0
Reserved
Must be kept at reset value.
27.7.6.
USBD endpoint x control and status register (USBD_EPxCS), x=[0..7]
Address offset: 0x00 to 0x1C
Reset value: 0x0000
This register can be accessed by half-word (16-bit) or word (32-bit)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RX_ST
RX_DTG
RX_STA[1:0]
SETUP
EP_CTL[1:0]
EP_KCTL
TX_ST
TX_DTG
TX_STA[1:0]
EP_ADDR[3:0]
rc_w0
t
t
r
rw
rw
rc_w0
t
t
rw
Bits
Fields
Descriptions
15
RX_ST
Reception successful transferred
Set by hardware when a successful OUT/SETUP transaction complete
Cleared by software by writing 0
14
RX_DTG
Reception data PID toggle
This bit represent the toggle data bit (0=DATA0,1=DATA1)for non-isochronous
endpoint
Used to implement the flow control for double-buffered endpoint
Used to swap buffer for isochronous endpoint
13:12
RX_STA[1:0]
Reception status bits
