GD32L23x User Manual
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27.4.
Signal description
Table 27-1. USBD signal description
I/O port
Type
Description
VBUS
Input
Bus power port
DM
Input/Output
Differential data line - port
DP
Input/Output
Differential data line + port
Note:
As soon as the USBD is enabled, these pins are connected to the USBD internal
transceiver automatically.
27.5.
Clock configuration
According to the USB standard definition, the USB full-speed module adopt fixed 48MHz clock.
It is necessary to configure two clock for using USBD, one is the USB controller clock, its
frequency must be configured to 48MHz, and the other one is the APB1 to USB interface
clock which is also APB1 bus clock, its frequency can be above or below 48MHz.
48MHz clock of USB controller can be generated by dividing MCU internal or external crystal
oscillator by a programmable prescaler, then multiplicating the frequency through PLL.
Regard two frequency division of 16MHz internal oscillator as the input of the PLL, then
6 frequencies doubling the clock.
Regard 8MHz external oscillator as the input of the PLL, then 6 frequencies doubling the
clock.
Note:
Regardless of using internal or external crystal oscillator to generate USB clock, the
clock accuracy must reach ±500ppm. If the accuracy of the USB clock cannot meet the
condition, data transfer may not conform to the requirements of the USB specification, and
even it may cause USB not working directly.
27.6.
Function overview
27.6.1.
USB endpoints
USBD supports 8 USB endpoints that can be individually configured.
Each endpoint supports:
Single/Double buffer (endpoint 0 can’t use double buffer).
One endpoint buffer descriptor.
Programmable buffer starting address and buffer length.
Configurable response to a packet.
Control transfer (endpoint 0 only).
