GD32L23x User Manual
392
000). In this case, the internal clock signal frequency should be at least four times
the
frequency
of the external clock signal.
18.4.12.
Register update
The LPTIMER_CAR register and LPTIMER_CMPV register are updated immediately after
the APB bus write operation, or updated at the end of the current period, when the LPTIMER
has already started. The SHWEN bit controls how to update the LPTIMER_CAR and the
LPTIMER_CMPV registers:
SHWEN = 0: after any write access, the LPTIMER_CAR and the LPTIMER_CMPV
registers are updated immediately.
SHWEN = 1: the LPTIMER_CAR and the LPTIMER_CMPV registers are updated at the
end of the current period, if the timer has been already started.
The APB bus and the LPTIMER core use different clocks, so there is a delay between the
APB write and the time when these values are actually used in the LPTIMER_CAR register
and LPTIMER_CMPV register. Within this delay time period, any additional write into these
registers must be avoided.
The CARUPIF flag and the CMPVUPIF flag in the LPTIMER_INTF register are respectively
used to indicate when the write operation to the LPTIMER_CAR register and the
LPTIMER_CMPV register is completed.
After the LPTIMER_CAR register or the LPTIMER_CMPV register is written, only the previous
write operation is completed, a new write operation to the same register can be performed.
Any continuous write operations performed before the CMPVUPIF flag or the CARUPIF flag
are set respectively will cause unpredictable results.
18.4.13.
Low-power modes
The LPTIMER is able to keep running in all power modes except for Standby mode with its
diversity of clock sources. The LPTIMER has the ability to wake up the system from the low-
power modes, and it is suitable for realizing timeout function with very low power consumption.
Table 18-4. LPTIMER works in low-power modes
Mode
Description
Sleep mode
Operating normally. LPTIMER interrupts cause the device to exit
Sleep mode.
Run2 mode
Operating normally.
Sleep2 mode
Operating normally. LPTIMER interrupts cause the device to exit the
LPSleep mode.
Deep-sleep0 /1 mode
When LPTIMER is clocked by LXTAL or Internal low speed RC
oscillator, LPTIMER interrupts cause the device to exit Deep-sleep
0 /1 mode.
