GD32L23x User Manual
204
13.4.
Function overview
Figure 13-1. ADC module block diagram
ADC_IN0
ADC_IN1
·
· ·
ADC_IN15
GPIO
C
h
a
n
n
e
l
s
e
le
c
to
r
V
REFINT
V
DDA
/V
DD
V
SSA
/V
SS
6~12-bit
Inserted data registers
（
16 bits x 4
）
Regular data registers
（
16 bits
）
Regular
channels
Inserted
channels
Channel Mangement
Trig select
E
X
T
I_
11
TI
M
E
R
8
_
CH
0
TI
M
E
R
8
_
CH
1
T
IM
E
R
1
_
CH
1
T
IM
E
R
2
_
T
R
G
O
T
IM
E
R
11
_
CH
0
Trig select
E
X
T
I_
15
T
IM
E
R
8
_
T
R
G
O
TI
M
E
R
1
_
T
R
G
O
T
IM
E
R
2
_
CH
3
T
IM
E
R
11
_
T
R
G
O
Analog
watchdog
A
P
B
B
U
S
EOC
EOIC
watchdog
event
Interrupt
generator
ADC
Interrupt
S
W
R
C
S
T
S
W
IC
S
T
SAR ADC
CLB
self calibration
OVSS[3:0]
OVSR[2:0]
OVSEN
TOVS
V
SENSE
DMA request
Over
sampler
V
BAT
/3
V
SLCD
/3
DRES[1:0]
12, 10, 8, 6 bits
TI
M
E
R
1
_
CH
0
13.4.1.
Calibration (CLB)
The ADC has a foreground calibration feature. During the procedure, the ADC calculates a
calibration factor which is internally applied to the ADC until the next ADC power-off. The
application can not use the ADC until the calibration is completed. The calibration should be
performed before starting A/D conversion. The calibration is initiated by setting the CLB bit to
1. The CLB bit stays at 1 during the calibration sequence. Then it is then cleared by hardware
as soon as the calibration is completed.
When the ADC operating conditions change (such as supply power voltage V
DDA
, temperature
and so on), it is recommended to re-run a calibration cycle.
The internal analog calibration can be reset by setting the RSTCLB bit in ADC_CTL1 register.
Calibration procedure by software:
1.
Ensure ADCON=1;
2.
Delay 14 ADCCLK to wait for ADC stability;
3.
Set RSTCLB (optional);
