GigaDevice Semiconductor GD32L23 Series, User Manual

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GD32L23x User Manual
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Figure 1-1. The structure of the Arm
®
Cortex
®
-M23 processor
Cortex-M23
Processor core
Nested
Vectored
Interrupt
Controller
(NVIC)
Data
Watchpoint
And Trace
(DWT)
Breakpoint
Unit
Bus Matrix
Processor
Romtable
AHB Master
Single-cycle IO
port
IRQ interface
Single Wire
Debug interface
1.2. System architecture
The Bus Matrix is implemented in the GD32L23x devices, which manages the access
arbitration between masters and Round Robin algorithm is used in arbitration. The bus matrix
provides access from a master to a slave, enabling concurrent access and efficient operation
even when several high-speed peripherals work simultaneously. A 32-bit multilayer bus is
implemented in the devices, which enables parallel access paths between multiple masters
and slaves in the system. The multilayer bus consists of an AHB interconnect matrix, tow AHB
bus. The interconnection relationship of the AHB interconnect matrix is shown below. In the
following table, “1” indicates the corresponding master is able to access the corresponding
slave through the AHB interconnect matrix, while the blank means the corresponding master
cannot access the corresponding slave through the AHB interconnect matrix. This
architecture is shown in Table 1-1. Bus Interconnection Matrix .
Table 1-1. Bus Interconnection Matrix
SBUS DMA
FMC
1 1
SRAM0
1 1
AHB1
1 1
AHB2
1 1
SRAM1
1 1
As is shown above, there are two masters connected with the AHB interconnect matrix,
including SBUS and DMA. CPU SBUS connects the system bus of the Cortex
®
-M23 core