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GigaDevice Semiconductor GD32L23 Series, User Manual

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GigaDevice Semiconductor GD32L23 Series User Manual Download Page 331

                                                                                                                   

GD32L23x User Manual

 

331 

 

 

101: Force high. O2CPRE is forced high level. 

110: PWM mode0. When counting up, O0CPRE is active as long as the counter is 

smaller  than  TIMERx_CH0CV  else  inactive.  When  counting  down,  O0CPRE  is 

inactive as long as the counter is larger than TIMERx_CH0CV else active. 

111: PWM mode1. When counting up, O0CPRE is inactive as long as the counter 

is  smaller  than  TIMERx_CH0CV  else  active.  When  counting  down,  O0CPRE  is 

active as long as the counter is larger than TIMERx_CH0CV else inactive. 

When configured in PWM mode, the O2CPRE level changes only when the output 

compare mode switches from “frozen” mode to “PWM” mode or when the result of 

the comparison changes. 

This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 

11 and CH2MS bit-filed is 00(COMPARE MODE). 

3 

CH2COMSEN 

Channel 2 compare output shadow enable 

When  this  bit  is  set,  the  shadow  register  of  TIMERx_CH2CV  register,  which 

updates at each update event will be enabled.   

0: Channel 2 output compare shadow disable 

1: Channel 2 output compare shadow enable 

The PWM mode can be used without validating the shadow register only in single 

pulse mode (SPM bit in TIMERx_CTL0 register is set). 

This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 

11 and CH0MS bit-filed is 00. 

2 

CH2COMFEN 

Channel 2 output compare fast enable 

When  this  bit  is  set,  the  effect  of  an  event  on  the  trigger  in  input  on  the 

capture/compare output will be accelerated if the channel is configured in PWM1 

or PWM2 mode. The output channel will treat an active edge on the trigger input as 

a compare match, and CH2_O is set to the compare level independently from the 

result of the comparison. 

0: Channel 2 output quickly compare disable. The minimum delay from an edge on 

the trigger input to activate CH2_O output is 5 clock cycles. 

1: Channel 2 output quickly compare enable. The minimum delay from an edge on 

the trigger input to activate CH2_O output is 3 clock cycles. 

1:0 

CH2MS[1:0] 

Channel 2 I/O mode selection 

This bit-field specifies the work mode of the channel and the input signal selection. 

This  bit-field  is  writable  only  when  the  channel  is  not  active.  (CH2EN  bit  in 

TIMERx_CHCTL2 register is reset).). 

00: Channel 2 is configured as output 

01: Channel 2 is configured as input, IS2 is connected to CI2FE2 

10: Channel 2 is configured as input, IS2 is connected to CI3FE2 

11: Channel 2 is configured as input, IS2 is connected to ITS. This mode is working 

only if an internal trigger input is selected through TRGS bits in TIMERx_SMCFG 

register. 

Summary of Contents for GD32L23 Series

Page 1: ...GigaDevice Semiconductor Inc GD32L23x Arm Cortex M23 32 bit MCU User Manual Revision 1 0 Oct 2021 ...

Page 2: ... sources selection register 1 SYSCFG_EXTISS1 36 1 6 4 EXTI sources selection register 2 SYSCFG_EXTISS2 38 1 6 5 EXTI sources selection register 3 SYSCFG_EXTISS3 39 1 6 6 IRQ Latency register SYSCFG_CPU_IRQ_LAT 40 1 7 Device electronic signature 41 1 7 1 Memory density information 41 1 7 2 Unique device ID 96 bits 41 2 Flash memory controller FMC 43 2 1 Overview 43 2 2 Characteristics 43 2 3 Functi...

Page 3: ... 4 10 Product ID register FMC_PID 63 3 Power management unit PMU 64 3 1 Overview 64 3 2 Characteristics 64 3 3 Function overview 65 3 3 1 Battery backup domain 65 3 3 2 VDD VDDA power domain 66 3 3 3 1 1V power domain 69 3 3 4 Power saving modes 70 3 4 Register definition 75 3 4 1 Control register 0 PMU_CTL0 75 3 4 2 Control and status register PMU_CS 76 3 4 3 Control register 1 PMU_CTL1 78 3 4 4 ...

Page 4: ... 18 Low power bandgap mode register RCU_LPB 116 5 Clock trim controller CTC 117 5 1 Overview 117 5 2 Characteristics 117 5 3 Function overview 117 5 3 1 REF sync pulse generator 118 5 3 2 CTC trim counter 118 5 3 3 Frequency evaluation and automatically trim process 119 5 3 4 Software program guide 120 5 4 Register definition 122 5 4 1 Control register 0 CTC_CTL0 122 5 4 2 Control register 1 CTC_C...

Page 5: ...tput mode register GPIOx_OMODE x A D F 144 7 4 3 Port output speed register GPIOx_OSPD x A D F 146 7 4 4 Port pull up down register GPIOx_PUD x A D F 148 7 4 5 Port input status register GPIOx_ISTAT x A D F 150 7 4 6 Port output control register GPIOx_OCTL x A D F 150 7 4 7 Port bit operate register GPIOx_BOP x A D F 151 7 4 8 Port configuration lock register GPIOx_LOCK x A D F 151 7 4 9 Alternate...

Page 6: ...169 10 4 4 Address generation 170 10 4 5 Circular mode 170 10 4 6 Memory to memory mode 170 10 4 7 Channel configuration 170 10 4 8 Interrupt 171 10 4 9 DMA request mapping 171 10 5 Register definition 172 10 5 1 Interrupt flag register DMA_INTF 172 10 5 2 Interrupt flag clear register DMA_INTC 172 10 5 3 Channel x control register DMA_CHxCTL 173 10 5 4 Channel x counter register DMA_CHxCNT 175 10...

Page 7: ... overview 195 12 2 1 Switch JTAG or SW interface 195 12 2 2 Pin assignment 195 12 2 3 JTAG daisy chained structure 196 12 2 4 Debug reset 196 12 2 5 JEDEC 106 ID code 196 12 3 Debug hold function overview 197 12 3 1 Debug support for power saving mode 197 12 3 2 Debug support for TIMER LPTIMER I2C RTC WWDGT and FWDGT 197 12 4 Register definition 198 12 4 1 ID code register DBG_ID 198 12 4 2 Contro...

Page 8: ...reshold register ADC_WDLT 226 13 5 9 Regular sequence register 0 ADC_RSQ0 227 13 5 10 Regular sequence register 1 ADC_RSQ1 227 13 5 11 Regular sequence register 2 ADC_RSQ2 228 13 5 12 Inserted sequence register ADC_ISQ 228 13 5 13 Inserted data register x ADC_IDATAx x 0 3 229 13 5 14 Regular data register ADC_RDATA 229 13 5 15 Oversampling control register ADC_OVSAMPCTL 230 13 5 16 Charge control ...

Page 9: ...ristics 257 16 3 Function overview 258 16 3 1 Block diagram 258 16 3 2 Clock source and prescalers 259 16 3 3 Shadow registers introduction 259 16 3 4 Configurable and field maskable alarm 259 16 3 5 Configurable periodic auto wakeup counter 260 16 3 6 RTC initialization and configuration 260 16 3 7 Calendar reading 261 16 3 8 Resetting the RTC 263 16 3 9 RTC shift function 263 16 3 10 RTC referen...

Page 10: ...er RTC_TAMP 286 16 4 17 Alarm 0 sub second register RTC_ALRM0SS 289 16 4 18 Alarm 1 sub second register RTC_ALRM1SS 290 16 4 19 Backup registers RTC_BKPx x 0 4 291 17 Timer TIMERx 292 17 1 General level0 timer TIMERx x 1 2 293 17 1 1 Overview 293 17 1 2 Characteristics 293 17 1 3 Block diagram 293 17 1 4 Function overview 294 17 1 5 TIMERx registers x 1 2 317 17 2 General level1 timer TIMERx x 8 1...

Page 11: ...PTIMER_CTL0 400 18 5 5 Control register 1 LPTIMER_CTL1 404 18 5 6 Compare value register LPTIMER_CMPV 405 18 5 7 Counter auto reload register LPTIMER_CAR 405 18 5 8 Counter register LPTIMER_CNT 406 18 5 9 External input remap register LPTIMER_EIRMP 406 18 5 10 Input high level counter max value register LPTIMER_INHLCMV 407 19 Universal synchronous asynchronous receiver transmitter USART 408 19 1 O...

Page 12: ...ART coherence control register USART_CHC 444 19 4 13 USART receive FIFO control and status register USART_RFCS 445 20 Low power universal asynchronous receiver transmitter LPUART 447 20 1 Overview 447 20 2 Characteristics 447 20 3 Function overview 448 20 3 1 LPUART frame format 449 20 3 2 Baud rate generation 450 20 3 3 LPUART transmitter 451 20 3 4 LPUART receiver 452 20 3 5 Use DMA for data buf...

Page 13: ... DMA for data transfer 498 21 3 13 I2C error and interrupts 499 21 3 14 I2C debug mode 499 21 4 Register definition 500 21 4 1 Control register 0 I2C_CTL0 500 21 4 2 Control register 1 I2C_CTL1 502 21 4 3 Slave address register 0 I2C_SADDR0 504 21 4 4 Slave address register 1 I2C_SADDR1 505 21 4 5 Timing register I2C_TIMING 506 21 4 6 Timeout register I2C_TIMEOUT 507 21 4 7 Status register I2C_STA...

Page 14: ...ration 542 22 9 4 DMA function 545 22 10 I2S interrupts 545 22 10 1 Status flags 545 22 10 2 Error conditions 545 22 11 Register definition 547 22 11 1 Control register 0 SPI_CTL0 547 22 11 2 Control register 1 SPI_CTL1 549 22 11 3 Status register SPI_STAT 551 22 11 4 Data register SPI_DATA 552 22 11 5 CRC polynomial register SPI_CRCPOLY 553 22 11 6 Receive CRC register SPI_RCRC 553 22 11 7 Transm...

Page 15: ... 583 23 9 8 Interrupt flag register CAU_INTF 583 23 9 9 Key registers CAU_KEY0 3 H L 584 23 9 10 Initial vector registers CAU_IV0 1 H L 586 23 9 11 GCM or CCM mode context switch register x CAU_GCMCCMCTXSx x 0 7 588 23 9 12 GCM mode context switch register x CAU_GCMCTXSx x 0 7 588 24 VREF 590 24 1 Overview 590 24 2 Characteristics 590 24 3 Function overview 590 24 4 Register definition 591 24 4 1 ...

Page 16: ...rol Status register CMP0_CS 611 26 4 2 Comparator 1 Control Status register CMP1_CS 613 27 Universal Serial Bus full speed device interface USBD 616 27 1 Overview 616 27 2 Main features 616 27 3 Block diagram 616 27 4 Signal description 617 27 5 Clock configuration 617 27 6 Function overview 617 27 6 1 USB endpoints 617 27 6 2 Operation procedure 620 27 6 3 USB events and interrupts 623 27 6 4 Ope...

Page 17: ..._EPxRBADDR x can be in 0 7 634 27 7 10 USBD endpoint x reception buffer byte count register USBD_EPxRBCNT x can be in 0 7 634 27 7 11 USBD LPM control and status register USBD_LPMCS 635 27 7 12 USBD DP pull up control register USBD_DPC 635 28 Document appendix 637 28 1 List of abbreviations used in registers 637 28 2 List of terms 637 28 3 Available peripherals 637 29 Revision history 638 ...

Page 18: ... 2 Input configuration 139 Figure 7 3 Output configuration 140 Figure 7 4 Analog configuration 140 Figure 7 5 Alternate function configuration 141 Figure 8 1 Block diagram of CRC calculation unit 156 Figure 9 1 TRNG block diagram 161 Figure 10 1 Block diagram of DMA 167 Figure 10 2 Handshake mechanism 169 Figure 10 3 DMA interrupt logic 171 Figure 11 1 Block diagram of DMAMUX 179 Figure 11 2 Synch...

Page 19: ...e logic x 0 1 2 3 303 Figure 17 11 Output compare under three modes 304 Figure 17 12 Timing chart of EAPWM 305 Figure 17 13 Timing chart of CAPWM 306 Figure 17 14 Example of counter operation in encoder interface mode 308 Figure 17 15 Example of encoder interface mode with CI0FE0 polarity inverted 308 Figure 17 16 Restart mode 309 Figure 17 17 Pause mode 310 Figure 17 18 Event mode 310 Figure 17 1...

Page 20: ...ge mode 389 Figure 18 13 Counter operation in decoder mode 1 with non inverted 390 Figure 18 14 Counter operation in decoder mode 1 with non inverted IN1EIF 390 Figure 18 15 Counter operation in decoder mode 1 with non inverted IN0EIF 391 Figure 18 16 Counter operation in decoder mode 1 with non inverted INRFOEIF 391 Figure 18 17 Counter operation in decoder mode 1 with non inverted INHLOEIF 391 F...

Page 21: ...ansmitting when SS 0 486 Figure 21 15 Programming model for slave transmitting when SS 1 487 Figure 21 16 Programming model for slave receiving 488 Figure 21 17 I2C initialization in master mode 489 Figure 21 18 Programming model for master transmitting N 255 490 Figure 21 19 Programming model for master transmitting N 255 491 Figure 21 20 Programming model for master receiving N 255 492 Figure 21...

Page 22: ...timing diagram DTLEN 01 CHLEN 1 CKPL 1 536 Figure 22 31 MSB justified standard timing diagram DTLEN 00 CHLEN 1 CKPL 0 536 Figure 22 32 MSB justified standard timing diagram DTLEN 00 CHLEN 1 CKPL 1 537 Figure 22 33 LSB justified standard timing diagram DTLEN 01 CHLEN 1 CKPL 0 537 Figure 22 34 LSB justified standard timing diagram DTLEN 01 CHLEN 1 CKPL 1 537 Figure 22 35 LSB justified standard timin...

Page 23: ...rd swapping 560 Figure 23 2 DATAM Byte swapping and Bit swapping 561 Figure 23 3 CAU diagram 562 Figure 23 4 DES TDES ECB encryption 563 Figure 23 5 DES TDES ECB decryption 564 Figure 23 6 DES TDES CBC encryption 565 Figure 23 7 DES TDES CBC decryption 566 Figure 23 8 AES ECB encryption 567 Figure 23 9 AES ECB decryption 568 Figure 23 10 AES CBC encryption 569 Figure 23 11 AES CBC decryption 570 F...

Page 24: ...n 168 Table 10 2 interrupt events 171 Table 11 1 Interrupt events 184 Table 11 2 Request multiplexer input mapping 185 Table 11 3 Trigger input mapping 186 Table 11 4 Synchronization input mapping 187 Table 12 1 Pin assignment 196 Table 13 1 ADC internal signals 203 Table 13 2 ADC pins definition 203 Table 13 3 External trigger for regular channels of ADC 213 Table 13 4 External trigger for insert...

Page 25: ...ble 21 5 SMBus with PEC configuration 495 Table 21 6 I2C error flags 499 Table 21 7 I2C interrupt events 499 Table 22 1 SPI signal description 515 Table 22 2 Quad SPI signal description 516 Table 22 3 SPI operation modes 520 Table 22 4 SPI interrupt requests 532 Table 22 5 I2S bitrate calculation formulas 541 Table 22 6 Audio sampling frequency calculation formulas 542 Table 22 7 Direction of I2S ...

Page 26: ...s to developers including A simple architecture that is easy to learn and program Ultra low power energy efficient operation Excellent code density Deterministic high performance interrupt handling Upward compatibility with Cortex M processor family The processor delivers high energy efficiency through a small but powerful instruction set and extensively optimized design providing high end process...

Page 27: ...ultilayer bus is implemented in the devices which enables parallel access paths between multiple masters and slaves in the system The multilayer bus consists of an AHB interconnect matrix tow AHB bus The interconnection relationship of the AHB interconnect matrix is shown below In the following table 1 indicates the corresponding master is able to access the corresponding slave through the AHB int...

Page 28: ...are the two APB buses connected with all of the APB slaves The two APB buses connect with all the APB peripherals APB1 is limited to 32Mhz APB2 is limited to 64Mhz The system architecture of GD32L23x series is shown in the following figure The AHB matrix based on AMBA 5 AHB LITE is a multi layer AHB which enables parallel access paths between multiple masters and slaves in the system Two masters o...

Page 29: ...Fmax 64MHz GPIO Ports A B C D F IRC48M 48MHz SYS Config TIMER8 APB2 F max 64MHz Powered by LDO 1 1 0 9V WWDGT APB1 F max 32MHz TIMER5 6 SPI1 I2S1 I2C0 2 RTC FWDGT PMU TIMER11 TIMER1 2 Powered by VDD VDDA IRC32K 32KHz USART1 LPTIMER C A U DMAMUX LXTAL 32 768KHz SBus DAC0 USBD UART3 4 LPUART VREF CMP0 1 T R N G SRAM Controller SRAM2 16K SBus SBus SLCD CTC 1 3 Memory map Program memory data memory re...

Page 30: ...Reserved 0x5006 0C00 0x5006 0FFF Reserved 0x5006 0800 0x5006 0BFF TRNG 0x5006 0400 0x5006 07FF Reserved 0x5006 0000 0x5006 03FF CAU 0x5005 0400 0x5005 FFFF Reserved 0x5005 0000 0x5005 03FF Reserved 0x5004 0000 0x5004 FFFF Reserved 0x5000 0000 0x5003 FFFF Reserved AHB2 0x4800 1800 0x4FFF FFFF Reserved 0x4800 1400 0x4800 17FF GPIOF 0x4800 1000 0x4800 13FF Reserved 0x4800 0C00 0x4800 0FFF GPIOD 0x480...

Page 31: ...BFF CTC 0x4000 C400 0x4000 C7FF Reserved 0x4000 C000 0x4000 C3FF I2C2 0x4000 9800 0x4000 BFFF Reserved 0x4000 9400 0x4000 97FF LPTIMER 0x4000 8400 0x4000 93FF Reserved 0x4000 8000 0x4000 83FF LPUART 0x4000 7C00 0x4000 7FFF Reserved 0x4000 7800 0x4000 7BFF Reserved 0x4000 7400 0x4000 77FF DAC0 0x4000 7000 0x4000 73FF PMU 0x4000 6400 0x4000 6FFF Reserved 0x4000 6000 0x4000 63FF USBD RAM 512 bytes 0x...

Page 32: ...FF 0x2000 0000 0x2000 0FFF Code 0x1FFF F810 0x1FFF FFFF Reserved 0x1FFF F800 0x1FFF F80F Option bytes 16B 0x1FFF D000 0x1FFF F7FF System memory 10KB 0x1FFF 7200 0x1FFF CFFF Reserved 0x1FFF 7000 0x1FFF 71FF OTP 512B 0x1000 0000 0x1FFF 6FFF Reserved 0x0804 0000 0x0FFF FFFF Reserved 0x0802 0000 0x0803 FFFF Main Flash memory 256KB 0x0801 0000 0x0801 FFFF 0x0800 0000 0x0800 FFFF 0x0001 0000 0x07FF FFFF...

Page 33: ...processor fetches the top of stack value from address 0x0000 0000 and the base address of boot code from 0x0000 0004 in sequence Then it starts executing code from the base address of boot code According to the selected boot source either the main flash memory original memory space beginning at 0x0800 0000 or the system memory original memory space beginning at 0x1FFF D000 is aliased in the boot m...

Page 34: ...gh current capability on the PB9 pin is disabled 1 High current capability on the PB9 pin is enabled and the speed control of the pin is bypassed 18 PB8_HCCE PB8 pin high current capability enable When it is set the PB8 pin can be used to control an infrared LED directly 0 High current capability on the PB8 pin is disabled 1 High current capability on the PB8 pin is enabled and the speed control o...

Page 35: ...etained across all reset events except POR It controls the mapping of either PA9 10 or PA11 12 pin pair on small pin count packages 0 No remap pin pair PA9 10 mapped on the pins 1 Remap pin pair PA11 12 mapped instead of PA9 10 3 2 Reserved Must be kept at reset value 1 0 BOOT_MODE 1 0 Boot mode Bit0 is mapping to the BOOT0 pin the value of bit1 is mapping to the BOOT1 pin x0 Boot from the Main Fl...

Page 36: ...eserved X111 reserved 7 4 EXTI1_SS 3 0 EXTI 1 sources selection X000 PA1 pin X001 PB1 pin X010 PC1 pin X011 PD1 pin X100 reserved X101 PF1 pin X110 reserved X111 reserved 3 0 EXTI0_SS 3 0 EXTI 0 sources selection X000 PA0 pin X001 PB0 pin X010 PC0 pin X011 PD0 pin X100 reserved X101 PF0 pin X110 reserved X111 reserved 1 6 3 EXTI sources selection register 1 SYSCFG_EXTISS1 Address offset 0x0C Reset...

Page 37: ...0 PA7 pin X001 PB7 pin X010 PC7 pin X011 reserved X100 reserved X101 reserved X110 reserved X111 reserved 11 8 EXTI6_SS 3 0 EXTI 6 sources selection X000 PA6 pin X001 PB6 pin X010 PC6 pin X011 PD6 pin X100 reserved X101 reserved X110 reserved X111 reserved 7 4 EXTI5_SS 3 0 EXTI 5 sources selection X000 PA5 pin X001 PB5 pin X010 PC5 pin X011 PD5 pin X100 reserved X101 reserved X110 reserved X111 re...

Page 38: ...11_SS 3 0 EXTI10_SS 3 0 EXTI9_SS 3 0 EXTI8_SS 3 0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 EXTI11_SS 3 0 EXTI 11 sources selection X000 PA11 pin X001 PB11 pin X010 PC11 pin X011 reserved X100 reserved X101 reserved X110 reserved X111 reserved 11 8 EXTI10_SS 3 0 EXTI 10 sources selection X000 PA10 pin X001 PB10 pin X010 PC10 pin X011 reserved X100 reserv...

Page 39: ...0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI15_SS 3 0 EXTI14_SS 3 0 EXTI13_SS 3 0 EXTI12_SS 3 0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 EXTI15_SS 3 0 EXTI 15 sources selection X000 PA15 pin X001 PB15 pin X010 PC15 pin X011 reserved X100 reser...

Page 40: ...reserved X101 reserved X110 reserved X111 reserved 1 6 6 IRQ Latency register SYSCFG_CPU_IRQ_LAT Address offset 0x100 Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IRQ_LATENCY 7 0 rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 IRQ_LATENCY 7 0 IRQ...

Page 41: ...etc 1 7 1 Memory density information Base address 0x1FFF F7E0 The value is factory programmed and can never be altered by user This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRAM_DENSITY 15 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FLASH_DENSITY 15 0 r Bits Fields Descriptions 31 16 SRAM_DENSITY 15 0 SRAM density The value indicates the on chip SRAM...

Page 42: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNIQUE_ID 63 48 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNIQUE_ID 47 32 r Bits Fields Descriptions 31 0 UNIQUE_ID 63 32 Unique device ID Base address 0x1FFF F7F0 The value is factory programmed and can never be altered by user This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNIQUE_ID 95 80 r 15 14 13 12 11 ...

Page 43: ...ock used for user data storage 16B option bytes block for user application requirements Option bytes are uploaded to the option byte control registers when the system is reset Flash security protection to prevent illegal code data access Page erase program protection to prevent unexpected operation Fast program support Low power mode support 2 3 Function overview 2 3 1 Flash memory architecture Th...

Page 44: ...FF 2KB Information block Boot loader area 0x1FFF D000 0x1FFF F7FF 10KB Option bytes block Option bytes 0x1FFF F800 0x1FFF F80F 16B One time program block OTP bytes 0x1FFF_7000 0x1FFF_71FF 512B Note The information block stores the boot loader This block cannot be programmed or erased by user Table 2 3 64KB flash base address and size for flash memory Block Name Address range size bytes Main flash ...

Page 45: ... in the FMC_WS register needs to be configured correctly depend on the AHB clock frequency when reading the flash memory The relation between WSCNT and AHB clock frequency is show as the Table 2 5 The relation between WSCNT and AHB clock frequency Table 2 5 The relation between WSCNT and AHB clock frequency when LDO is 1 1V AHB clock frequency WSCNT configured 32MHz 0 0 wait state added 64MHz 1 1 ...

Page 46: ...fer data 64 bit 32 bit needs at least 2 clocks and 16 bit needs at least 4 clocks In this case pre fetch the data of next double word address from flash memory and store to pre fetch buffer So when the CPU finish the current buffer and need execute the next data the pre fetch buffer hit 2 3 3 Unlock the FMC_CTL register After reset the FMC_CTL register is not accessible in write mode and the LK bi...

Page 47: ...til all the operations have finished by checking the value of the BUSY bit in the FMC_STAT register Read and verify the page using a DBUS access if required When the operation is executed successfully the ENDF bit in the FMC_STAT register is set and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set Note that a correct target page address must be confirmed Otherw...

Page 48: ...ng steps show the mass erase register access sequence Unlock the FMC_CTL register if necessary Check the BUSY bit in the FMC_STAT register to confirm that no flash memory operation is in progress BUSY equals to 0 Otherwise wait until the operation has finished Set the MER bit in the FMC_CTL register if erase entire flash Send the mass erase command to the FMC by setting the START bit in the FMC_CT...

Page 49: ...n the FMC_CTL register is set The software can check the WPERR bit in the FMC_STAT register to detect this condition in the interrupt handler The following figure indicates the mass erase operation flow Figure 2 2 Process of mass erase operation Set the MER bit Is the LK bit is 0 Send the command to FMC by set START bit Start Yes No Unlock the FMC_CTL Is the BUSY bit is 0 Yes No Is the BUSY bit is...

Page 50: ... the FMC_CTL register is set Note that there are some program error need caution The programming operation checks the address if it has been erased or not If the address has not been erased the PGERR bit in the FMC_STAT register will be set Each word can be programmed only one time after erase and before next erase Note that the PG bit must be set before the word half word programming operation Ad...

Page 51: ...efore programming page programming time is shortened At the same time high voltage rise and fall times are avoided for each word Only the main memory can be programmed in fast programming mode The following steps show the register access sequence of the fast programming operation Check the row 32 double word in flash to confirm all data in flash is all FF Unlock the FMC_CTL register if necessary C...

Page 52: ...these conditions a flash operation error interrupt will be triggered by the FMC if the ERIE bit in the FMC_CTL register is set The software can check the PGAERR WPERR bit in the FMC_STAT register to detect which condition occurred in the interrupt handler The following figure displays the word programming operation flow Figure 2 4 Process of fast program operation Set the PG bit Is the LK bit is 0...

Page 53: ...e the software must first check whether the flash memory is FF and a row must not be programmed twice or more between two erase operations If program one row twice or more between two erase operations unpredictable result may occur 2 3 8 OTP programming The OTP programming method is same as the main flash programming The OTP block can only be programed once and cannot be erased Note It must ensure...

Page 54: ...ramming Wait until all the operations have been finished by checking the value of the BUSY bit in the FMC_STAT register Read and verify the flash memory if required using a DBUS access When the operation is executed successfully the ENDF bit in the FMC_STAT register is set and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set Note that there programming errors m...

Page 55: ... 0 0x1fff f806 DATA 15 8 user defined data bit 15 to 8 0x1fff f807 DATA_N 15 8 DATA complement value bit 15 to 8 0x1fff f808 WP 7 0 Page erase program protection bit 7 to 0 0 protection active 1 unprotected 0x1fff f809 WP_N 7 0 WP complement value bit 7 to 0 0x1fff f80a WP 15 8 Page erase program protection bit 15 to 8 0x1fff f80b WP_N 15 8 WP complement value bit 15 to 8 0x1fff f80c WP 23 16 Page...

Page 56: ...r the low security protection the main flash can only be accessed by user code In debug mode boot from SRAM or boot loader mode all operations to main flash is forbidden If a read operation to main flash in debug mode boot from SRAM or boot loader mode a bus error will be generated If a program erase operation to main flash in debug mode boot from SRAM or boot from boot loader mode the WPERR bit i...

Page 57: ...CU enter deep sleep mode or RUN_SLP bit is set 0 Flash enter power down mode 1 Flash enter sleep mode 13 RUN_SLP Flash enter sleep power down mode set by SLEEP_SLP bit or IDLE mode during MCU run low power run mode The flash memory can be put in sleep power down mode only when the code is executed from RAM This bit is write protected by FMC_SLPKEY 0 Flash is in IDLE mode or wakeup from sleep power...

Page 58: ...0 19 18 17 16 KEY 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY 15 0 w Bits Fields Descriptions 31 0 KEY 31 0 FMC_CTL unlock register These bits are only be written by software Write KEY 31 0 with keys to unlock FMC_CTL register 2 4 3 Option byte unlock key register FMC_OBKEY Address offset 0x08 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 ...

Page 59: ...reset value 5 ENDF End of operation flag bit When the operation executed successfully this bit is set by hardware The software can clear it by writing 1 4 WPERR Erase Program protection error flag bit When erase program on protected pages this bit is set by hardware The software can clear it by writing 1 3 PGAERR Program alignment error flag bit This bit is set by hardware when DBUS write data is ...

Page 60: ...et value 10 ERRIE Error interrupt enable bit This bit is set or cleared by software 0 no interrupt generated by hardware 1 error interrupt enable 9 OBWEN Option byte erase program enable bit This bit is set by hardware when right sequence written to the FMC_OBKEY register This bit can be cleared by software 8 FSTPG Main flash fast program command bit This bit is set or clear by software 0 no effec...

Page 61: ...flash program command bit This bit is set or clear by software 0 no effect 1 main flash program command Note This register should be reset after the corresponding flash operation completed 2 4 6 Address register FMC_ADDR Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR 31 16 w 15 14 13 12 11 10 9 8 7 6 ...

Page 62: ...s security protection code 0 no protection 1 protection 0 OBERR Option bytes read error bit This bit is set by hardware when the option bytes and its complement byte do not match then the option bytes is set to 0xFF 2 4 8 Erase Program protection register FMC_WP Address offset 0x20 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ...

Page 63: ...o unlock RUN_SLP bit in FMC_WS register SLPKEY1 0x04152637 SLPKEY2 0xBCAD9E8F 2 4 10 Product ID register FMC_PID Address offset 0x100 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PID 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PID 15 0 r Bits Field Descriptions 31 0 PID 31 0 Product reserved ID code register These bits ar...

Page 64: ... of the VDD domain is supplied directly by VDD An embedded LDO in the VDD VDDA domain is used to supply the 1 1V domain power A power switch is implemented for the Backup domain It can be powered from the VBAT voltage when the main VDD supply is shut down 3 2 Characteristics Three power domains VBAK VDD VDDA and 1 1V power domains Ten power saving modes Run Run1 Run2 Sleep Sleep1 Sleep2 Deep sleep...

Page 65: ...rives Backup Domain power supply for RTC unit LXTAL oscillator and BPOR and three pads including PC13 to PC15 In order to ensure the content of the Backup domain registers and the RTC supply when VDD supply is shut down VBAT pin can be connected to an optional standby voltage supplied by a battery or by another source The power switch is controlled by the Power Down Reset circuit in the VDD VDDA d...

Page 66: ...C15 should not exceed 2MHz when they are in output mode maximum load 30pF The external VBAT battery can be charged by the VDD through an internal resistor The charging resistor can be selected by configuring the VCRSEL bit in PMU_CTL0 register A 5 kOhms resistor or a 1 5 kOhms resistor can be selected for external VBAT battery charing The external VBAT battery charing is enabled by setting the VCE...

Page 67: ...d 40mV Figure 3 2 Waveform of the POR PDR VDD VDDA VPOR tRSTTEMPO 2ms Power Reset Active Low t VPDR 40mV Vhyst The BOR circuit is used to detect VDD VDDA and generate the power reset signal which resets the whole chip except the Backup domain when the supply voltage is lower than the specified threshold which defined in the BOR_TH bits in option bytes Notice that the POR PDR circuit is always impl...

Page 68: ...D threshold This event is internally connected to the EXTI line 16 and can generate an interrupt if it is enabled through the EXTI registers Figure 3 4 Waveform of the LVD threshold shows the relationship between the LVD threshold and the LVD output LVD interrupt signal depends on EXTI line 16 rising or falling edge configuration The following figure shows the relationship between the supply volta...

Page 69: ... the APB interfaces for the Backup domain and the VDD VDDA domain etc are located in this power domain Once the 1 1V is powered up the POR will generate a reset sequence on the 1 1V power domain If need to enter the expected power saving mode the associated control bits must be configured Then once a WFI Wait for Interrupt or WFE Wait for Event instruction is executed the device will enter an expe...

Page 70: ...p sleep2 mode 3 3 4 Power saving modes After a system reset or a power reset the GD32L23x MCU operates at full function and all power domains are active Users can achieve lower power consumption through slowing down the system clocks HCLK PCLK1 and PCLK2 or gating the clocks of the unused peripherals Besides ten power saving modes are provided to achieve even lower power consumption they are Run R...

Page 71: ...guring the LDOVS bits in PMU_CTL0 Sleep2 mode The Sleep2 mode is corresponding to the SLEEPING mode of the Cortex M23 When in Run2 mode The NPLDO should be selected as 0 9V by configuring the LDOVS bits in PMU_CTL0 The LDNP in PMU_CTL0 should be configured to select the low dirver mode Deep sleep mode The Deep sleep mode is based on the SLEEPDEEP mode of the Cortex M23 In Deep sleep mode all clock...

Page 72: ...eup NPLDO Note If power on or exit from standby it needs to wait more than 600us before entering Deep sleep 1 mode Deep sleep 2 mode The Deep sleep 2 mode is based on the SLEEPDEEP mode of the Cortex M23 In Deep sleep 2 mode all clocks in the 1 1V domain are off and all of IRC16M IRC48M HXTAL and PLLs are disabled The power of COREOFF0 SRAM1 COREOFF1 domain is cut off The contents of COREOFF0 SRAM...

Page 73: ...keup status Wakeup Latency Run no effect on all clocks all power on NPLDO on LPLDO on system power reset or wakeup from standby Run1 system clock 16Mhz NPLDO on LPLDO on LDOVS set to 0 9V clear LDVOS Run2 system clock 2Mhz NPLDO in low driver mode LPLDO on LDOVS set to 0 9V and LDNP set to 1 clear LDVOS and LDNP Sleep Only CPU clock is off NPLDO on LPLDO on SLEEPDEEP 0 WFI or WFE from Run Any inte...

Page 74: ...10 WFI or WFE Any interrupt from EXTI lines for WFI Any event or interrupt when SEVONPEND is 1 from EXTI for WFE Run Run1 Run 2 IRC16M wakeup time NPLDO wakeup time Flash wakeup time Standby 1 The 1 1V domain is power off 2 Disable IRC16M IRC48M HXTAL and PLLs NPLDO off LPLDO off SLEEPDEEP 1 LPMOD 11 WFI or WFE 1 NRST pin 2 WKUP pins 3 FWDGT reset 4 RTC Run IRC16M wakeup time NPLDO wakeup time Fla...

Page 75: ...L closed And the LDO output voltage selected by LDOVS bits takes effect when the main PLL enabled If the main PLL closed the LDO output voltage low mode selected value of this bit filed not changed 0x LDO output voltage low mode 0 9V 1x LDO output voltage high mode 1 1V 13 VCRSEL VBAT battery charging resistor selection 0 5 kOhms resistor is selected for charing VBAT battery 1 1 5 kOhms resistor i...

Page 76: ...ow Voltage Detector Enable 0 Disable Low Voltage Detector 1 Enable Low Voltage Detector 3 STBRST Standby Flag Reset 0 No effect 1 Reset the standby flag This bit is always read as 0 2 WURST Wakeup Flag Reset 0 No effect 1 Reset the wakeup flag This bit is always read as 0 1 0 LPMOD 1 0 Select the low power mode to enter when the Cortex M23 enters SLEEPDEEP mode 00 Deep sleep 01 Deep sleep 1 10 Dee...

Page 77: ...ving mode As the WKUP pin4 is active high the WKUP pin4 is internally configured to input pull down mode And set this bit will trigger a wakup event when the input is aready high 11 WUPEN3 WKUP Pin3 PB2 enable 0 Disable WKUP pin3 function 1 Enable WKUP pin3 function If WUPEN3 is set before entering the power saving mode a rising edge on the WKUP pin3 wakes up the system from the power saving mode ...

Page 78: ...d Must be kept at reset value 2 LVDF Low Voltage Detector Status Flag 0 Low Voltage event has not occurred VDD is higher than the specified LVD threshold 1 Low Voltage event occurred VDD is equal to or lower than the specified LVD threshold Note The LVD function is stopped in Standby mode 1 STBF Standby Flag 0 The device has not entered the Standby mode 1 The device has been in the Standby mode Th...

Page 79: ...et value 5 CORE1WAKE COREOFF1 domain wakeup This bit is set by software only in Run Run1 Run2 mode and COREOFF1 in sleep mode and cleared by hardware 4 CORE1SLEEP COREOFF1 domain go to power off This bit is set by software only in Run Run1 Run2 mode and COREOFF1 in active mode and cleared by hardware 3 2 Reserved Must be kept at reset value 1 SRAM1PWAKE SRAM1 wakeup This bit is set by software onl...

Page 80: ... Must be kept at reset value 3 4 5 Parameter register PMU_PAR Address offset 0x10 Reset value 0x040A 2064 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TWKEN TWKSRA M1EN TWKCOR E1EN TWK_CORE1 7 0 TSW_IRC16MCNT 4 0 rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TWK_SRAM1 7 0 TWK_CORE0 7 0 rw rw Bits Fields Descriptions 31 TWKE...

Page 81: ...ower switch of COREOFF1 domain 4 clock step and the max value is 64us 20 16 TSW_IRC16MCNT 4 0 When enter deep sleep mode switch to IRC16M clock Wait the IRC16M COUNTER and then set deep sleep signal The default is 10 IRC16M clock 15 8 TWK_SRAM1 7 0 Wakeup time of power switch of SRAM1 domain 4 IRC16M clock step and the max value is 64us 7 0 TWK_CORE0 7 0 Wakeup time of power switch of COREOFF0 dom...

Page 82: ... power reset sets all registers to their reset values except the backup domain The power reset which active signal is low will be de asserted when the internal LDO voltage regulator is ready to provide 1 1V power for GD32L23x series The RESET service routine vector is fixed at address 0x0000_0004 in the memory map System Reset A system reset is generated by the following events A power reset POWER...

Page 83: ...n Internal 16 MHz RC oscillator IRC16M an Internal 48 MHz RC oscillator IRC48M a High speed crystal oscillator HXTAL an Internal 32KHz RC oscillator IRC32K a Low speed crystal oscillator LXTAL a Phase Lock Loop PLL a HXTAL clock monitor a LXTAL clock monitor clock prescalers clock multiplexers and clock gating circuitry The clocks of the AHB APB and Cortex M23 are derived from the system clock CK_...

Page 84: ... to USART1 LPUART CK_SYS CK_APB1 10 01 00 11 LPTIMERSEL 1 0 CK_IRC16M DIV CK_LXTAL CK_LPTIMER to LPTIMER CK_IRC32K CK_APB2 16 10 12 14 16 11 13 15 17 1x IRC16M divide 1 2 4 8 16 CK_IRC1 6MDIV CK_CTC to CTC The frequency of AHB APB2 and the APB1 domains can be configured by each prescaler The maximum frequency of the AHB APB2 and APB1 domains is 64MHz 64MHz 32MHz The Cortex System Timer SysTick ext...

Page 85: ...HXTAL which has a frequency from 4 to 32 MHz produces a highly accurate clock source for use as the system clock A crystal with a specific frequency must be connected and located close to the two HXTAL pins The external resistor and capacitor components connected to the crystal are necessary for proper oscillation Figure 4 3 HXTAL clock source OSCIN OSCOUT C1 C2 Crystal The HXTAL crystal oscillato...

Page 86: ...ze the time required for the system to recover from the Deep sleep Mode the hardware forces the IRC16M clock to be the system clock when the system initially wakes up IRC16M can be switched on by LPUART USART0 USART1 I2C0 I2C1 I2C2 during deep sleep mode If the IRC16M switch on during deep sleep state the unworked peripheral should been disabled for save power Internal 48M RC oscillators IRC48M Th...

Page 87: ...s a low cost clock source as no external components are required The IRC32K RC oscillator can be switched on or off by using the IRC32KEN bit in the Reset Source Clock Register RCU_RSTSCK The IRC32KSTB flag in the Reset Source Clock Register RCU_RSTSCK will indicate if the IRC32K clock is stable An interrupt can be generated if the related interrupt enable bit IRC32KSTBIE in the Interrupt register...

Page 88: ...e selected via the CK_OUT clock source selection bits CKOUTSEL in the configuration register 0 RCU_CFG0 The corresponding GPIO pin should be configured in the properly alternate function I O AFIO mode to output the selected clock signal Table 4 1 Clock source select Clock Source Selection bits Clock Source 000 No Clock 001 CK_IRC48M 010 CK_IRC32K 011 CK_LXTAL 100 CK_SYS 101 CK_IRC16M 110 CK_HXTAL ...

Page 89: ...IRC16M clock which used to the I2C0 I2C1 I2C2 to wake up the deep sleep 1 2 mode FMC and PMU also have capable of open IRC16M clock or close IRC16M clock if they work in deep sleep 1 2 mode To save power in deep sleep 1 2 mode CK_FMC and LPUART USART0 USART1 function clock can be gated individually if they don t work in deep sleep 1 2 mode mode But I2C0 I2C1 I2C2 ADC LPTIMER PMU function clock can...

Page 90: ...lock is stable and ready for use 0 PLL is not stable 1 PLL is stable 24 PLLEN PLL enable Set and reset by software This bit cannot be reset if the PLL clock is used as the system clock Reset by hardware when entering Deep sleep or Standby mode 0 PLL is switched off 1 PLL is switched on 23 LXTALCKMD LXTAL clock failure detection Set by hardware to indicate when a failure has been detected by the cl...

Page 91: ...ernal RC oscillator regardless of the control bit IRC16MEN state 18 HXTALBPS External crystal oscillator HXTAL clock bypass mode enable The HXTALBPS bit can be written only if the HXTALEN is 0 0 Disable the HXTAL Bypass mode 1 Enable the HXTAL Bypass mode in which the HXTAL output clock is equal to the input clock 17 HXTALSTB External crystal oscillator HXTAL clock stabilization flag Set by hardwa...

Page 92: ... offset 0x04 Reset value 0x003C 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PLLDV CKOUTDIV 2 0 PLLMF 6 CKOUTSEL 2 0 PLLMF 5 0 PLLSEL rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCPSC 1 0 APB2PSC 2 0 APB1PSC 2 0 AHBPSC 3 0 SCSS 1 0 SCS 1 0 rw rw rw rw r rw Bits Fields Descriptions 31 PLLDV The CK_PLL ...

Page 93: ...LL source clock x PLLMF 6 0 1 1111111 Reserved Note The PLL output frequency must not exceed 64 MHz 17 16 PLLSEL PLL clock source selection Set and reset by software to control the PLL clock source 00 IRC16M clock selected as source clock of PLL 01 HXTAL selected as source clock of PLL 1x IRC48M clock selected as source clock of PLL 15 14 ADCPSC 1 0 ADC clock prescaler selection These bits and bit...

Page 94: ...ected 1100 CK_SYS 64 selected 1101 CK_SYS 128 selected 1110 CK_SYS 256 selected 1111 CK_SYS 512 selected 3 2 SCSS 1 0 System clock switch status Set and reset by hardware to indicate the clock source of system clock 00 select CK_IRC16M as the CK_SYS source 01 select CK_HXTAL as the CK_SYS source 10 select CK_PLL as the CK_SYS source 11 select CK_IRC48M as the CK_SYS source 1 0 SCS 1 0 System clock...

Page 95: ...Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 CKMIC HXTAL clock stuck interrupt clear Write 1 by software to reset the CKMIF flag 0 Not reset CKMIF flag 1 Reset CKMIF flag 22 LXTALCKMIC LXTAL clock stuck interrupt clear Write 1 by software to reset the LXTALCKMIF flag 0 Not reset LXTALCKMIF flag 1 Reset LXTALCKMIF flag 21 IRC48MSTBIC IRC48M stabilization interrupt clear Wr...

Page 96: ...zation interrupt 1 Enable the IRC48M stabilization interrupt 12 PLLSTBIE PLL stabilization interrupt enable Set and reset by software to enable disable the PLL stabilization interrupt 0 Disable the PLL stabilization interrupt 1 Enable the PLL stabilization interrupt 11 HXTALSTBIE HXTAL stabilization interrupt enable Set and reset by software to enable disable the HXTAL stabilization interrupt 0 Di...

Page 97: ...n setting the PLLSTBIC bit 0 No PLL stabilization interrupt generated 1 PLL stabilization interrupt generated 3 HXTALSTBIF HXTAL stabilization interrupt flag Set by hardware when the external 4 32 MHz crystal oscillator clock is stable and the HXTALSTBIE bit is set Reset by software when setting the HXTALSTBIC bit 0 No HXTAL stabilization interrupt generated 1 HXTAL stabilization interrupt generat...

Page 98: ...9 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved USART0 RST Reserved SPI0RST TIMER8 RST Reserved ADCRST Reserved CMPRST SYSCFG RST rw rw rw rw rw rw Bits Fields Descriptions 31 15 Reserved Must be kept at reset value 14 USART0RST USART0 Reset This bit is set and reset by software 0 No reset 1 Reset the USART0 13 Reserved Must be kept at reset value 12 SPI0RST SPI0 Reset This bit ...

Page 99: ... PMURST Reserved I2C2RST USBDRST I2C1RST I2C0RST UART4R ST UART3RS T LPUARTR ST USART1 RST Reserved rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SPI1RST Reserved WWDGT RST SLCDRS T LPTIMER RST TIMER11 RST Reserved TIMER6R ST TIMER5R ST Reserved TIMER2R ST TIMER1R ST rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 30 Reserved Must be kept at reset value 30 ...

Page 100: ...20 UART4RST UART4 reset This bit is set and reset by software 0 No reset 1 Reset UART4 19 UART3RST UART3 reset This bit is set and reset by software 0 No reset 1 Reset UART3 18 LPUARTRST LPUART reset This bit is set and reset by software 0 No reset 1 Reset LPUART 17 USART1RST USART1 reset This bit is set and reset by software 0 No reset 1 Reset USART1 16 15 Reserved Must be kept at reset value 14 ...

Page 101: ...ept at reset value 5 TIMER6RST TIMER6 timer reset This bit is set and reset by software 0 No reset 1 Reset TIMER6 timer 4 TIMER5RST TIMER5 timer reset This bit is set and reset by software 0 No reset 1 Reset TIMER5 timer 3 2 Reserved Must be kept at reset value 1 TIMER2RST TIMER2 timer reset This bit is set and reset by software 0 No reset 1 Reset TIMER2 timer 0 TIMER1RST TIMER1 timer reset This b...

Page 102: ...0 Disabled GPIO port D clock 1 Enabled GPIO port D clock 19 PCEN GPIO port C clock enable This bit is set and reset by software 0 Disabled GPIO port C clock 1 Enabled GPIO port C clock 18 PBEN GPIO port B clock enable This bit is set and reset by software 0 Disabled GPIO port B clock 1 Enabled GPIO port B clock 17 PAEN GPIO port A clock enable This bit is set and reset by software 0 Disabled GPIO ...

Page 103: ...led SRAM0 interface clock during Sleep mode 1 Reserved Must be kept at reset value 0 DMAEN DMA clock enable This bit is set and reset by software 0 Disabled DMA clock 1 Enabled DMA clock 4 3 7 APB2 enable register RCU_APB2EN Address offset 0x18 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserv...

Page 104: ...lock enable This bit is set and reset by software 0 Disabled ADC interface clock 1 Enabled ADC interface clock 8 2 Reserved Must be kept at reset value 1 CMPEN Comparator clock enable This bit is set and reset by software 0 Disabled system comparator clock 1 Enabled comparator clock 0 SYSCFGEN System configuration clock enable This bit is set and reset by software 0 Disabled system configuration c...

Page 105: ...DACEN DAC clock enable This bit is set and reset by software 0 Disabled DAC clock 1 Enabled DAC clock 28 PMUEN Power interface clock enable This bit is set and reset by software 0 Disabled Power interface clock 1 Enabled Power interface clock 27 25 Reserved Must be kept at reset value 24 I2C2EN I2C2 clock enable This bit is set and reset by software 0 Disabled I2C2 clock 1 Enabled I2C2 clock 23 US...

Page 106: ...ust be kept at reset value 14 SPI1EN SPI1 clock enable This bit is set and reset by software 0 Disabled SPI1 clock 1 Enabled SPI1 clock 13 12 Reserved Must be kept at reset value 11 WWDGTEN Window watchdog timer clock enable This bit is set and reset by software 0 Disabled window watchdog timer clock 1 Enabled window watchdog timer clock 10 SLCDEN SLCD clock enable This bit is set and reset by sof...

Page 107: ...ck 1 Enabled TIMER1 timer clock 4 3 9 Backup domain control register RCU_BDCTL Address offset 0x20 Reset value 0x0000 0018 reset by Backup domain Reset This register can be accessed by byte 8 bit half word 16 bit and word 32 bit Note The LXTALEN LXTALBPS RTCSRC and RTCEN bits of the Backup domain control register BDCTL are only reset after a Backup domain Reset These bits can be modified only when...

Page 108: ... capability Set and reset by software Backup domain reset reset this value 00 lower driving capability 01 medium low driving capability 10 medium high driving capability 11 higher driving capability reset value Note The LXTALDRI is not in bypass mode 2 LXTALBPS LXTAL bypass mode enable Set and reset by software 0 Disable the LXTAL Bypass mode 1 Enable the LXTAL Bypass mode 1 LXTALSTB External low ...

Page 109: ...watchdog timer reset generated Reset by writing 1 to the RSTFC bit 0 No window watchdog reset generated 1 Window watchdog reset generated 29 FWDGTRSTF Free Watchdog timer reset flag Set by hardware when a Free Watchdog timer generated Reset by writing 1 to the RSTFC bit 0 No Free Watchdog timer reset generated 1 Free Watchdog timer reset generated 28 SWRSTF Software reset flag Set by hardware when...

Page 110: ...are to indicate if the IRC32K output clock is stable and ready for use 0 IRC32K is not stable 1 IRC32K is stable 0 IRC32KEN IRC32K enable Set and reset by software 0 Disable IRC32K 1 Enable IRC32K 4 3 11 AHB reset register RCU_AHBRST Address offset 0x28 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ...

Page 111: ...A 1 Reset GPIO port A 16 7 Reserved Must be kept at reset value 6 CRCRST CRC reset This bit is set and reset by software 0 No reset CRC module 1 Reset CRC module 5 0 Reserved Must be kept at reset value 4 3 12 Configuration register 1 RCU_CFG1 Address offset 0x2C Reset value 0x0000 0007 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20...

Page 112: ...2 Address offset 0x30 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADCPS C 3 2 Reserved IRC16MDIVSEL USART1SEL 1 0 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved USBDSEL LPUARTSEL 1 0 LPTIMERSEL 1 0 ADCSEL I2C2SEL 1 0 I2C1SEL 1 0 I2C0SEL 1 0 USART0SEL 1 0 rw rw rw rw rw rw rw rw Bits Fi...

Page 113: ...C16MDIV 10 9 LPTIMERSEL 1 0 CK_LPTIMER clock source selection This bit is set and reset by software 00 CK_LPTIMER select CK_APB2 01 CK_LPTIMER select CK_IRC32K 10 CK_LPTIMER select CK_LXTAL 11 CK_LPTIMER select CK_IRC16MDIV 8 ADCSEL CK_ADC clock source selection This bit is set and reset by software 0 CK_ADC select CK_IRC16M 1 CK_ADC select CK_APB2 which is divided by 2 4 6 8 10 12 14 16 or by the...

Page 114: ... 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRNGEN Reserved CAUEN Reserved rw rw Bits Fields Descriptions 31 4 Reserved Must be kept at reset value 3 TRNGEN TRNG clock enable This bit is set and reset by software 0 Disabled TRNG clock 1 Enabled TRNG clock 2 Reserved Must be kept at reset value 1 CAUEN CAU clock enable This bit is set and reset by software 0 Disabled CAU clock 1 Ena...

Page 115: ...eserved Must be kept at reset value 4 3 16 Voltage key register RCU_VKEY Address offset 0x100 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY 15 0 w Bits Fields Descriptions 31 0 KEY 31 0 The key of RCU_DSV register These bits are written only b...

Page 116: ...t and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LPBMSEL 1 0 rw Bits Fields Descriptions 31 3 Reserved Must be kept at reset value 2 0 LPBMSEL 1 0 Low power mode selection signal The length of holding phase of sample and hold circuit is controlled 011 The length of holding phase is 3 2ms 32 clock cycles 010 The length of hold...

Page 117: ...nce signal source It can automatically adjust the trim value to provide a precise IRC48M clock 5 2 Characteristics Three external reference signal source GPIO LXTAL clock USBD_SOF Provide software reference sync pulse Automatically trimmed by hardware without any software action 16 bits trim counter with reference signal source capture and reload 8 bits clock trim base value to frequency evaluatio...

Page 118: ...tting REFPOL bit in CTC_CTL1 register and can be divided to a suitable frequency with a configurable prescaler by setting REFPSC bits in CTC_CTL1 register Thirdly if a software reference pulse needed write 1 to SWREFPUL bit in CTC_CTL0 register The software reference pulse generated in last step is logical OR with the external reference pulse 5 3 2 CTC trim counter The CTC trim counter is clocked ...

Page 119: ...lock is slower than correct clock the frequency of 48M It needs to improve TRIMVALUE in CTC_CTL0 register If a REF sync pulse occurs on up counting it means the current clock is faster than correct clock the frequency of 48M It needs to reduce TRIMVALUE in CTC_CTL0 register The CKOKIF CKWARNIF CKERR and REFMISS in CTC_STAT register shows the frequency evaluation scope If the AUTOTRIM bit in CTC_CT...

Page 120: ...t changed Counter 128 x CKLIM when up counting The REFMISS in CTC_STAT register set and an interrupt generated if ERRIE bit in CTC_CTL0 register is 1 The TRIMVALUE in CTC_CTL0 register is not changed If adjusting the TRIMVALUE in CTC_CTL0 register over the value of 127 the overflow will be occurred while adjusting the TRIMVALUE under the value of 0 the underflow will be occurred The TRIMVALUE is i...

Page 121: ...GD32L23x User Manual 121 The typical step size is 0 12 Where the 𝐹𝑐𝑙𝑜𝑐𝑘 is the frequency of correct clock IRC48M the 𝐹𝑅𝐸𝐹 is the frequency of reference sync pulse ...

Page 122: ...is mode used to hardware trim The middle value is 64 When increase 1 the IRC48M clock frequency add around 57KHz When decrease 1 the IRC48M clock frequency sub around 57KHz 7 SWREFPUL Software reference source sync pulse This bit is set by software and generates a reference sync pulse to CTC counter This bit is cleared by hardware automatically and read as 0 0 No effect 1 generates a software refe...

Page 123: ...ol register 1 CTC_CTL1 Address offset 0x04 Reset value 0x2022 BB7F This register has to be accessed by word 32 bit This register cannot be modified when CNTEN is 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 REF POL Reserved REFSEL 1 0 Reserved REFPSC 2 0 CKLIM 7 0 rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RLVALUE 15 0 rw Bits Fields Descriptions 31 REFPOL Reference signal source polar...

Page 124: ...cy evaluation and automatically trim process Please refer to the Frequency evaluation and automatically trim process for detail 15 0 RLVALUE 15 0 CTC counter reload value These bits are set and cleared by software to define the CTC counter reload value These bits reload to CTC trim counter when a reference sync pulse received to start or restart the counter 5 4 3 Status register CTC_STAT Address o...

Page 125: ...1 to ERRIC bit in CTC_INTC register 0 No Reference sync pulse miss occur 1 Reference sync pulse miss occur 8 CKERR Clock trim error bit This bit is set by hardware when the clock trim error occur This is occur when the CTC trim counter greater or equal to 128 x CKLIM during down counting when a reference sync pulse detected This means the clock is too slow and cannot be trimmed to correct frequenc...

Page 126: ... counter smaller to 3 x CKLIM when a reference sync pulse detected this bit will be set This means the clock is OK to use The TRIMVALUE need not to adjust or adjust one step When the CKOKIE in CTC_CTL0 register is an interrupt occur This bit is cleared by writing 1 to CKOKIC bit in CTC_INTC register 0 No Clock trim OK occur 1 Clock trim OK occur 5 4 4 Interrupt clear register CTC_INTC Address offs...

Page 127: ...C CKWARNIF interrupt clear bit This bit is written by software and read as 0 Write 1 to clear CKWARNIF bit in CTC_STAT register Write 0 is no effect 0 CKOKIC CKOKIF interrupt clear bit This bit is written by software and read as 0 Write 1 to clear CKOKIF bit in CTC_STAT register Write 0 is no effect ...

Page 128: ...y configuration 4 priority levels Efficient interrupt processing Support exception pre emption and tail chaining Wake up system from power saving mode Up to 30 independent edge detectors in EXTI Three trigger types rising falling and both edges Software interrupt or event trigger Trigger sources configurable 6 3 Interrupts function overview The ARM Cortex M23 processor and the Nested Vectored Inte...

Page 129: ...0_0044 IRQ 2 18 RTC Tamper and Timestamp from EXTI interrupt 0x0000_0048 IRQ 3 19 RTC Wakeup from EXTI interrupt 0x0000_004C IRQ 4 20 FMC global interrupt 0x0000_0050 IRQ 5 21 RCU or CTC global interrupt 0x0000_0054 IRQ 6 22 EXTI Line0 interrupt 0x0000_0058 IRQ 7 23 EXTI Line1 interrupt 0x0000_005C IRQ 8 24 EXTI Line2 interrupt 0x0000_0060 IRQ 9 25 EXTI Line3 interrupt 0x0000_0064 IRQ 10 26 EXTI L...

Page 130: ...RQ 40 56 I2C2 error interrupt 0x0000_00E0 IRQ 41 57 RTC alarm from EXTI interrupt 0x0000_00E4 IRQ 42 58 USBD wakeup from EXTI interrupt 0x0000_00E8 IRQ 43 59 EXTI line 9 5 interrupts 0x0000_00EC IRQ 44 46 60 62 Reserved 0x0000_00F0 0x0000_00F8 IRQ 47 63 EXTI line 15 10 interrupts 0x0000_00FC IRQ 48 54 64 70 Reserved 0x0000_0100 0x0000_0118 IRQ 55 71 DMA MUX interrupt 0x0000_011C IRQ 56 72 CMP0 out...

Page 131: ...l lines from GPIO pins and 14 lines from internal modules including LVD USB RTC I2C USART CMP LPUART and LPTIMER All GPIO pins can be selected as an EXTI trigger source by configuring SYSCFG_EXTISSx registers in SYSCFG module please refer to System configuration registers section for detail EXTI can provide not only interrupts but also event signals to the processor The Cortex M23 processor fully ...

Page 132: ...6 PB6 PC6 PD6 7 PA7 PB7 PC7 8 PA8 PB8 PC8 PD8 9 PA9 PB9 PC9 PD9 10 PA10 PB10 PC10 11 PA11 PB11 PC11 12 PA12 PB12 PC12 13 PA13 PB13 PC13 14 PA14 PB14 PC14 15 PA15 PB15 PC15 16 LVD 17 RTC Alarm 18 USBD Wakeup 19 RTC Tamper and Timestamp 20 RTC Wakeup 21 CMP0 output 22 CMP1 output 23 I2C0 Wakeup 24 I2C2 Wakeup 25 USART0 Wakeup 26 USART1 Wakeup 27 I2C1 Wakeup 28 LPUART Wakeup 29 LPTIMER Wakeup ...

Page 133: ... Bits Fields Descriptions 31 30 Reserved Must be kept at reset value 29 0 INTENx Interrupt enable bit x x 0 29 0 Interrupt from Linex is disabled 1 Interrupt from Linex is enabled 6 6 2 Event enable register EXTI_EVEN Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved EVEN29 EVEN28 EVEN27 EVEN26 EVEN2...

Page 134: ...ing edge trigger enable x 0 29 0 Rising edge of Linex is invalid 1 Rising edge of Linex is valid as an interrupt event request 6 6 4 Falling edge trigger enable register EXTI_FTEN Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FTEN29 FTEN28 FTEN27 FTEN26 FTEN25 FTEN24 FTEN23 FTEN22 FTEN21 FTEN20 F...

Page 135: ...nt software trigger x 0 29 0 Deactivate the EXTIx software interrupt event request 1 Activate the EXTIx software interrupt event request 6 6 6 Pending register EXTI_PD Address offset 0x14 Reset value undefined This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PD29 PD28 PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD21 PD19 PD19 PD17 PD16 rc_w1 rc_w1 rc_...

Page 136: ...alog mode Each GPIO pin can be configured as pull up pull down or no pull up pull down All GPIOs are high current capable except for analog mode 7 2 Characteristics Input output direction control Schmitt trigger input function enable control Each pin weak pull up pull down function Output push pull open drain enable control Output set reset control External interrupt with programmable trigger edge...

Page 137: ... 00 pull up 01 pull down 10 GPIO OUTPUT push pull Floating 01 0 00 pull up 01 pull down 10 open drain Floating 1 00 pull up 01 pull down 10 AFIO INPUT X Floating 10 X 00 pull up 01 pull down 10 AFIO OUTPUT push pull Floating 10 0 00 pull up 01 pull down 10 open drain Floating 1 00 pull up 01 pull down 10 ANALOG X X 11 X XX Figure 7 1 Basic structure of a standard I O port bit shows the basic struc...

Page 138: ... GPIO pins are configured as input pins all GPIO pins have an internal weak pull up and weak pull down which can be chosen And the data on the external pins can be captured at every AHB clock cycle to the port input status register GPIOx_ISTAT When the GPIO pins are configured as output pins user can configure the speed of the ports And chooses the output driver mode Push Pull or Open Drain mode T...

Page 139: ...scillators additional functions the port type is set automatically by related RTC PMU and RCU registers These ports can be used as normal GPIO when the additional functions disabled 7 3 5 Input configuration When GPIO pin is configured as Input The schmitt trigger input is enabled The weak pull up and pull down resistors could be chosen Every AHB clock cycle the data present on the I O pin is got ...

Page 140: ...tput configuration shows the output configuration Figure 7 3 Output configuration Vss Output Control Vdd Output Control Register Input Status Register Write Read Write Alternate Function Output Read Input driver Output driver I O pin Schmitt trigger Bit Operate Registers ESD protection Vdd Vss 7 3 7 Analog configuration When GPIO pin is used as analog configuration The weak pull up and pull down r...

Page 141: ...igure 7 5 Alternate function configuration shows the alternate function configuration Figure 7 5 Alternate function configuration Vss Output Control Vdd Alternate Function Output Alternate Function Input Input driver Output driver I O pin Schmitt trigger ESD protection Vdd Vss 7 3 9 GPIO locking function The locking mechanism allows the IO configuration to be protected The protected registers are ...

Page 142: ... 7 3 10 GPIO single cycle toggle function GPIO could toggle the I O output level in single AHB cycle by writing 1 to the corresponding bit of GPIOx_TG register The output signal frequency could up to the half of the AHB clock ...

Page 143: ...12 11 10 9 8 7 6 5 4 3 2 1 0 CTL7 1 0 CTL6 1 0 CTL5 1 0 CTL4 1 0 CTL3 1 0 CTL2 1 0 CTL1 1 0 CTL0 1 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 30 CTL15 1 0 Pin 15 configuration bits These bits are set and cleared by software Refer to CTL0 1 0 description 29 28 CTL14 1 0 Pin 14 configuration bits These bits are set and cleared by software Refer to CTL0 1 0 description 27 26 CTL13 1 0 Pin ...

Page 144: ...nfiguration bits These bits are set and cleared by software Refer to CTL0 1 0 description 9 8 CTL4 1 0 Pin 4 configuration bits These bits are set and cleared by software Refer to CTL0 1 0 description 7 6 CTL3 1 0 Pin 3 configuration bits These bits are set and cleared by software Refer to CTL0 1 0 description 5 4 CTL2 1 0 Pin 2 configuration bits These bits are set and cleared by software Refer t...

Page 145: ...e bit These bits are set and cleared by software Refer to OM0 description 13 OM13 Pin 13 output mode bit These bits are set and cleared by software Refer to OM0 description 12 OM12 Pin 12 output mode bit These bits are set and cleared by software Refer to OM0 description 11 OM11 Pin 11 output mode bit These bits are set and cleared by software Refer to OM0 description 10 OM10 Pin 10 output mode bi...

Page 146: ... by software Refer to OM0 description 0 OM0 Pin 0 output mode bit These bits are set and cleared by software 0 Output push pull mode reset value 1 Output open drain mode 7 4 3 Port output speed register GPIOx_OSPD x A D F Address offset 0x08 Reset value 0x0C00 0000 for port A 0x0000 0000 for others This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24...

Page 147: ...0 1 0 description 19 18 OSPD9 1 0 Pin 9 output max speed bits These bits are set and cleared by software Refer to OSPD0 1 0 description 17 16 OSPD8 1 0 Pin 8 output max speed bits These bits are set and cleared by software Refer to OSPD0 1 0 description 15 14 OSPD7 1 0 Pin 7 output max speed bits These bits are set and cleared by software Refer to OSPD0 1 0 description 13 12 OSPD6 1 0 Pin 6 output...

Page 148: ...2 21 20 19 18 17 16 PUD15 1 0 PUD14 1 0 PUD13 1 0 PUD12 1 0 PUD11 1 0 PUD10 1 0 PUD9 1 0 PUD8 1 0 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PUD7 1 0 PUD6 1 0 PUD5 1 0 PUD4 1 0 PUD3 1 0 PUD2 1 0 PUD1 1 0 PUD0 1 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 30 PUD15 1 0 Pin 15 pull up or pull down bits These bits are set and cleared by software Refer to PUD0 1 0 descripti...

Page 149: ...ware Refer to PUD0 1 0 description 11 10 PUD5 1 0 Pin 5 pull up or pull down bits These bits are set and cleared by software Refer to PUD0 1 0 description 9 8 PUD4 1 0 Pin 4 pull up or pull down bits These bits are set and cleared by software Refer to PUD0 1 0 description 7 6 PUD3 1 0 Pin 3 pull up or pull down bits These bits are set and cleared by software Refer to PUD0 1 0 description 5 4 PUD2 ...

Page 150: ... ISTATy Port input status y 0 15 These bits are set and cleared by hardware 0 Input signal low 1 Input signal high 7 4 6 Port output control register GPIOx_OCTL x A D F Address offset 0x14 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OCTL15 OCTL14 O...

Page 151: ...y bit 1 Clear the corresponding OCTLy bit 15 0 BOPy Port set bit y y 0 15 These bits are set and cleared by software 0 No action on the corresponding OCTLy bit 1 Set the corresponding OCTLy bit 7 4 8 Port configuration lock register GPIOx_LOCK x A D F Address offset 0x1C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved...

Page 152: ...11 10 9 8 7 6 5 4 3 2 1 0 SEL3 3 0 SEL2 3 0 SEL1 3 0 SEL0 3 0 rw rw rw rw Bits Fields Descriptions 31 28 SEL7 3 0 Pin 7 alternate function selected These bits are set and cleared by software Refer to SEL0 3 0 description 27 24 SEL6 3 0 Pin 6 alternate function selected These bits are set and cleared by software Refer to SEL0 3 0 description 23 20 SEL5 3 0 Pin 5 alternate function selected These bi...

Page 153: ...ed register 1 GPIOx_AFSEL1 x A D F Address offset 0x24 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SEL15 3 0 SEL14 3 0 SEL13 3 0 SEL12 3 0 rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SEL11 3 0 SEL10 3 0 SEL9 3 0 SEL8 3 0 rw rw rw rw Bits Fields Descriptions 31 28 SEL15 3 0 Pin 15 alternat...

Page 154: ... by software Refer to SEL8 3 0 description 3 0 SEL8 3 0 Pin 8 alternate function selected These bits are set and cleared by software 0000 AF0 selected reset value 0001 AF1 selected 0010 AF2 selected 0011 AF3 selected 0100 AF4 selected 0101 AF5 selected 0110 AF6 selected 0111 AF7 selected 1000 AF8 selected 1001 AF9 selected 1010 1111 Reserved 7 4 11 Bit clear register GPIOx_BC x A D F Address offse...

Page 155: ...set value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TG15 TG14 TG13 TG12 TG11 TG10 TG9 TG8 TG7 TG6 TG5 TG4 TG3 TG2 TG1 TG0 w w w w w w w w w w w w w w w w Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 TGy Port toggle bit y y 0 15 Th...

Page 156: ... 7 8 16 32 bit data input For 7 8 16 32 bit input data length the calculation cycles are 1 2 4 AHB clock cycles User configurable polynomial value and size After CRC module reset user can configure initial value Free 8 bit register is unrelated to calculation and can be used for any other goals by any other peripheral devices Figure 8 1 Block diagram of CRC calculation unit AHB BUS Interface Input...

Page 157: ...ata is 0x1A2B3C4D 1 byte reverse 32 bit data is divided into 4 groups and reverse implement in group inside Reversed data 0x58D43CB2 2 half word reverse 32 bit data is divided into 2 groups and reverse implement in group inside Reversed data 0xD458B23C 3 word reverse 32 bit data is divided into 1 groups and reverse implement in group inside Reversed data 0xB23CD458 For output data reverse type is ...

Page 158: ...used to calculate new data and the register can be written the new data directly Write value cannot be read because the read value is the previous CRC calculation result 8 4 2 Free data register CRC_FDATA Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved...

Page 159: ...1 0 Reverse type for input data 0 Dot not use reverse for input data 1 Reverse input data with every 8 bit length 2 Reverse input data with every 16 bit length 3 Reverse input data with whole 32 bit length 4 3 PS 1 0 Size of polynomial 0 32 bit 1 16 bit POLY 15 0 is used for calculation 2 8 bit POLY 7 0 is used for calculation 3 7 bit POLY 6 0 is used for calculation 2 1 Reserved Must be kept at r...

Page 160: ... CRC data value When RST bit in CRC_CTL asserted CRC_DATA will be programmed to this value 8 4 5 Polynomial register CRC_POLY Address offset 0x14 Reset value 0x04C1 1DB7 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 POLY 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POLY 15 0 rw Bits Fields Descriptions 31 0 POLY 31 0 User configurable polynomial ...

Page 161: ...ue seed is generated from analog noise so the random number is a true random number 9 3 Function overview Figure 9 1 TRNG block diagram AHB 32 bit Bus TRNG_CTL TRNG_STAT TRNG_DATA LFSR Clock Check Analog Seed TRNG_CLK Seed Check HCLK The random number seed comes from analog circuit This analog seed is then plugged into a linear feedback shift register LFSR where a 32 bit width random number is gen...

Page 162: ... 4 When an interrupt occurs check the status register TRGN_STAT if SEIF 0 CEIF 0 and DRDY 1 then the random value in the data register could be read As required by the FIPS PUB 140 2 the first random data in data register should be saved but not be used Every subsequent new random data should be compared to the previously random data The data can only be used if it is not equal to the previously o...

Page 163: ...lue 3 IE Interrupt enabled bit This bit controls the generation of an interrupt when DRDY SEIF or CEIF was set 0 disable TRNG interrupt 1 enable TRNG interrupt 2 TRNGEN TRNG enabled bit 0 disable TRNG module reduce power consuming 1 enable TRNG module 1 0 Reserved Must be kept at reset value 9 4 2 Status register TRNG_STAT Address offset 0x04 Reset value 0x0000 0000 This register has to be accesse...

Page 164: ...ted at current time if more than 64 consecutive same bits or more than 32 consecutive 01 or 10 changing are detected 1 CECS Clock error current status 0 Clock error is not detected at current time In case of CEIF 1 and CECS 0 it means clock error has been detected before but now is recovered 1 Clock error is detected at current time TRNG_CLK frequency is lower than 1 16 HCLK frequency 0 DRDY Rando...

Page 165: ...GD32L23x User Manual 165 Bits Fields Descriptions 31 0 TRNDATA 31 0 32 bit random data ...

Page 166: ... the CPU access to the system bus for some bus cycles Round robin scheduling is implemented in the bus matrix to ensure at least half of the system bus bandwidth for the CPU 10 2 Characteristics Programmable length of data to be transferred max to 65536 7 channels and each channel are configurable AHB and APB peripherals FLASH SRAM can be accessed as source and destination Each channel is connecte...

Page 167: ...peripheral requests coming at the same time Channel management to control address data selection and data counting 10 4 Function overview 10 4 1 DMA operation Each DMA transfer consists of two operations including the loading of data from the source and the storage of the loaded data to the destination The source and destination addresses are computed by the DMA controller based on the programmed ...

Page 168: ... 16 bits 16 bits 1 Read B1B0 15 0 0x0 2 Read B3B2 15 0 0x2 3 Read B5B4 15 0 0x4 4 Read B7B6 15 0 0x6 1 Write B1B0 15 0 0x0 2 Write B3B2 15 0 0x2 3 Write B5B4 15 0 0x4 4 Write B7B6 15 0 0x6 16 bits 8 bits 1 Read B1B0 15 0 0x0 2 Read B3B2 15 0 0x2 3 Read B5B4 15 0 0x4 4 Read B7B6 15 0 0x6 1 Write B0 7 0 0x0 2 Write B2 7 0 0x1 3 Write B4 7 0 0x2 4 Write B6 7 0 0x3 8 bits 32 bits 1 Read B0 7 0 0x0 2 R...

Page 169: ...roller has initiated an AHB command to access the peripheral Figure 10 2 Handshake mechanism shows how the handshake mechanism works between the DMA controller and peripherals Figure 10 2 Handshake mechanism DMA Acknowledge Peripheral request Peripheral is ready to transmit or receive data and assert the request signal to DMA Peripheral request Peripheral request DMA acknowledge Wait the DMA bus i...

Page 170: ... the end of every DMA transfer DMA can always responds the peripheral request until the CHEN bit in the DMA_CHxCTL register is cleared 10 4 6 Memory to memory mode The memory to memory mode is enabled by setting the M2M bit in the DMA_CHxCTL register In this mode the DMA channel can also work without being triggered by a request from a peripheral The DMA channel starts transferring as soon as it i...

Page 171: ...r a dedicated clear bit in the DMA_INTC register and a dedicated enable bit in the DMA_CHxCTL register The relationship is described in the following Table 10 2 interrupt events Table 10 2 interrupt events Interrupt event Flag bit Clear bit Enable bit DMA_INTF DMA_INTC DMA_CHxCTL Full transfer finish FTFIF FTFIFC FTFIE Half transfer finish HTFIF HTFIFC HTFIE Transfer error ERRIF ERRIFC ERRIE The D...

Page 172: ...ter 0 Transfer error has not occurred on channel x 1 Transfer error has occurred on channel x 26 22 18 14 10 6 2 HTFIFx Half transfer finish flag of channel x x 0 6 Hardware set and software cleared by configuring DMA_INTC register 0 Half number of transfer has not finished on channel x 1 Half number of transfer has finished on channel x 25 21 17 13 9 5 1 FTFIFx Full Transfer finish flag of channe...

Page 173: ...r half transfer finish flag 25 21 17 13 9 5 1 FTFIFCx Clear bit for full transfer finish flag of channel x x 0 6 0 No effect 1 Clear full transfer finish flag 24 20 16 12 8 4 0 GIFCx Clear global interrupt flag of channel x x 0 6 0 No effect 1 Clear GIFx ERRIFx HTFIFx and FTFIFx bits in the DMA_INTF register 10 5 3 Channel x control register DMA_CHxCTL x 0 6 where x is a channel number Address off...

Page 174: ...l Software set and cleared 00 8 bit 01 16 bit 10 32 bit 11 Reserved These bits can not be written when CHEN is 1 7 MNAGA Next address generation algorithm of memory Software set and cleared 0 Fixed address mode 1 Increasing address mode This bit can not be written when CHEN is 1 6 PNAGA Next address generation algorithm of peripheral Software set and cleared 0 Fixed address mode 1 Increasing addre...

Page 175: ...pt 1 Enable channel full transfer finish interrupt 0 CHEN Channel enable Software set and cleared 0 Disable channel 1 Enable channel 10 5 4 Channel x counter register DMA_CHxCNT x 0 6 where x is a channel number Address offset 0x0C 0x14 x Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 ...

Page 176: ...L register is 1 When PWIDTH is 01 16 bit the LSB of these bits is ignored Access is automatically aligned to a half word address When PWIDTH is 10 32 bit the two LSBs of these bits are ignored Access is automatically aligned to a word address 10 5 6 Channel x memory base address register DMA_CHxMADDR x 0 6 where x is a channel number Address offset 0x14 0x14 x Reset value 0x0000 0000 This register...

Page 177: ...GD32L23x User Manual 177 When MWIDTH in the DMA_CHxCTL register is 10 32 bit the two LSBs of these bits are ignored Access is automatically aligned to a word address ...

Page 178: ...t is served by the DMA controller which generates a DMA acknowledge signal the DMA request signal is de asserted 11 2 Characteristics 7 channels for DMAMUX request multiplexer 4 channels for DMAMUX request generator Support 21 trigger inputs Support 21 synchronization inputs Each DMAMUX request generator channel has a DMA request trigger input selector a DMAMUX request generator counter and the tr...

Page 179: ...x_out Synchronization inputs Syncx_in Configuration Register 11 4 Signal description The DMAMUX signals are described as follows Reqx_in DMAMUX request multiplexer inputs from peripheral requests and request generator channels Peri_reqx DMAMUX DMA request line inputs from peripherals Gen_reqx DMAMUX generated DMA request from request generator Reqx_out DMAMUX requests outputs to DMA controller Trg...

Page 180: ... a built in DMAMUX request multiplexer counter for each request multiplexer channel Request multiplexer channel A DMA request input for the DMAMUX request multiplexer channel x is configured by the MUXID 5 0 bits in the DMAMUX_RM_CHxCFG register sourced either from the peripherals or from the DMAMUX request generator the sources can refer to Table 11 2 Request multiplexer input mapping A DMAMUX re...

Page 181: ...0 bits of the DMAMUX_RM_CHxCFG register The number of DMA requests transferred to the request multiplexer channel x output following a detected synchronization event is NBR 4 0 1 Figure 11 2 Synchronization mode shows an example when NBR 4 0 4 SYNCEN 1 EVGEN 1 SYNCP 1 0 01 Figure 11 2 Synchronization mode The selected Reqx_in Syncx_in Evtx_out 4 3 2 1 Reqx_out 0 DMAMUX request multiplexer counter ...

Page 182: ...4 0 4 SYNCEN 0 EVGEN 1 Figure 11 3 Event generation The selected Reqx_in Reqx_out Evtx_out 4 3 2 1 SYNCEN DMAMUX request multiplexer counter Pending DMA request 4 3 2 0 4 3 1 0 1 2 0 EVGEN Counter underrun event occurs Note If EVGEN 1 and NBR 4 0 0 an event is generated after each served DMA request Synchronization overrun If a new synchronization event occurs before the built in DMAMUX request mu...

Page 183: ...t generator channel is decremented At the request generator counter underrun the request generator channel stops generating DMA requests The built in DMAMUX request generator counter will be automatically reloaded to its programmed value upon the next trigger input event the built in counter is programmed by the NBRG 4 0 bits of the DMAMUX_RG_CHxCFG register Note The number of generated DMA reques...

Page 184: ...channel y TOIFy in DMAMUX_RG_INTF register TOIFCy in DMAMUX_RG_INTC register TOIE in DMAMUX_RG_CH xCFG register Trigger overrun interrupt When the DMAMUX request trigger overrun flag TOIFx is set and the trigger overrun interrupt is enabled by setting TOIE bit a trigger overrun interrupt will be generated The overrun flag TOIFx is reset by writing 1 to the corresponding clear bit of overrun flag T...

Page 185: ... 7 Reserved 8 Reserved 9 Reserved 10 I2C0_RX 11 I2C0_TX 12 I2C1_RX 13 I2C1_TX 14 I2C2_RX 15 I2C2_TX 16 SPI0_RX 17 SPI0_TX 18 SPI1_RX 19 SPI1_TX 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 TIMER1_CH0 26 TIMER1_CH1 27 TIMER1_CH2 28 TIMER1_CH3 29 Reserved 30 TIMER1_UP 31 Reserved 32 TIMER2_CH0 33 TIMER2_CH1 34 TIMER2_CH2 35 TIMER2_CH3 36 TIMER2_TRIG 37 TIMER2_UP 38 Reserved ...

Page 186: ...RT1_TX 54 UART3_RX 55 UART3_TX 56 UART4_RX 57 UART4_TX 58 LPUART_RX 59 LPUART_TX 60 Reserved 61 Reserved 62 Reserved 63 Reserved Trigger input mapping The DMA request trigger input for the DMAMUX request generator channel x is selected through the TID 4 0 bits in DMAMUX_RG_CHxCFG register the sources can refer to Table 11 3 Trigger input mapping Table 11 3 Trigger input mapping Trigger input ident...

Page 187: ... Reserved 22 TIMER11_CH0_O 23 Reserved Synchronization input mapping The synchronization input is selected by SYNCID 4 0 bits in the DMAMUX_RM_CHxCFG register the sources can refer to Table 11 4 Synchronization input mapping Table 11 4 Synchronization input mapping Synchronization input identification SYNCID 4 0 Source 0 EXTI_0 1 EXTI_1 2 EXTI_2 3 EXTI_3 4 EXTI_4 5 EXTI_5 6 EXTI_6 7 EXTI_7 8 EXTI_...

Page 188: ...3x User Manual 188 Synchronization input identification SYNCID 4 0 Source 13 EXTI_13 14 EXTI_14 15 EXTI_15 16 Evt0_out 17 Evt1_out 18 Evt2_out 19 Evt3_out 20 Reserved 21 Reserved 22 TIMER11_CH0_O 23 Reserved ...

Page 189: ...erved Must be kept at reset value 28 24 SYNCID 4 0 Synchronization input identification Selects the synchronization input source 23 19 NBR 4 0 Number of DMA requests to forward The the number of DMA requests to forward to the DMA controller after a synchronization event before an output event is generated equals to NBR 4 0 1 These bits shall only be written when both SYNCEN and EVGEN bits are disa...

Page 190: ...ved Must be kept at reset value 6 SOIF6 Synchronization overrun event flag of request multiplexer channel 6 Refers to SOIF0 descriptions 5 SOIF5 Synchronization overrun event flag of request multiplexer channel 5 Refers to SOIF0 descriptions 4 SOIF4 Synchronization overrun event flag of request multiplexer channel 4 Refers to SOIF0 descriptions 3 SOIF3 Synchronization overrun event flag of request...

Page 191: ...ynchronization overrun event flag of request multiplexer channel 5 Refers to SOIFC0 descriptions 4 SOIFC4 Clear bit for synchronization overrun event flag of request multiplexer channel 4 Refers to SOIFC0 descriptions 3 SOIFC3 Clear bit for synchronization overrun event flag of request multiplexer channel 3 Refers to SOIFC0 descriptions 2 SOIFC2 Clear bit for synchronization overrun event flag of ...

Page 192: ...led 18 17 RGTP 1 0 DMAMUX request generator trigger polarity 00 No event trigger detection 01 Rising edge 10 Falling edge 11 Rising and falling edges 16 RGEN DMAMUX request generator channel x enable 0 Disable DMAMUX request generator channel x 1 Enable DMAMUX request generator channel x 15 9 Reserved Must be kept at reset value 8 TOIE Trigger overrun interrupt enable 0 Disable interrupt 1 Enable ...

Page 193: ...s before the request generator counter underrun the flag is set It is cleared by writing 1 to the corresponding TOIFC0 bit in the DMAMUX_RG_INTC register 11 6 6 Rquest generator channel interrupt flag clear register DMAMUX_RG_INTC Address offset 0x144 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9...

Page 194: ...r overrun event flag of request generator channel 1 Refers to TOIFC0 descriptions 0 TOIFC0 Clear bit for trigger overrun event flag of request generator channel 0 Writing 1 clears the corresponding trigger overrun flag TOIF0 in the DMAMUX_RG_INTF register ...

Page 195: ...y a debug tool via Serial Wire SW Debug Port or JTAG interface JTAG Debug Port 12 2 1 Switch JTAG or SW interface By default the JTAG interface is active The sequence for switching from JTAG to SWD is Send 50 or more TCK cycles with TMS 1 Send the 16 bit sequence on TMS 1110011110011110 0xE79E LSB first Send 50 or more TCK cycles with TMS 1 The sequence for switching from SWD to JTAG is Send 50 or...

Page 196: ...while the Cortex M23 JTAG IR is 4 bit width So when JTAG in IR shift step it first shift 5 bit BYPASS instruction 5 b 11111 for BSD JTAG and then shift normal 4 bit instruction for Cortext M23 JTAG Because of the data shift under BSD JTAG BYPASS mode adding 1 extra bit to the data chain is needed The BSD JTAG IDCODE is 0x790007A3 12 2 4 Debug reset The JTAG DP and SW DP register are in the power o...

Page 197: ... are provided by CK_IRC16M and the debugger can debug in deep sleep mode When the SLP_HOLD bit in DBG control register 0 DBG_CTL0 is set and entering the sleep mode the clock of AHB bus for CPU is not closed and the debugger can debug in sleep mode 12 3 2 Debug support for TIMER LPTIMER I2C RTC WWDGT and FWDGT When the core is halted and the corresponding bit in DBG control register 0 or DBG contr...

Page 198: ...x0000 0000 power reset only This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TIMER11_ HOLD Reserved TIMER8_ HOLD Reserved TIMER6_H OLD TIMER5_ HOLD Reserved I2C1_HOL D rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2C0_HOL D Reserved TIMER2_ HOLD TIMER1_ HOLD Reserved WWDGT_ HOLD FWDGT_H OLD Reserved STB_ HOLD DSLP_ HOLD SLP_ HOLD rw r...

Page 199: ...1 hold the I2C1 status to avoid SMBUS timeout for debugging when the core is halted 15 I2C0_HOLD I2C0 hold bit This bit is set and reset by software 0 no effect 1 hold the I2C0 status to avoid SMBUS timeout for debugging when the core is halted 14 Reserved Must be kept at reset value 13 TIMER2_HOLD TIMER 2 hold bit This bit is set and reset by software 0 no effect 1 hold the TIMER 2 counter for de...

Page 200: ...ck are provided by CK_IRC16M 0 SLP_HOLD Sleep mode hold bit This bit is set and reset by software 0 no effect 1 In the sleep mode the clock of AHB is on 12 4 3 Control register 1 DBG_CTL1 Address offset 0x08 Reset value 0x0000 0000 power reset only This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved I2C2_HO LD LPTIMER _HOLD rw rw 15 14 13 12 11 ...

Page 201: ...ter for debugging when the core is halted 15 11 Reserved Must be kept at reset value 10 RTC_HOLD RTC hold bit This bit is set and reset by software 0 no effect 1 hold the RTC counter for debugging when the core is halted 9 0 Reserved Must be kept at reset value ...

Page 202: ... bit 8 bit or 6 bit configurable resolution Self calibration Programmable sampling time Data alignment with built in data registers DMA support for regular group Dual clock domain architecture APB clock and ADC clock Analog input channels 16 external analog inputs 1 channel for internal temperature sensor VSENSE 1 channel for internal reference voltage VREFINT 1 channel for monitoring external VBA...

Page 203: ...on Table 13 1 ADC internal signals Internal signal name Signal type Description VSENSE Input Internal temperature sensor output voltage VREFINT Input Internal voltage reference output voltage VBAT Input VBAT pin input voltage divided by 3 VSLCD Input VSLCD pin input voltage divided by 3 Table 13 2 ADC pins definition Name Signal type Remarks VDDA VDD Input analog power supply Analog power supply e...

Page 204: ...3 4 1 Calibration CLB The ADC has a foreground calibration feature During the procedure the ADC calculates a calibration factor which is internally applied to the ADC until the next ADC power off The application can not use the ADC until the calibration is completed The calibration should be performed before starting A D conversion The calibration is initiated by setting the CLB bit to 1 The CLB b...

Page 205: ...d 13 4 4 Regular and inserted channel groups The ADC supports 20 multiplexed channels and organizes the conversion results into two groups a regular channel group and an inserted channel group In the regular group a sequence of up to 16 conversions can be organized in a specific sequence The ADC_RSQ0 ADC_RSQ2 registers specify the selected channels of the regular group The RL 3 0 bits in the ADC_R...

Page 206: ...egular group 6 Wait for the EOC flag to be set 7 Read the converted result from the ADC_RDATA register 8 Clear the EOC flag by writing 0 Software procedure for a single conversion of an inserted channel 1 Make sure the DISIC SM bits in the ADC_CTL0 register are reset 2 Configure the ISQ3 with the analog channel number 3 Configure the ADC_SAMPTx register 4 Configure ETEIC and ETSIC bits in the ADC_...

Page 207: ...C_CTL1 register if it is needed 5 Prepare the DMA module to transfer data from the ADC_RDATA 6 Set the SWRCST bit or generate an external trigger for the regular group Scan conversion mode The scan conversion mode will be enabled when the SM bit in the ADC_CTL0 register is set In this mode the ADC performs conversion on the channels with a specific sequence specified in the ADC_RSQ0 ADC_RSQ2 regis...

Page 208: ...e set 7 Clear the EOC flag by writing 0 Software procedure for scan conversion on an inserted channel group 1 Set the SM bit in the ADC_CTL0 register 2 Configure the ADC_ISQ and ADC_SAMPTx registers 3 Configure the ETEIC and ETSIC bits in the ADC_CTL1 register if it is needed 4 Set the SWICST bit or generate an external trigger for the inserted group 5 Wait for the EOC EOIC flags to be set 6 Read ...

Page 209: ... regular and inserted groups cannot both work in discontinuous conversion mode Only one group conversion can be set in discontinuous conversion mode at a time Figure 13 6 Discontinuous conversion mode CH2 CH1 CH5 CH7 CH11 CH16 CH2 CH1 Inserted trigger EOC One circle of regular group RL 8 DISNUM 3 b010 CH9 CH10 CH8 CH9 CH10 EOIC One circle of inserted group IL 3 Regular trigger Sample Convert CH12 ...

Page 210: ...ddition to the ICA bit if the CTN bit is also set regular channels are continuously converted after inserted channels Figure 13 7 Auto insertion CTN 1 CH0 CH1 CH2 CH3 CH4 Sample Convert CH15 EOIC EOC CH0 CH1 Regular group Inserted group The auto insertion mode can not be enabled when the discontinuous conversion mode is set Triggered insertion If the ICA bit is cleared the triggered insertion occu...

Page 211: ... analog watchdog 13 4 8 Data alignment The alignment of data stored after conversion can be specified by DAL bit in the ADC_CTL1 register After being decreased by the user defined offset written in the ADC_IOFFx registers the inserted group data value may be a negative value The sign value is extended When left aligned the 12 10 8 bit data are aligned on a half word while the 6 bit data are aligne...

Page 212: ...0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Regular group data Inserted group data 0 0 0 Sign 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Regular group data Inserted group data DAL 0 DAL 1 Figure 13 12 Data alignment of 6 bit resolution Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 D5 D4 D3 D2 D1 D0 Regular group data Inserted group data Si...

Page 213: ... in the ADC_CTL1 register ETSRC 2 0 and ETSIC 2 0 control bits are used to specify which out of 8 possible events can trigger conversion for the regular and inserted groups Table 13 3 External trigger for regular channels of ADC ETSRC 2 0 Trigger source Trigger type 000 TIMER8_CH0 Internal on chip signal 001 TIMER8_CH1 010 reserved 011 TIMER1_CH1 100 TIMER2_TRGO 101 TIMER11_CH0 110 EXTI_11 Externa...

Page 214: ... and the sampling time 10µs for the channel 2 Enable the temperature sensor by setting the TSVREN bit in the ADC control register 1 ADC_CTL1 3 Start the ADC conversion by setting the ADCON bit or by external trigger 4 Read the resulting temperature data Vtemperature in the ADC data register and get the temperature using the following formula Temperature C Dtemperature D30 Avg_Slope 30 Dtemperature...

Page 215: ...s VSLCD 3 to the ADC_IN19 input channel So the converted digital value is VSLCD 3 13 4 15 ADC interrupts The interrupt can be produced on one of the events End of conversion for regular and inserted groups The analog watchdog event the analog watchdog status bit is set Separate interrupt enable bits are available for flexibility 13 4 16 Programmable resolution DRES fast conversion mode It is possi...

Page 216: ...efficient M means bit right shifting up to 8 bits It is configured through the OVSS 3 0 bits in the ADC_OVSAMPCTL register The summation unit can yield a result up to 20 bits 256 x 12 bit which is first shifted right The upper bits of the result are then truncated keeping only the 16 least significant bits rounded to the nearest value using the least significant bits left apart by the shifting bef...

Page 217: ...0x00FF 0x007F 0x003F 8x 0x7FF8 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 0x007F 16x 0xFFF0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 32x 0x1FFE0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 64x 0x3FFC0 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 128x 0x7FF80 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 256x 0...

Page 218: ...GD32L23x User Manual 218 Analog watchdog The oversampling configuration can only be changed when ADCON is reset Make sure configuring the oversampling before setting ADCON to 1 ...

Page 219: ...rsion starts Cleared by software writing 0 to it 3 STIC Start flag of inserted channel group 0 No inserted channel group started 1 Inserted channel group started Set by hardware when inserted channel group conversion starts Cleared by software writing 0 to it 2 EOIC End of inserted group conversion flag 0 No end of inserted group conversion 1 End of inserted group conversion Set by hardware at the...

Page 220: ...eset value 25 24 DRES 1 0 ADC resolution 00 12bit 01 10bit 10 8bit 11 6bit 23 RWDEN Regular channel analog watchdog enable 0 Regular channel analog watchdog disable 1 Regular channel analog watchdog enable 22 IWDEN Inserted channel analog watchdog enable 0 Inserted channel analog watchdog disable 1 Inserted channel analog watchdog enable 21 16 Reserved Must be kept at reset value 15 13 DISNUM 2 0 ...

Page 221: ...for WDE 0 WDE interrupt disable 1 WDE interrupt enable 5 EOCIE Interrupt enable for EOC 0 EOC interrupt disable 1 EOC interrupt enable 4 0 WDCHSEL 4 0 Analog watchdog channel select 00000 ADC channel 0 00001 ADC channel 1 00010 ADC channel 2 01000 ADC channel 8 01001 ADC channel9 01010 ADC channel 16 01011 ADC channel 17 01100 ADC channel 18 01101 ADC channel 19 Other values are reserved Note ADC ...

Page 222: ...el 16 temperature sensor enable of ADC 0 Channel 16 of ADC disable 1 Channel 16 of ADC enable 22 SWRCST Start on regular channel Set 1 on this bit starts the conversion of a regular channel group if ETSRC is 111 It is set by software and cleared by software or by hardware after the conversion starts 21 SWICST Start on inserted channel Set 1 on this bit starts the conversion ofan inserted channel g...

Page 223: ...disable 1 DMA request enable 7 4 Reserved Must be kept at reset value 3 RSTCLB Reset calibration This bit is set by software and cleared by hardware after the calibration registers are initialized 0 Calibration register initialization done 1 Calibration register initialization starts 2 CLB ADC calibration 0 Calibration done 1 Calibration start 1 CTN Continuous mode 0 Continuous mode disable 1 Cont...

Page 224: ...SPT10 2 0 description 26 24 SPT18 2 0 Refer to SPT10 2 0 description 23 21 SPT17 2 0 Refer to SPT10 2 0 description 20 18 SPT16 2 0 Refer to SPT10 2 0 description 17 15 SPT15 2 0 Refer to SPT10 2 0 description 14 12 SPT14 2 0 Refer to SPT10 2 0 description 11 9 SPT13 2 0 Refer to SPT10 2 0 description 8 6 SPT12 2 0 Refer to SPT10 2 0 description 5 3 SPT11 2 0 Refer to SPT10 2 0 description 2 0 SPT...

Page 225: ... SPT0 2 0 description 17 15 SPT5 2 0 Refer to SPT0 2 0 description 14 12 SPT4 2 0 Refer to SPT0 2 0 description 11 9 SPT3 2 0 Refer to SPT0 2 0 description 8 6 SPT2 2 0 Refer to SPT0 2 0 description 5 3 SPT1 2 0 Refer to SPT0 2 0 description 2 0 SPT0 2 0 Channel sampling time 000 2 5 cycles 001 7 5 cycles 010 13 5 cycles 011 28 5 cycles 100 41 5 cycles 101 55 5 cycles 110 71 5 cycles 111 239 5 cyc...

Page 226: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WDHT 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 WDHT 11 0 Analog watchdog high threshold These bits define the high threshold for the analog watchdog 13 5 8 Watchdog low threshold register ADC_WDLT Address offset 0x28 Reset value 0x0000 0000 This register has to be ...

Page 227: ...roup length The total number of conversion in regular group equals to RL 3 0 1 19 15 RSQ15 4 0 Refer to RSQ0 4 0 description 14 10 RSQ14 4 0 Refer to RSQ0 4 0 description 9 5 RSQ13 4 0 Refer to RSQ0 4 0 description 4 0 RSQ12 4 0 Refer to RSQ0 4 0 description 13 5 10 Regular sequence register 1 ADC_RSQ1 Address offset 0x30 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 3...

Page 228: ...Q3 0 RSQ2 4 0 RSQ1 4 0 RSQ0 4 0 rw rw rw rw Bits Fields Descriptions 31 30 Reserved Must be kept at reset value 29 25 RSQ5 4 0 Refer to RSQ0 4 0 description 24 20 RSQ4 4 0 Refer to RSQ0 4 0 description 19 15 RSQ3 4 0 Refer to RSQ0 4 0 description 14 10 RSQ2 4 0 Refer to RSQ0 4 0 description 9 5 RSQ1 4 0 Refer to RSQ0 4 0 description 4 0 RSQ0 4 0 The channel number 0 19 is written to these bits to ...

Page 229: ...nt from the regular conversion sequence the inserted channels are converted starting from 4 IL 1 0 1 if IL 1 0 length is less than 4 IL Insert channel order 11 ISQ0 ISQ1 ISQ2 ISQ3 10 ISQ1 ISQ2 ISQ3 01 ISQ2 ISQ3 00 ISQ3 13 5 13 Inserted data register x ADC_IDATAx x 0 3 Address offset 0x3C 0x48 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 2...

Page 230: ... 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TOVS OVSS 3 0 OVSR 2 0 Reserved OVSEN rw rw rw rw Bits Fields Descriptions 31 10 Reserved Must be kept at reset value 9 TOVS Triggered Oversampling This bit is set and cleared by software 0 All oversampling conversions for a channel are done consecutively after a trigger 1 Each conversion needs a trigger f...

Page 231: ...ite this bit only when ADCON 0 which ensures that no conversion is ongoing 1 Reserved Must be kept at reset value 0 OVSEN Oversampling enable This bit is set and cleared by software 0 Oversampling disabled 1 Oversampling enabled Note Software is allowed to write this bit only when ADCON 0 which ensures that no conversion is ongoing 13 5 16 Charge control register ADC_CCTL Address offset 0xC0 Reset...

Page 232: ... Reserved Must be kept at reset value 11 0 CCNT 11 0 ADC charge pulse width counter This bit field controls the value of the ADC charge pulse width The relationship between CCNT value and the pulse width is as follow Pulse Width 5us CCNT 11 0 tPCLK2 Note Software is allowed to write this bit only when ADCON 0 which ensures that no conversion is ongoing ...

Page 233: ...riggers The output voltage can be optionally buffered for higher drive capability 14 2 Main featuress DAC main features are as follows 8 bit or 12 bit resolution Left or right data alignment DMA capability for each channel Conversion update synchronously Conversion trigged by external triggers Configurable internal buffer Input voltage reference VREF Noise wave generation LFSR noise mode and Trian...

Page 234: ...pply Input analog supply ground VREF Positive reference voltage for the DAC 2 6 V VREF VDDA Input analog positive reference DAC_OUT DAC analog output Analog output signal Note The GPIO pins PA4 for DAC_OUT should be configured to analog mode before enable the DAC module 14 3 Function description 14 3 1 DAC enable The DAC can be powered on by setting the DEN bit in the DAC_CTL0 register A tWAKEUP t...

Page 235: ...MER6_TRGO 101 TIMER5_TRGO 110 EXTI9 External signal 111 SWTRIG Software trigger The TIMERx_TRGO signals are generated from the timers while the software trigger can be generated by setting the SWTR bits in the DAC_SWT register 14 3 5 DAC conversion If the external trigger is enabled by setting the DTEN bit in DAC_CTL0 register the DAC holding data is transferred to the DAC output data OUT_DO regis...

Page 236: ...bits of the LFSR register while the MSB bits are masked Figure 14 2 DAC LFSR algorithm 9 7 8 6 5 4 3 2 1 11 10 0 X6 X0 X4 X XOR X12 NOR 12 Triangle noise mode in this mode a triangle signal is added to the OUT_DH value and then the result is stored into the OUT_DO register The minimum value of the triangle signal is 0 while the maximum value of the triangle signal is 2 DWBW 1 Figure 14 3 DAC trian...

Page 237: ...N bits of the DAC_CTL0 register A DAC DMA request will be generated when an external hardware trigger not a software trigger occurs If a second external trigger arrives before the acknowledgement of the previous request the new request will not be serviced and an underrun error event occurs The DDUDR bit in the DAC_STAT0 register is set an interrupt will be generated if the DDUDRIE bit in the DAC_...

Page 238: ...DBOFF 1 Otherwise DAC is connected to the external pin and to on chip peripherals CMP 13 DDUDRIE DAC_OUT DMA underrun interrupt enable 0 DAC_OUT DMA underrun interrupt disabled 1 DAC_OUT DMA underrun interrupt enabled 12 DDMAEN DAC_OUT DMA enable 0 DAC_OUT DMA mode disabled 1 DAC_OUT DMA mode enabled 11 8 DWBW 3 0 DAC_OUT noise wave bit width These bits specify bit width of the noise wave signal o...

Page 239: ...its are only used if bit DTEN 1 and select the external event used to trigger DAC 000 TIMER1 TRGO 001 TIMER2 TRGO 010 reserved 011 reserved 100 TIMER6 TRGO 101 TIMER5 TRGO 110 EXTI line 9 111 Software trigger 2 DTEN DAC_OUT trigger enable 0 DAC_OUT trigger disabled 1 DAC_OUT trigger enabled 1 DBOFF DAC_OUT output buffer turn off 0 DAC_OUT output buffer turns on to reduce the output impedance and i...

Page 240: ...2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OUT_DH 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 OUT_DH 11 0 DAC_OUT 12 bit right aligned data These bits specify the data that is to be converted by DAC_OUT 14 4 4 DAC_OUT 12 bit left aligned data holding register OUT_L12DH Address offset 0x0C Reset ...

Page 241: ... 3 2 1 0 Reserved OUT_DH 7 0 rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 OUT_DH 7 0 DAC_OUT 8 bit right aligned data These bits specify the MSB 8 bits of the data that is to be converted by DAC_OUT 14 4 6 DAC_OUT data output register OUT_DO Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 242: ...3 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DDUDR Reserved rc_w1 Bits Fields Descriptions 31 14 Reserved Must be kept at reset value 13 DDUDR DAC_OUT DMA underrun flag set by hardware cleared by software write 1 0 no underrun occurred 1 underrun occurred Speed of DAC trigger is high than the DMA transfer 12 0 Reserved Must be kept at reset value ...

Page 243: ...equires an independent environment and lower timing accuracy The Free watchdog timer causes a reset when the internal down counter reaches 0 or the counter is refreshed when the value of the counter is greater than the window register value The register write protection function in free watchdog can be enabled to prevent it from changing the configuration unexpectedly 15 1 2 Characteristics Free r...

Page 244: ...s 0x0000 0FFF so if it is not updated the window option is disabled A reload operation is performed in order to reset the downcounter to the FWDGT_RLD value and the prescaler counter to generate the next reload as soon as the window value is changed The free watchdog can automatically start at power on when the hardware free watchdog bit in the device option bits is set To avoid reset the software...

Page 245: ...3125 1 32 011 0 03125 4095 03125 1 64 100 0 03125 8190 03125 1 128 101 0 03125 16380 03125 1 256 110 or 111 0 03125 32760 03125 The FWDGT timeout can be more accurately by calibrating the IRC32K Note When after the execution of watchdog reload operation if the MCU needs enter the deepsleep standby mode immediately more than 3 IRC32K clock intervals must be inserted in the middle of reload and deep...

Page 246: ...by writing these bits with different values 0x5555 Disable the FWDGT_PSC FWDGT_RLD and FWDGT_WND write protection 0xCCCC Start the free watchdog timer counter When the counter reduces to 0 the free watchdog generates a reset 0xAAAA Reload the counter Prescaler register FWDGT_PSC Address offset 0x04 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28...

Page 247: ...d 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RLD 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 RLD 11 0 Free watchdog timer counter reload value Write 0xAAAA in the FWDGT_CTL register will reload the FWDGT conter with the RLD value These bits are write protected Write 0X5555 to the...

Page 248: ...ing a write operation to FWDGT_RLD register this bit is set and the value read from FWDGT_RLD register is invalid 0 PUD Free watchdog timer prescaler value update During a write operation to FWDGT_PSC register this bit is set and the value read from FWDGT_PSC register is invalid Window register FWDGT_WND Address offset 0x10 Reset value 0x0000 0FFF This register can be accessed by half word 16 bit ...

Page 249: ...ected Write 0x5555 in the FWDGT_CTL register before writing these bits If several window values are used by the application it is mandatory to wait until WUD bit has been reset before changing the window value However after updating the window value it is not necessary to wait until WUD is reset before continuing code execution except in case of low power mode entry Before entering low power mode ...

Page 250: ...dow watchdog timer clock is prescaled from the APB1 clock The window watchdog timer is suitable for the situation that requires an accurate timing 15 2 2 Characteristics Programmable free running 7 bit down counter Generate reset in two conditions when WWDGT is enabled Reset when the counter reached 0x3F The counter is refreshed when the value of the counter is greater than the window register val...

Page 251: ...egister WWDGT_CFG specifies the window value The software can prevent the reset event by reloading the down counter The counter value is less than the window value and greater than 0x3F otherwise the watchdog causes a reset The early wakeup interrupt EWI is enabled by setting the EWIE bit in the WWDGT_CFG register and the interrupt will be generated when the counter reaches 0x40 or the counter is ...

Page 252: ...and maximum values of the tWWDGT Table 15 2 Min max timeout value at 64 MHz fPCLK1 Prescaler divider PSC 3 0 Min timeout value CNT 6 0 0x40 Max timeout value CNT 6 0 0x7F 1 1 0000 64μs 4 096ms 1 2 0001 128μs 8 192ms 1 4 0010 256μs 16 384ms 1 8 0011 512μs 32 768ms 1 16 0100 1 024ms 65 536ms 1 32 0101 2 048ms 131 072ms 1 64 0110 4 096ms 262 144ms 1 128 0111 8 192ms 524 288ms 1 256 1000 16 384ms 1049...

Page 253: ...D32L23x User Manual 253 If the WWDGT_HOLD bit in DBG module is cleared the WWDGT continues to work even the Cortex M23 core halted Debug mode While the WWDGT_HOLD bit is set the WWDGT stops in Debug mode ...

Page 254: ...g timer disabled 1 Window watchdog timer enabled 6 0 CNT 6 0 The value of the watchdog timer counter A reset occur when the value of this counter decreases from 0x40 to 0x3F When the value of this counter is greater than the window value writing this counter also causes a reset Configuration register WWDGT_CFG Address offset 0x04 Reset value 0x0000 007F This register can be accessed by half word 1...

Page 255: ...x40 It can be cleared by a hardware reset or software clock reset A write operation of 0 has no effect 8 7 PSC 1 0 Prescaler This bits with bit 17 16 determines the time base of the watchdog counter 6 0 WIN 6 0 The Window value A reset occur if the watchdog counter CNT bits in WWDGT_CTL is written when the value of the watchdog counter is greater than the Window value Status register WWDGT_STAT Ad...

Page 256: ...terrupt flag When the counter reaches 0x40 or refreshes before it reaches the window value this bit is set by hardware even the interrupt is not enabled EWIE in WWDGT_CFG is cleared This bit is cleared by writing 0 There is no effect when writing 1 ...

Page 257: ...y software External high accurate low frequency 50Hz or 60Hz clock used to achieve higher calendar accuracy performed by reference clock detection option function Atomic clock adjust max adjust accuracy is 0 95PPM for calendar calibration performed by digital calibration function Sub second adjustment by shift function Time stamp function for saving event time Three Tamper sources can be chosen an...

Page 258: ...election Logic RTC_OUT RTC Block Diagram ALARM 1 Alarm 1 Flag RTC_WTRV Auto reload wakeup timer WTCS RTC 2 4 8 16 ck_spre Default 1 Hz RTC Clock RTC_ALARM WTF RTC_TAMP2 The RTC unit includes Alarm event interrupt Tamper event interrupt Tamper detection erases the backup registers Timestamp can be generated when a switch to VBAT occurs 32 bit backup registers Optional RTC output function 512Hz defa...

Page 259: ...uction BPSHAD control bit decides the location when APB bus accesses the RTC calendar register RTC_DATE RTC_TIME and RTC_SS By default the BPSHAD is cleared and APB bus accesses the shadow calendar registers Shadow calendar registers is updated with the value of real calendar registers every two RTC clock and at the same time RSYNF bit will be set once This update mechanism is not performed in Dee...

Page 260: ...n is enabled the down counter is running When it reaches 0 the WTF flag is set and the wakeup counter is automatically reloaded with RTC_WUT value When WTF asserts software must then clear it If WTIE is set and this counter reaches 0 a wakeup interrupt will make system exit from the power saving mode System reset has no influence on this function WTF is also can be output to RTC_OUT from RTC_ALARM...

Page 261: ...me RTC unit supports daylight saving time adjustment through S1H A1H and DSM bit S1H and A1H can subtract or add 1 hour to the calendar when the calendar is running S1H and A1H operation can be tautologically set and DSM bit can be used to recording this adjust operation After setting the S1H A1H subtract add 1 hour will perform when next second comes Alarm function operation process To avoid unex...

Page 262: ...ading calendar registers RTC_SS RTC_TIME and RTC_DATE 1 after a system reset 2 after an initialization 3 after shift function Especially that software must clear RSYNF bit and wait it asserted before reading calendar register after wakeup from power saving mode Reading calendar registers under BPSHAD 1 When BPSHAD 1 RSYNF is cleared and maintains as 0 by hardware so reading calendar registers does...

Page 263: ... remote clock with higher degree of precision and RTC 1Hz clock ck_spre has an offset in a fraction of a second with the remote clock RTC unit provides a function named shift function to remove this offset and thus make second precision higher RTC_SS register indicates the fraction of a second in binary format and is down counting when RTC is running Therefore by adding the SFS 14 0 value to the s...

Page 264: ...are not aligned this reload operation will shift ck_spre clock edge a bit to make the ck_spre 1Hz clock edge aligned to the reference clock edge When reference detection function is running while the external reference clock is removed no reference clock edge found in 3 ck_apre window the calendar updating still can be performed by LXTAL clock only If the reference clock is recovered later detecti...

Page 265: ...bration function FREQI setting will be ignored when FACTOR_A 3 When the FACTOR_A is less than 3 the FACTOR_S value should be set to a value less than the nominal value Assuming that RTC clock frequency is nominal 32 768 KHz the corresponding FACTOR_S should be set as following rule FACTOR_A 2 2 less than nominal FACTOR_S 8189 with 32 768 KHz FACTOR_A 1 4 less than nominal FACTOR_S 16379 with 32 76...

Page 266: ...y control bit ITSEN When a time stamp event occurs on RTC_TS pin TSEN 1 the calendar value will be saved in time stamp registers RTC_DTS RTC_TTS RTC_SSTS and the time stamp flag TSF is set to 1 by hardware Time stamp event can generate an interrupt if time stamp interrupt enable TSIE is set When an internal time stamp event detected ITSEN 1 the calendar value will be saved in time stamp registers ...

Page 267: ...ntly enabled on tamper input pin by setting corresponding TPxEN bit Tamper detection configuration is set before enable TPxEN bit TPxMASK 0 The TPxF flag is set after the tamper event occurs on the pin with the following latency 1 When FLT is different from 0x0 Level detection mode with configurable filtering there are three ck_apre cycles 2 When TPTS is set Timestamp on tamper event there are thr...

Page 268: ...n mode the internal pull up resistors on the tamper detection input pin are deactivated Because of detecting the tamper event will reset the backup registers RTC_BKPx writing to the backup register should ensure that the tamper event reset and the writing operation will not occur at the same time a recommend way to avoid this situation is disable the tamper detection before writing to the backup r...

Page 269: ...the content of alarm flag or auto wakeup flag bit in RTC_STAT The OPOL bit in RTC_CTL can configure the polarity of the alarm or auto wakeup flag output which means that the RTC_ALARM output is the opposite of the corresponding flag bit or not 16 3 16 RTC pin configuration RTC_OUT RTC_TS and RTC_TAMP0 use the same pin PC13 Function of PC13 is controlled by the RTC and regardless of PC13 GPIO confi...

Page 270: ...modes except Standby mode Standby mode VBAT only mode PC13 RTC_TAMP0 RTC_TS RTC_OUT YES YES YES PA0 RTC_TAMP1 YES YES YES PA2 RTC_TAMP2 YES YES YES PB2 RTC_OUT YES NO NO PB15 RTC_REFIN YES NO NO 16 3 17 RTC power saving mode management Table 16 3 RTC power saving mode management Mode Active in Mode Exit Mode Sleep Yes RTC Interrupts Sleep1 Yes RTC Interrupts LPSleep Yes RTC Interrupts Deep sleep Y...

Page 271: ...et the rising edge for triggering 2 Configure and enable the RTC alarm tamper timestamp auto wakeup interrupt 3 Configure and enable the RTC alarm tamper timestamp auto wakeup function Table 16 4 RTC interrupts control Interrupt Event flag Control Bit Exit Sleep Exit Deep sleep And Standby Alarm 0 ALRM0F ALRM0IE Y Y 1 Alarm 1 ALRM1F ALRM1IE Y Y 1 Wakeup WTF WTIE Y Y 1 Timestamp TSF TSIE Y Y 1 Tamp...

Page 272: ... 2 0 MNU 3 0 Reserved SCT 2 0 SCU 3 0 rw rw rw rw Bits Fields Descriptions 31 23 Reserved Must be kept at reset value 22 PM AM PM mark 0 AM or 24 hour format 1 PM 21 20 HRT 1 0 Hour tens in BCD code 19 16 HRU 3 0 Hour units in BCD code 15 Reserved Must be kept at reset value 14 12 MNT 2 0 Minute tens in BCD code 11 8 MNU 3 0 Minute units in BCD code 7 Reserved Must be kept at reset value 6 4 SCT 2...

Page 273: ...units in BCD code 7 6 Reserved Must be kept at reset value 5 4 DAYT 1 0 Day tens in BCD code 3 0 DAYU 3 0 Day units in BCD code 16 4 3 Control register RTC_CTL Address offset 0x08 System reset not affected Backup domain reset value 0x0000 0000 This register is writing protected This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OUT2EN Reserved ITSEN COE...

Page 274: ...nable invert output RTC_ALARM 19 COS Calibration output selection Valid only when COEN 1 and prescalers are at default values 0 Calibration output is 512 Hz 1 Calibration output is 1Hz 18 DSM Daylight saving mark This bit is flexible used by software Often can be used to recording the daylight saving hour adjustment 17 S1H Subtract 1 hour winter time change One hour will be subtracted from current...

Page 275: ...be kept at reset value 6 CS Clock System 0 24 hour format 1 12 hour format Note Can only be written in initialization state 5 BPSHAD Shadow registers bypass control 0 Reading calendar from shadow registers 1 Reading calendar from current real time calendar Note If frequency of APB1 clock is less than seven times the frequency of RTCCLK this bit must set to 1 4 REFEN Reference clock detection funct...

Page 276: ...at reset value 17 ITSF Internal timestamp flag Set by hardware when internal time stamp event is detected Cleared by software writing 0 and must be cleared together with TSF bit by writing 0 in both bits 16 SCPF Smooth calibration pending flag Set to 1 by hardware when software writes to RTC_HRFC without entering initialization mode and set to 0 by hardware when smooth calibration configuration is...

Page 277: ...n mode for setting calendar time date and prescaler Counter will stop under this mode 6 INITF Initialization state flag Set to 1 by hardware and calendar register and prescaler can be programmed in this state 0 Calendar registers and prescaler register cannot be changed 1 Calendar registers and prescaler register can be changed 5 RSYNF Register synchronization flag Set to 1 by hardware every 2 RTC...

Page 278: ...gisters programming is allowed 16 4 5 Prescaler register RTC_PSC Address offset 0x10 System reset not effected Backup domain reset value 0x007F 00FF This register is write protected and can only be written in initialization state This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FACTOR_A 6 0 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FA...

Page 279: ... 7 Alarm 0 time and date register RTC_ALRM0TD Address offset 0x1C System reset not effect Backup domain reset value 0x0000 0000 This register is write protected and can only be written in initialization state This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MSKD DOWS DAYT 1 0 DAYU 3 0 MSKH PM HRT 1 0 HRU 3 0 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9...

Page 280: ...U 3 0 Second units in BCD code 16 4 8 Alarm 1 time and date register RTC_ALRM1TD Address offset 0x20 System reset not effect Backup domain reset value 0x0000 0000 This register is write protected and can only be written in initialization state This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MSKD DOWS DAYT 1 0 DAYU 3 0 MSKH PM HRT 1 0 HRU 3 0 rw rw rw...

Page 281: ... field 1 Mask minutes field 14 12 MNT 2 0 Minutes tens in BCD code 11 8 MNU 3 0 Minutes units in BCD code 7 MSKS Alarm second mask bit 0 Not mask second field 1 Mask second field 6 4 SCT 2 0 Second tens in BCD code 3 0 SCU 3 0 Second units in BCD code 16 4 9 Write protection key register RTC_WPK Address offset 0x24 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28...

Page 282: ... FACTOR_S SSC FACTOR_S 1 16 4 11 Shift function control register RTC_SHIFTCTL Address offset 0x2C System reset not effect Backup Reset value 0x0000 0000 This register is writing protected and can only be wrote when SOPF 0 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 A1S Reserved w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SFS 14 0 w Bits Fiel...

Page 283: ...o 1 Reset TSF bit will also clear this register This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PM HRT 1 0 HRU 3 0 r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MNT 2 0 MNU 3 0 Reserved SCT 2 0 SCU 3 0 r r r r Bits Fields Descriptions 31 23 Reserved Must be kept at reset value 22 PM AM PM mark 0 AM or 24 hour format 1 PM 21 20 HRT 1 0...

Page 284: ...scriptions 31 16 Reserved Must be kept at reset value 15 13 DOW 2 0 Days of the week 12 MONT Month tens in BCD code 11 8 MONU 3 0 Month units in BCD code 7 6 Reserved Must be kept at reset value 5 4 DAYT 1 0 Day tens in BCD code 3 0 DAYU 3 0 Day units in BCD code 16 4 14 Sub second of time stamp register RTC_SSTS Address offset 0x38 Backup domain reset 0x0000 0000 System reset no effect This regis...

Page 285: ...t reset value 15 FREQI Increase RTC frequency by 488 5PPM 0 No effect 1 One RTCCLK pulse is inserted every 211 pulses This bit should be used in conjunction with CMSK bit If the input clock frequency is 32 768KHz the number of RTCCLK pulses added during 32s calibration window is 512 FREQI CMSK 14 CWND8 Frequency compensation window 8 second selected 0 No effect 1 Calibration window is 8 second Not...

Page 286: ... 0 interrupt 1 Enable tamper 0 interrupt 26 Reserved Must be kept at reset value 25 TP2MASK Tamper 2 mask flag 0 Tamper 2 event generates a trigger event and TP2F must be cleared by software to allow next tamper event detection 1 Tamper 2 event generates a trigger event TP2F is masked and internally cleared by hardware The backup registers are not erased Note The Tamper 2 interrupt must not be ena...

Page 287: ...uration 14 13 PRCH 1 0 Pre charge duration time of RTC_TAMPx This setting determines the pre charge time before each sampling 0x0 1 RTC clock 0x1 2 RTC clock 0x2 4 RTC clock 0x3 8 RTC clock 12 11 FLT 1 0 RTC_TAMPx filter count setting This bit determines the tamper sampling type and the number of consecutive sample 0x0 Detecting tamper event using edge mode Pre charge duration is disabled automati...

Page 288: ...enable 0 Disable tamper 2 detection function 1 Enable tamper 2 detection function 4 TP1EG Tamper 1 event trigger edge If tamper detection is in edge mode FLT 0 0 Rising edge triggers a tamper detection event 1 Falling edge triggers a tamper detection event If tamper detection is in level mode FLT 0 0 Low level triggers a tamper detection event 1 High level triggers a tamper detection event 3 TP1EN...

Page 289: ...d 0x2 SSC 1 0 is to be compared and all others are ignored 0x3 SSC 2 0 is to be compared and all others are ignored 0x4 SSC 3 0 is to be compared and all others are ignored 0x5 SSC 4 0 is to be compared and all others are ignored 0x6 SSC 5 0 is to be compared and all others are ignored 0x7 SSC 6 0 is to be compared and all others are ignored 0x8 SSC 7 0 is to be compared and all others are ignored...

Page 290: ...SC 2 0 is to be compared and all others are ignored 0x4 SSC 3 0 is to be compared and all others are ignored 0x5 SSC 4 0 is to be compared and all others are ignored 0x6 SSC 5 0 is to be compared and all others are ignored 0x7 SSC 6 0 is to be compared and all others are ignored 0x8 SSC 7 0 is to be compared and all others are ignored 0x9 SSC 8 0 is to be compared and all others are ignored 0xA SS...

Page 291: ...000 System reset no effect This register has to be accessed by word 32 bit Bits Fields Descriptions 31 0 DATA 31 0 Data These registers can be wrote or read by software The content remains valid even in power saving mode because they can powered on by VBAT Tamper detection flag TPxF assertion will reset these registers ...

Page 292: ...ure Compare 4 2 0 Complementary Dead time Break Single Pulse Quadrature Decoder Slave Controller Inter connection 1 2 TRGO TO DAC DMA 3 Debug Mode 1 TIMER1 ITI0 TIMER2_TRGO ITI1 1 b0 ITI2 1 b0 ITI3 1 b0 TIMER2 ITI0 TIMER1_TRGO ITI1 1 b0 ITI2 1 b0 ITI3 1 b0 2 TIMER8 ITI0 TIMER1_TRGO ITI1 TIMER2_TRGO ITI2 1 b0 ITI3 1 b0 TIMER11 ITI0 1 b0 ITI1 TIMER1_TRGO ITI2 TIMER2_TRGO ITI3 1 b0 3 Only update even...

Page 293: ... is selectable internal clock internal trigger external input external trigger Multiple counter modes up counting down counting and center aligned counting Quadrature decoder used for motion tracking and determination of both rotation direction and position Hall sensor function used for 3 phase motor control Programmable prescaler 16 bits The factor can be changed ongoing Each channel is user conf...

Page 294: ... ETIFP 17 1 4 Function overview Clock selection The general level0 TIMER has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC TIMERx_SMCFG bit 2 0 SMC 2 0 3 b000 Internal clock CK_TIMER is selected as timer clock source which is from module RCU The default clock source is the CK_TIMER for driving the counter prescaler when the slave mode is disa...

Page 295: ...C1 1 b1 external clock mode 1 External input ETI is selected as timer clock source The TIMER_CK which drives counter s prescaler to count can be triggered by the event of rising or falling edge on the external pin ETI This mode can be selected by setting the SMC1 bit in the TIMERx_SMCFG register to 1 The other way to select the ETI signal as the clock source is setting the SMC 2 0 to 0x7 and the T...

Page 296: ...counter overflows The counting direction bit DIR in the TIMERx_CTL0 register should be set to 0 for the up counting mode Whenever if the update event software trigger is enabled by setting the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and an update event will be generated If the UPDIS bit in TIMERx_CTL0 register is set the update event is disabled When an upda...

Page 297: ... 1 CEN CNT_CLK PSC_CLK CNT_REG 5E 5F 60 61 62 63 00 01 02 03 04 05 06 07 Update event UPE Update interrupt flag UPIF CNT_REG 5F 60 Update event UPE Update interrupt flag UPIF Hardware set Software clear Hardware set PSC 0 PSC 1 TIMER_CK 08 63 62 61 00 01 02 03 CNT_CLK PSC_CLK ...

Page 298: ...ister in a count down direction Once the counter reaches 0 the counter restarts to count again from the counter reload value The counting direction bit DIR in the TIMERx_CTL0 register should be set to 1 for the down counting mode When the update event is set by the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to the counter reload value and an update event will be gen...

Page 299: ...NT_CLK PSC_CLK CNT_REG 05 04 03 02 01 00 63 62 61 60 5F 5E 5C 5B Update event UPE Update interrupt flag UPIF CNT_REG 04 03 Update event UPE Update interrupt flag UPIF Hardware set Software clear Hardware set TIMERx_PSC PSC 0 TIMERx_PSC PSC 1 TIMER_CK 5A 00 01 02 63 62 61 CNT_CLK PSC_CLK ...

Page 300: ... event when the counter counts to TIMERx_CREP 1 in the count up direction and generates an underflow event when the counter counts to 1 in the count down direction The counting direction bit DIR in the TIMERx_CTL0 register is read only and indicates the counting direction when in the center aligned counting mode The counting direction is updated by hardware automatically Setting the UPG bit in the...

Page 301: ... CAM 2 b10 upcount only TIMERx_CTL0 CAM 2 b01 downcount only CHxIF Capture compare channels The general level0 Timer has four independent channels which can be used as capture inputs or compare match outputs Each channel is built around a channel capture compare register including an input stage channel controller and an output stage Input capture mode Input capture mode allows the channel to perf...

Page 302: ...ough the edge detector the rising or falling edge is detected by configuring CHxP bit The input capture signal can also be selected from the input signal of other channel or the internal trigger signal by configuring CHxMS bits The IC prescaler makes several input events generate one effective capture event On the capture event TIMERx_CHxCV will store the value of counter So the process can be div...

Page 303: ... Output compare logic x 0 1 2 3 Capture compare register CHxCV Counter output comparator Compare output control CHxCOMCTL Output enable and polarity selector CHxP CHxE OxCPRE CHx_O CNT CHxCV CNT CHxCV CNT CHxCV Figure 17 10 Output compare logic x 0 1 2 3 shows the logic circuit of output compare mode The relationship between the channel output signal CHx_O and the OxCPRE signal more details refer ...

Page 304: ...timing configuration by TIMERx_CAR and TIMERx_CHxCV The TIMERx_CHxCV can be changed onging to meet the expected waveform Step5 Start the counter by configuring CEN to 1 The timing chart below shows the three compare modes toggle set clear CAR 0x63 CHxVAL 0x3 Figure 17 11 Output compare under three modes CEN CNT_REG 00 01 02 03 04 05 62 63 Overflow match toggle CNT_CLK OxCPRE 00 01 02 03 04 05 62 6...

Page 305: ... 2 TIMERx_CAR and duty cycle is determined by 2 TIMERx_CHxCV Figure 17 13 Timing chart of CAPWM shows the CAPWM output and interrupts waveform In up counting mode if the value of TIMERx_CHxCV is greater than the value of TIMERx_CAR the output will be always inactive in PWM mode 0 CHxCOMCTL 3 b110 And if the value of TIMERx_CHxCV is greater than the value of TIMERx_CAR the output will be always act...

Page 306: ...HxCOMCTL field to 0x01 setting to low by configuring the CHxCOMCTL field to 0x02 or toggling signal by configuring the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register The PWM mode 0 PWM mode 1 output is another output type of OxCPRE which is setup by configuring the CHxCOMCTL field to 0x06 0x07 In these modes the OxCPRE signal level is changed accord...

Page 307: ...ing the voltage level change of each direction selection source The mechanism of changing the counter direction is shown in Table 17 2 Counting direction versus encoder signals The quadrature decoder can be regarded as an external clock with a direction selection This means that the counter counts continuously from 0 to the counter reload value Therefore users must configure the TIMERx_CAR registe...

Page 308: ...unter Hall sensor function Hall sensor is generally used to control BLDC Motor the general level0 timer can support this function Each of the 3 HALL sensors provides a pulse that applied to an input capture pin can then be analyzed and both speed and position can be deduced Enable XOR by setting TI0S then each of input signal change will make the CI0 toggle CH0VAL will record the value of counter ...

Page 309: ... is selected as the trigger source configure the ETP for polarity selection and inversion For the ITIx no filter and prescaler can be used For the CIx filter can be used by configuring CHxCAPFLT no prescaler can be used For the ETIFP filter can be used by configuring ETFC and prescaler can be used by configuring ETPSC Exam1 Restart mode The counter will be cleared and restart when a rising edge of...

Page 310: ...mode Single pulse mode is enabled by setting SPM in TIMERx_CTL0 If SPM is set the counter will be cleared and stopped automatically when the next update event occurs In order to get a pulse waveform the TIMERx is configured to PWM mode or compare mode by CHxCOMCTL Once the timer is set to the single pulse mode it is not necessary to configure the timer enable bit CEN in the TIMERx_CTL0 register to...

Page 311: ...curs without taking the comparison result into account The CHxCOMFEN bit is available only when the output channel is configured to the PWM mode 0 or PWM mode 1 and the trigger source is derived from the trigger signal Figure 17 19 Single pulse mode TIMERx_CHxCV 0x04 TIMERx_CAR 0x60 TIMER_CK CNT_CLK CEN CNT_REG 00 01 02 03 04 05 5F 60 00 O2CPRE CI3 Under SPM counter stop Timers interconnection The...

Page 312: ...rflow 2 Configure the TIMER2 period TIMER2_CAR registers 3 Select the TIMER1 input trigger source from TIMER2 TRGS 000 in the TIMER1_SMCFG register 4 Configure TIMER1 in external clock mode 1 SMC 111 in TIMER1_SMCFG register 5 Start TIMER1 by writing 1 in the CEN bit TIMER1_CTL0 register 6 Start TIMER2 by writing 1 in the CEN bit TIMER2_CTL0 register Start TIMER1 with TIMER2 s Enable Update signal...

Page 313: ...3 TRGIF 14 TIMER2 TIMER1 In this example we also can use update Event as trigger source instead of enable signal Refer to Figure 17 22 Triggering TIMER1 with update signal of TIMER2 Do as follow 1 Configure TIMER2 in master mode and send its Update Event UPE as trigger output MMC 010 in the TIMER2_CTL1 register 2 Configure the TIMER2 period TIMER2_CAR registers 3 Configure TIMER1 to get the input ...

Page 314: ... the CEN bit TIMER1_CTL0 register 5 Start TIMER2 by writing 1 in the CEN bit TIMER2_CTL0 register 6 Stop TIMER2 by writing 0 in the CEN bit TIMER2_CTL0 register Figure 17 23 Pause TIMER1 with enable of TIMER2 TIMER_CK CNT_REG CNT_REG CEN 61 62 63 11 12 13 TRGIF TIMER2 TIMER1 In this example we also can use O0CPRE as trigger source instead of enable signal output Refer to Figure 17 24 Pause TIMER1 ...

Page 315: ...ed in Master Slave mode Do as follow 1 Configure TIMER2 slave mode to get the input trigger from CI0 TRGS 101 in the TIMER2_SMCFG register 2 Configure TIMER2 in event mode SMC 110 in the TIMER2_SMCFG register 3 Configure the TIMER2 in Master Slave mode by writing MSM 1 TIMER2_SMCFG register 4 Configure TIMER1 to get the input trigger from TIMER2 TRGS 000 in the TIMER1_SMCFG register 5 Configure TI...

Page 316: ...ase address then DMA will access the TIMERx_DMATB In fact TIMERx_DMATB register is only a buffer timer will map the TIMERx_DMATB to an internal register appointed by the field of DMATA in TIMERx_DMACFG If the field of DMATC in TIMERx_DMACFG is 0 1 transfer the timer sends only one DMA request While if TIMERx_DMATC is not 0 such as 3 4 transfers then timer will send 3 more requests to DMA and DMA w...

Page 317: ... time generators and the digital filters 00 fDTS fTIMER_CK 01 fDTS fTIMER_CK 2 10 fDTS fTIMER_CK 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter aligns mode selection 00 No center aligned mode edge aligned mode The direction of the counter is specified by the DIR bi...

Page 318: ...st The UPG bit is set The counter generates an overflow or underflow event The slave mode controller generates an update event 1 When enabled only counter overflow underflow generates an update interrupt or DMA request 1 UPDIS Update disable This bit is used to enable or disable the update event generation 0 update event enable The update event is generate and the buffered registers are loaded wit...

Page 319: ...the signal on TRGO is delayed compared to the actual reset 001 Enable This mode is useful to start several timers at the same time or to control a window in which a slave timer is enabled In this mode the master mode controller selects the counter enable signal TIMERx_EN as TRGO The counter enable signal is set when CEN control bit is set or the trigger input in pause mode is high There is a delay...

Page 320: ...ctive at high level or rising edge 1 ETI is active at low level or falling edge 14 SMC1 Part of SMC for enable External clock mode1 In external clock mode 1 the counter is clocked by any active edge on the ETIF signal 0 External clock mode 1 disabled 1 External clock mode 1 enabled It is possible to simultaneously use external clock mode 1 with the restart mode pause mode or event mode But the TRG...

Page 321: ...N 5 1011 fSAMP fDTS 16 N 6 1100 fSAMP fDTS 16 N 8 1101 fSAMP fDTS 32 N 5 1110 fSAMP fDTS 32 N 6 1111 fSAMP fDTS 32 N 8 7 MSM Master slave mode This bit can be used to synchronize selected timers to begin counting at the same time The TRGI is used as the start event and through TRGO timers are connected together 0 Master slave mode disable 1 Master slave mode enable 6 4 TRGS 2 0 Trigger selection T...

Page 322: ...nd disables the counter when it is low 110 Event mode A rising edge of the trigger input enables the counter The counter cannot be disabled by the slave mode controller 111 External clock mode0 The counter counts on the rising edges of the selected trigger DMA and interrupt enable register TIMERx_DMAINTEN Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 3...

Page 323: ... disabled 1 enabled 5 Reserved Must be kept at reset value 4 CH3IE Channel 3 capture compare interrupt enable 0 disabled 1 enabled 3 CH2IE Channel 2 capture compare interrupt enable 0 disabled 1 enabled 2 CH1IE Channel 1 capture compare interrupt enable 0 disabled 1 enabled 1 CH0IE Channel 0 capture compare interrupt enable 0 disabled 1 enabled 0 UPIE Update interrupt enable 0 disabled 1 enabled I...

Page 324: ... software 0 No over capture interrupt occurred 1 Over capture interrupt occurred 8 7 Reserved Must be kept at reset value 6 TRGIF Trigger interrupt flag This flag is set by hardware on trigger event and cleared by software When the slave mode controller is enabled in all modes but pause mode an active edge on trigger input generates a trigger event When the slave mode controller is enabled in paus...

Page 325: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRGG Reserved CH3G CH2G CH1G CH0G UPG w w w w w w Bits Fields Descriptions 31 7 Reserved Must be kept at reset value 6 TRGG Trigger event generation This bit is set by software and cleared by hardware automatically When this bit is set the TRGIF flag in TIMERx_STAT register is set related interrupt or DMA transfer can occur if enabled 0 No generate a t...

Page 326: ... counting it takes the auto reload value The prescaler counter is cleared at the same time 0 No generate an update event 1 Generate an update event Channel control register 0 TIMERx_CHCTL0 Address offset 0x18 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH1COM CEN CH1COMCTL 2 0...

Page 327: ...signal keeps stable independent of the comparison between the register TIMERx_CH0CV and the counter TIMERx_CNT 001 Set the channel output O0CPRE signal is forced high when the counter matches the output compare register TIMERx_CH0CV 010 Clear the channel output O0CPRE signal is forced low when the counter matches the output compare register TIMERx_CH0CV 011 Toggle on match O0CPRE toggles when the ...

Page 328: ... cycles 1 Channel 0 output quickly compare enable The minimum delay from an edge on the trigger input to activate CH0_O output is 3 clock cycles 1 0 CH0MS 1 0 Channel 0 I O mode selection This bit field specifies the work mode of the channel and the input signal selection This bit field is writable only when the channel is not active CH0EN bit in TIMERx_CHCTL2 register is reset 00 Channel 0 is con...

Page 329: ...eld specifies the factor of the prescaler on channel 0 input The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear 00 Prescaler disable capture is done on each channel input edge 01 Capture is done every 2 channel input edges 10 Capture is done every 4 channel input edges 11 Capture is done every 8 channel input edges 1 0 CH0MS 1 0 Channel 0 mode selection Same as Output compare...

Page 330: ...This mode is working only if an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register 7 CH2COMCEN Channel 2 output compare clear enable When this bit is set the O2CPRE signal is cleared when High level is detected on ETIF input 0 Channel 2 output compare clear disable 1 Channel 2 output compare clear enable 6 4 CH2COMCTL 2 0 Channel 2 compare output control This bit field c...

Page 331: ...register is set This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 11 and CH0MS bit filed is 00 2 CH2COMFEN Channel 2 output compare fast enable When this bit is set the effect of an event on the trigger in input on the capture compare output will be accelerated if the channel is configured in PWM1 or PWM2 mode The output channel will treat an active edge on the trigger...

Page 332: ...000 Filter disable fSAMP fDTS N 1 0001 fSAMP fTIMER_CK N 2 0010 fSAMP fTIMER_CK N 4 0011 fSAMP fTIMER_CK N 8 0100 fSAMP fDTS 2 N 6 0101 fSAMP fDTS 2 N 8 0110 fSAMP fDTS 4 N 6 0111 fSAMP fDTS 4 N 8 1000 fSAMP fDTS 8 N 6 1001 fSAMP fDTS 8 N 8 1010 fSAMP fDTS 16 N 5 1011 fSAMP fDTS 16 N 6 1100 fSAMP fDTS 16 N 8 1101 fSAMP fDTS 32 N 5 1110 fSAMP fDTS 32 N 6 1111 fSAMP fDTS 32 N 8 3 2 CH2CAPPSC 1 0 Cha...

Page 333: ...ept at reset value 13 CH3P Channel 3 capture compare function polarity Refer to CH0P description 12 CH3EN Channel 3 capture compare function enable Refer to CH0EN description 11 CH2NP Channel 2 complementary output polarity Refer to CH0NP description 10 Reserved Must be kept at reset value 9 CH2P Channel 2 capture compare function polarity Refer to CH0P description 8 CH2EN Channel 2 capture compar...

Page 334: ...r trigger operation in slave mode And CIxFE0 will not be inverted CH0NP 0 CH0P 1 CIxFE0 s falling edge is the active signal for capture or trigger operation in slave mode And CIxFE0 will be inverted CH0NP 1 CH0P 0 Reserved CH0NP 1 CH0P 1 CIxFE0 s falling and rising edge are both the active signal for capture or trigger operation in slave mode And CIxFE0 will be not inverted This bit cannot be modi...

Page 335: ...d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 PSC 15 0 Prescaler value of the counter clock The PSC clock is divided by PSC 1 to generate the counter clock The value of this bit filed will be loaded to the corresponding shadow register at every update event Counter auto reload register TIMERx_CAR Address offset 0x2C Res...

Page 336: ...ture or compare value of channel0 When channel 0 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When channel 0 is configured in output mode this bit filed contains value to be compared to the counter When the corresponding shadow register is enabled the shadow register updates every update event Channel...

Page 337: ...1 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH2VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH2VAL 15 0 Capture or compare value of channel 2 When channel 2 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When channel 2 is configured in output m...

Page 338: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DMATC 4 0 Reserved DMATA 4 0 rw rw Bits Fields Descriptions 31 13 Reserved Must be kept at reset value 12 8 DMATC 4 0 DMA transfer count This filed is defined the number of DMA will access R W the register of TIMERx_DMATB 7 5 Reserved Must be kept at reset value 4 0 DMATA 4 0 DMA transfer access sta...

Page 339: ...4 will be accessed The transfer Timer is calculated by hardware and ranges from 0 to DMATC Configuration register TIMERx_CFG Address offset 0xFC Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CHVSEL Reserved rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset...

Page 340: ...may be synchronized to provide a larger timer with their counters incrementing in unison 17 2 2 Characteristics Total channel num 2 Counter width 16bit Source of count clock is selectable internal clock internal trigger external input external trigger counter mode Count up only Programmable prescaler 16 bit Factor can be changed on the go Each channel is user configurable Input capture mode Output...

Page 341: ... overview Clock selection The general level1 TIMER has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC TIMERx_SMCFG bit 2 0 SMC 2 0 3 b000 Internal timer clock CK_TIMER which is from module RCU The default internal clock source is the CK_TIMER used to drive the counter prescaler when the slave mode is disabled SMC 2 0 3 b000 When the CEN is set...

Page 342: ...ck mode 1 External input pin source ETI The TIMER_CK driven counter s prescaler to count can be triggered by the event of rising or falling edge on the external pin ETI This mode can be selected by setting the SMC1 bit in the TIMERx_SMCFG register to 1 The other way to select the ETI signal as the clock source is set the SMC 2 0 to 0x7 and the TRGS 2 0 to 0x7 respectively Note that the ETI signal ...

Page 343: ...m 0 The update event is generated at each counter overflow The counting direction bit DIR in the TIMERx_CTL1 register should be set to 0 for the up counting mode When the update event is set by the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and generates an update event If the UPDIS bit in TIMERx_CTL0 register is set the update event is disabled When an update ...

Page 344: ...IMER_CK 08 63 62 61 00 01 02 03 CNT_CLK PSC_CLK Figure 17 30 Up counter timechart change TIMERx_CAR on the go TIMER_CK CEN CNT_CLK PSC_CLK CNT_REG 5E 5F 60 61 62 63 00 01 02 03 04 05 06 07 Update event UPE Update interrupt flag UPIF Auto reload register 65 63 change CAR Vaule CNT_REG 5E 5F 60 61 62 63 64 65 00 01 02 62 63 00 Update event UPE Update interrupt flag UPIF Auto reload register 65 63 ch...

Page 345: ...ture logic CI0 Synchronizer D presclare Capture Register CH0VAL Clock Processer Counter TIMER_CK Q Filter D Q D Q Edge Detector CI1FE0 ITS CH0MS CH0IF CH0IE CH0_CC_I TIMERx_CC_INT Capture INT From Other Channal CH0CAPPSC Edge selector inverter Based on CH0P CH0NP CI0FE0 Rising Falling ITI0 ITI3 ITI1 ITI2 CI0FED Rising Falling IS0 CI0FED First the channel input signal CIx is synchronized to TIMER_C...

Page 346: ...in the channel control register TIMERx_CHCTL0 and set capture on rising edge Select channel 1 capture signal to CI0 by setting CH1MS to 2 b10 in the channel control register TIMERx_CHCTL0 and set capture on falling edge The counter set to restart mode and restart on channel 0 rising edge Then the TIMERX_CH0CV can measure the PWM period and the TIMERx_CH1CV can measure the PWM duty Output compare m...

Page 347: ...CPRE PWM mode In the output PWM mode by setting the CHxCOMCTL bits to 3 b110 PWM mode0 or to 3 b 111 PWM mode1 the channel can outputs PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers Based on the counter mode we have can also divide PWM into EAPWM Edge aligned PWM and CAPWM Centre aligned PWM The EAPWM period is determined by TIMERx_CAR and duty cycle is by TIMERx_CHx...

Page 348: ...to zero the output will be always inactive under PWM mode0 CHxCOMCTL 3 b110 Figure 17 33 EAPWM timechart 0 CHxVAL CAR PWM MODE0 PWM MODE1 Cx OUT Cx OUT Interrupt signal CHxIF CHxOF Figure 17 34 CAPWM timechart 0 CHxVAL CAR PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF CHxOF CAM 2 b01 down only CAM 2 b10 up only CHxIF CHxOF CAM 2 b11 up down CHxIF CHxOF ...

Page 349: ...tive active level irrespective of the comparison condition between the counter and the TIMERx_CHxCV values The OxCPRE signal can be forced to 0 when the ETIFE signal is derived from the external ETI pin and when it is set to a high level by setting the CHxCOMCEN bit to 1 in the TIMERx_CHCTL0 register The OxCPRE signal will not return to its active level until the next update event occurs Slave con...

Page 350: ...0 61 62 63 00 01 02 03 04 00 01 02 UPIF ITI0 TRGIF Internal sync delay Exam2 Pause mode The counter can be paused when the trigger input is low TRGS 2 0 3 b101 CI0FE0 is the selection TI0S 0 Non xor CH0NP 0 CH0P 0 no inverted Capture will be sensitive to the rising edge only Filter is bypass in this example Figure 17 36 Pause mode TIMER_CK CEN CNT_REG 5E 5F 60 61 62 CI0 TRGIF CI0FE0 63 Exam3 Event...

Page 351: ...keep the CEN bit at a high state until the update event occurs or the CEN bit is written to 0 by software If the CEN bit is cleared to 0 using software the counter will be stopped and its value held If the CEN bit is automatically cleared to 0 by a hardware update event the counter will be reinitialized In the single pulse mode the trigger active edge which sets the CEN bit to 1 will enable the co...

Page 352: ...0x60 TIMER_CK CNT_CLK CEN CNT_REG 00 01 02 03 04 05 5F 60 00 O2CPRE CI3 Under SPM counter stop Timers interconnection Refer to Timers interconnection Timer debug mode When the Cortex M23 halted and the TIMERx_HOLD configuration bit in DBG_CTL2 register set to 1 the TIMERx counter stops ...

Page 353: ...ER_CK and the dead time and sampling clock DTS which is used by the dead time generators and the digital filters 00 fDTS fTIMER_CK 01 fDTS fTIMER_CK 2 10 fDTS fTIMER_CK 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 4 Reserved Must be kept at reset value 3 SPM Single pulse mode 0 Co...

Page 354: ... Counter disable 1 Counter enable The CEN bit must be set by software when timer works in external clock pause mode and encoder mode While in event mode the hardware can set the CEN bit automatically Slave mode configuration register TIMERx_SMCFG Address offset 0x08 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 1...

Page 355: ...d 100 Restart mode The counter is reinitialized and the shadow registers are updated on the rising edge of the selected trigger input 101 Pause mode The trigger input enables the counter clock when it is high and disables the counter when it is low 110 Event mode A rising edge of the trigger input enables the counter The counter cannot be disabled by the slave mode controller 111 External clock mo...

Page 356: ... rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31 11 Reserved Must be kept at reset value 10 CH1OF Channel 1 over capture flag Refer to CH0OF description 9 CH0OF Channel 0 over capture flag When channel 0 is configured in input mode this flag is set by hardware when a capture event occurs while CH0IF flag has already been set This flag is cleared by software 0 No over capture interr...

Page 357: ...e on an update event and cleared by software 0 No update interrupt occurred 1 Update interrupt occurred Software event generation register TIMERx_SWEVG Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRGG Reserved CH1G CH0G UPG w w w w Bits Fields Desc...

Page 358: ...enerate an update event 1 Generate an update event Channel control register 0 TIMERx_CHCTL0 Address offset 0x18 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH1COMCTL 2 0 CH1CO MSEN CH1CO MFEN CH1MS 1 0 Reserved CH0COMCTL 2 0 CH0CO MSEN CH0CO MFEN CH0MS 1 0 CH1CAPFLT 3...

Page 359: ... compare register TIMERx_CH0CV 100 Force low O0CPRE is forced low level 101 Force high O0CPRE is forced high level 110 PWM mode0 When counting up O0CPRE is active as long as the counter is smaller than TIMERx_CH0CV else inactive When counting down O0CPRE is inactive as long as the counter is larger than TIMERx_CH0CV else active 111 PWM mode1 When counting up O0CPRE is inactive as long as the count...

Page 360: ... Channel 0 is configured as output 01 Channel 0 is configured as input IS0 is connected to CI0FE0 10 Channel 0 is configured as input IS0 is connected to CI1FE0 11 Channel 0 is configured as input IS0 is connected to ITS This mode is working only if an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register Input capture mode Bits Fields Descriptions 31 16 Reserved Must be ke...

Page 361: ... edges 11 Capture is done every 8 channel input edges 1 0 CH0MS 1 0 Channel 0 mode selection Same as Output compare mode Channel control register 2 TIMERx_CHCTL2 Address offset 0x20 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH1NP Reserved CH1P CH1EN...

Page 362: ...e active signal for capture or trigger operation in slave mode And CIxFE0 will not be inverted CH0NP 0 CH0P 1 CIxFE0 s falling edge is the active signal for capture or trigger operation in slave mode And CIxFE0 will be inverted CH0NP 1 CH0P 0 Reserved CH0NP 1 CH0P 1 CIxFE0 s falling and rising edge are both the active signal for capture or trigger operation in slave mode And CIxFE0 will be not inv...

Page 363: ... 0 PSC 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 PSC 15 0 Prescaler value of the counter clock The PSC clock is divided by PSC 1 to generate the counter clock The value of this bit filed will be loaded to the corresponding shadow register at every update event Counter auto reload register TIMERx_CAR Address offset 0x2C Reset value 0x0000 0000 This register ha...

Page 364: ...utput mode this bit filed contains value to be compared to the counter When the corresponding shadow register is enabled the shadow register updates every update event Channel 1 capture compare value register TIMERx_CH1CV Address offset 0x38 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4...

Page 365: ...0 01 Channel 0 input is connected to the LXTAL 10 Channel 0 input is connected to HXTAL 32 clock 11 Channel 0 input is connected to CKOUTSEL Channel input remap register TIMERx_IRMP x 11 Address offset 0x50 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CI0_RMP 1 0 rw Bi...

Page 366: ...19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CHVSEL Reserved rw rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 CHVSEL Write CHxVAL register selection This bit field set and reset by software 1 If write the CHxVAL register the write value is same as the CHxVAL value the write access ignored 0 No effect 0 Reserved Must be kept at reset value ...

Page 367: ...e mode is supported Auto reload function Interrupt output or DMA request on update event 17 3 3 Block diagram Figure 17 39 Basic timer block diagram provides details on the internal configuration of the basic timer Figure 17 39 Basic timer block diagram PSC Trigger processor Trigger Selector Counter Counter Register Interrupt Register set and update Interrupt collector APB BUS CK_TIMER CAR TIMERx_...

Page 368: ... Normal mode internal clock divided by 1 CK_TIMER CEN PSC_CLK TIMER_CK CNT_REG Reload Pulse 17 18 19 20 21 22 update event generate UPG 23 00 01 02 03 04 05 06 07 Update event UPE Prescaler The prescaler can divide the timer clock TIMER_CK to a counter clock PSC_CLK by any factor ranging from 1 to 65536 It is controlled by prescaler register TIMERx_PSC which can be changed ongoing but it is adopte...

Page 369: ...e counter restarts to count once again from 0 The update event is generated at each counter overflow When the update event is set by the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and generates an update event If set the UPDIS bit in TIMERx_CTL0 register the update event is disabled When an update event occurs all the registers repetition counter auto reload re...

Page 370: ..._CLK PSC_CLK CNT_REG 5E 5F 60 61 62 63 00 01 02 03 04 05 06 07 Update event UPE Update interrupt flag UPIF CNT_REG 5F 60 Update event UPE Update interrupt flag UPIF Hardware set Software clear Hardware set TIMERx_PSC PSC 0 TIMERx_PSC PSC 1 TIMER_CK 08 63 62 61 00 01 02 03 CNT_CLK PSC_CLK ...

Page 371: ... Auto reload register 65 63 change CAR Vaule CNT_REG 5E 5F 60 61 62 63 64 65 00 01 02 62 63 00 Update event UPE Update interrupt flag UPIF Auto reload register 65 63 change CAR Vaule 65 63 Auto reload shadow register Hardware set Hardware set Software clear Hardware set ARSE 0 ARSE 1 Timer debug mode When the Cortex M23 halted and the TIMERx_HOLD configuration bit in DBG_CTL register set to 1 the ...

Page 372: ...enabled 6 4 Reserved Must be kept at reset value 3 SPM Single pulse mode 0 Single pulse mode disable Counter continues after update event 1 Single pulse mode enable The CEN is cleared by hardware and the counter stops at next update event 2 UPS Update source This bit is used to select the update event sources by software 0 When enabled any of the following events generate an update interrupt or DM...

Page 373: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MMC 2 0 Reserved rw Bits Fields Descriptions 31 7 Reserved Must be kept at reset value 6 4 MMC 2 0 Master mode control These bits control the selection of TRGO signal which is sent in master mode to slave timers for synchronization function 000 Reset When the UPG bit in the TIMERx_SWEVG register is set or a reset is generated by the slave mode controlle...

Page 374: ... Reserved UPDEN Reserved UPIE rw rw Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 UPDEN Update DMA request enable 0 disabled 1 enabled 7 1 Reserved Must be kept at reset value 0 UPIE Update interrupt enable 0 disabled 1 enabled Interrupt flag register TIMERx_INTF Address offset 0x10 Reset value 0x0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23...

Page 375: ... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UPG w Bits Fields Descriptions 31 1 Reserved Must be kept at reset value 0 UPG Update event generation This bit can be set by software and cleared by hardware automatically When this bit is set the counter is cleared The prescaler counter is cleared at the same time 0 No generate an update event 1 Generate an update event Counter register TIMERx_CNT ...

Page 376: ...rved Must be kept at reset value 15 0 PSC 15 0 Prescaler value of the counter clock The PSC clock is divided by PSC 1 to generate the counter clock The value of this bit filed will be loaded to the corresponding shadow register at every update event Counter auto reload register TIMERx_CAR Address offset 0x2C Reset value 0x0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24...

Page 377: ... and it is suitable for realizing timeout function with very low power consumption 18 2 Characteristics Counter width 32 bit Source of counter clock is selectable Internal clock an Internal 16 MHz RC oscillator IRC16M an Internal 32 KHz RC oscillator IRC32K a 32 768 KHz Low Speed crystal oscillator LXTAL or an APB2 clock PCLK2 External clock the sources through LPTIMER external input 0 used as a p...

Page 378: ... 4 1 Clock selection The LPTIMER can be clocked by several clock sources It can be clocked using an internal clock signal which can be chosen among internal 16 MHz RC oscillator IRC16M internal 32 KHz RC oscillator IRC32K 32 768 KHz Low Speed crystal oscillator LXTAL APB2 clock PCLK2 sources through the Reset and clock unit RCU LPTIMER can also use an external clock signal on its external input 0 ...

Page 379: ...nal clock signal should also be provided Case 0 In this case the internal clock signal frequency should be at least four times the frequency of the external clock signal The clock modes below can be selected depending on CKSSEL and CNTMEN values CKSSEL 0 the LPTIMER is clocked by an internal clock source Internal clock mode 0 CNTMEN 0 The LPTIMER is configured to be clocked by an internal clock so...

Page 380: ...register is used to enable disable the LPTIMER core logic After the LPTEN bit is set to 1 it is necessary to delay two LPTIMER_CK clocks before the LPTIMER is actually enabled The LPTIMER_CTL0 and LPTIMER_INTEN registers except for INHLCOIE and HLCMVUPIF bit must be modified only when the LPTIMER is disabled 18 4 3 Prescaler The prescaler can divide the timer clock LPTIMER_CK to the counter clock ...

Page 381: ...itivity depends on the number of consecutive equal samples that should be detected on the LPTIMER input and treats the signal level change as a valid transition Figure 18 4 Input filter timing diagram ECKFLT 2 b01 shows an example of the input filter behavior in case of a 2 consecutive samples programmed Figure 18 4 Input filter timing diagram ECKFLT 2 b01 CK_LPTIMER Filter_OUT LPTIMER_IN ignored ...

Page 382: ...r is completed 18 4 6 Start counting mode The LPTIMER counter may be started either by software or after the detection of an active edge on one of the 8 trigger inputs ETMEN 1 0 is used to configure the trigger mode of LPTIMER ETMEN 1 0 2 b 00 The LPTIMER counter is started as soon as the CTNMST bit or SMST bit is set by software ETMEN 1 0 2 b00 ETSEL 2 0 is used to select which of the 8 trigger i...

Page 383: ... disabled Single counting mode the LPTIMER is started from a trigger event software trigger or external trigger and stops when reaching the value of CARL 31 0 bits in LPTIMER_CAR register Single counting mode The SMST bit is set to 1 to enable the the single counting mode In this mode a new trigger event will restart the LPTIMER Any trigger event that occurs after the counter is started and before...

Page 384: ...nored ignored If ETMEN 1 0 2 b 00 the software trigger is enabled setting the SMST bit will start the counter for single counting mode Continuous counting mode The CTNMST bit is set to 1 to enable the the continuous counting mode If an external trigger is selected to start LPTIMER counter an external trigger event that arrives after the CTNMST bit is set will start the counter for continuous count...

Page 385: ...oad register and LPTIMER_CMPV compare value register are used to generate several different waveforms on LPTIMER output The LPTIMER can generate the following waveforms PWM mode the LPTIMER output is set as soon as a match occurs between the value of LPTIMER_CMPV and the LPTIMER_CNT registers The LPTIMER output is reset as soon as a match occurs between the value of LPTIMER_CAR and the LPTIMER_CNT...

Page 386: ...hows the effect of the polarity change with the OPSEL bit Figure 18 9 LPTIMER_O output mode with OPSEL bit CARL 31 0 CMPVAL 31 0 COUNT PWM Single pulse mode Set mode Set mode PWM Single pulse mode OPSEL 0 OPSEL 1 18 4 10 Timeout function By setting the TIMEOUT bit a valied edge detected on a selected trigger input can be used to reset the LPTIMER counter The first trigger event will start the time...

Page 387: ...to interact with each other to generate the counter value At first the CTNMST bit is set to 1 to enable the the continuous counting mode and the DECMEN bit is set to 1 to enable the decoder mode Then setting DECMSEL 0 to select that the decoder mode 0 and setting the CKPSEL 1 0 2b 00 2b 01 or 2b 10 to select that the timer counting is determined only by the rising edge only by falling edge or both...

Page 388: ...IN1F Rising Falling Rising Falling Decoder rising edge mode IN0F High x x Up IN0F Low x x Down IN1F High Down x x IN1F Low Up x x Decoder falling edge mode IN0F High x x Down IN0F Low x x Up IN1F High Up x x IN1F Low Down x x Decoder both edge mode IN0F High x x Up Down IN0F Low x x Down Up IN1F High Down Up x x IN1F Low Up Down x x Note means no counting x means impossible Figure 18 11 Counter op...

Page 389: ...elect that the decoder mode 1 and setting the CKPSEL 1 0 2b 00 2b 01 to select that the inputs of LPTIMER_IN0 and LPTIMER_IN1 are non inverted or inverted When two non overlap pulses appear in IN0FP and IN1FP in sequence the counter will increment once Figure 18 13 Counter operation in decoder mode 1 with non inverted shows two waveform timing diagrams for the counter can count correctly in decode...

Page 390: ...hip in Figure 18 13 Counter operation in decoder mode 1 with non inverted the counter cannot count Depending on the input wavefroms the corresponding interrupt flags will be set IN1EIF IN0EIF INRFOEIF INHLOEIF and the interrupts will generated if enabled by IN1EIE IN0EIE INRFOEIE or INHLOEIE in LPTIMER_INTEN register Figure 18 14 Counter operation in decoder mode 1 with non inverted IN1EIF IN1FP I...

Page 391: ...ter 0 CARL INRFOEIF IN0FP IN1FP Counter 0 CARL Figure 18 17 Counter operation in decoder mode 1 with non inverted INHLOEIF INHLOEIF IN0FP IN1FP Counter 0 CARL INHLOEIF IN0FP IN1FP Counter 0 CARL INHLOEIF IN1FP IN0FP Counter 0 CARL INHLOEIF IN1FP IN0FP Counter 0 CARL Note that when the LPTIMER used in decoder modes an internal clock signal should also be provided CKSSEL 0 and the internal clock of ...

Page 392: ...PVUPIF flag in the LPTIMER_INTF register are respectively used to indicate when the write operation to the LPTIMER_CAR register and the LPTIMER_CMPV register is completed After the LPTIMER_CAR register or the LPTIMER_CMPV register is written only the previous write operation is completed a new write operation to the same register can be performed Any continuous write operations performed before th...

Page 393: ...id Table 18 5 LPTIMER interrupt events Interrupt event Description LPTIMER_IN1 error Interrupt flag is set when the signal of LPTIMER_IN1 does not jump between the two consecutive rising edges of LPTIMER_IN0 just used in decoder mode 1 LPTIMER_IN0 error Interrupt flag is set when the signal of LPTIMER_IN0 does not jump between the two consecutive rising edges of LPTIMER_IN1 just used in decoder mo...

Page 394: ...egister update Interrupt flag is set when the APB bus write operation to the LPTIMER_CMPV register has been successfully completed External trigger edge event Interrupt flag is set when an external trigger active edge event is detected Counter auto reload register match Interrupt flag is set when the value of the Counter register LPTIMER_CNT matches the value of the Counter auto reload register LP...

Page 395: ...LPTIMER_IN0 error interrupt flag This flag is set by hardware when the signal of LPTIMER_IN0 does not jump between the two consecutive rising edges of LPTIMER_IN1 IN0EIF flag can be cleared by writing 1 to the IN0EIC bit in the INTC register Note This flag just used in decoder mode 1 29 INRFOEIF The falling and rising edges of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt flag This flag is s...

Page 396: ...writing 1 to the UPIC bit in the INTC register 4 CARUPIF Counter auto reload register update interrupt flag This flag is set by hardware when the APB bus write operation to the LPTIMER_CAR register has been successfully completed CARUPIF flag can be cleared by writing 1 to the CARUPIC bit in the INTC register 3 CMPVUPIF Compare value register update interrupt flag This flag is set by hardware when...

Page 397: ...this bit to clear the INRFOEIF flag and write 0 has no effect 28 INHLOEIC The high level of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt flag clear bit Write 1 to this bit to clear the INHLOEIF flag and write 0 has no effect 27 INHLCOIC LPTIMER_INx x 0 1 high level counter overflow interrupt flag clear bit Write 1 to this bit to clear the INHLCOIF flag and write 0 has no effect 26 HLCMVUPIC...

Page 398: ...to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IN1EIE IN0EIE INRFOEIE INHLOEIE INHLCOIE HLCMV UPIE Reserved rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DOWNIE UPIE CARUPIE CMPV UPIE ETED EVIE CARMIE CMPV MIE rw rw rw rw rw rw rw Bits Fields Descriptions 31 IN1EIE LPTIMER_IN1 error interrupt enable bit 0 disabled 1 enabled This bit can be modified...

Page 399: ...L1 register is 0 25 7 Reserved Must be kept at reset value 6 DOWNIE LPTIMER counter direction change up to down interrupt enable bit 0 disabled 1 enabled This bit can be modified only when the LPTIMER is disabled The LPTEN bit in LPTIMER_CTL1 register is 0 5 UPIE LPTIMER counter direction change down to up interrupt enable bit 0 disabled 1 enabled This bit can be modified only when the LPTIMER is ...

Page 400: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved DECMSEL DECMEN CNTMEN SHWEN OPSEL OMSEL TIMEOUT ETMEN 1 0 Reserved rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETSEL 2 0 Reserved PSC 2 0 Reserved TFLT 1 0 Reserved ECKFLT 1 0 CKPSEL 1 0 CKSSEL rw rw rw rw rw rw Bits Fields Descriptions 31 26 Reserved Must be kept at reset value 25 DECMSEL Decoder mode select 0 Decoder mode 0 1 Dec...

Page 401: ...The output is set as long as the counter is match the value of LPTIMER_CAR This bit can be modified only when the LPTIMER is disabled The LPTEN bit in LPTIMER_CTL1 register is 0 20 OMSEL Output Mode select This bit is used to controls the output mode 0 PWM mode or single pulse mode CTNMST bit for PWM mode and SMST for single pulse mode 1 Set mode This bit can be modified only when the LPTIMER is d...

Page 402: ...mer clock LPTIMER_CK to a counter clock PSC_CLK 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 These bits can be modified only when the LPTIMER is disabled The LPTEN bit in LPTIMER_CTL1 register is 0 8 Reserved Must be kept at reset value 7 6 TFLT 1 0 Trigger filter The TFLT bits are used to configure the digital filter for triggers An internal clock source must be used in this function 00 F...

Page 403: ... configured in decoder mode 1 DECMEN 1 DECMSEL 1 the inputs of LPTIMER_IN0 and LPTIMER_IN1 are non inverted If the LPTIMER external input high level counter enable INHLCEN 1 the inputs of LPTIMER_IN0 and LPTIMER_IN1 are non inverted 01 the falling edge is the active edge used for counting If the LPTIMER is configured in decoder mode 0 the decoder falling edge mode is active If the LPTIMER is confi...

Page 404: ...17 16 INHLCEN LPTENF Reserved rw r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CTNMST SMST LPTEN rw rw rw Bits Fields Descriptions 31 INHLCEN LPTIMER external input high level counter enable 0 disabled 1 enabled 30 LPTENF LPTIMER enabled from LPTIMER core flag This bit is set and reset by hardware 0 LPTIMER is disabled 1 LPTIMER is enabled 29 3 Reserved Must be kept at reset value 2 CTNMST LPTI...

Page 405: ...d specifies the compare value of the counter This bit can be modified only when the LPTIMER is enabled The LPTEN bit in LPTIMER_CTL1 register is 1 18 5 7 Counter auto reload register LPTIMER_CAR Address offset 0x18 Reset value 0x0001 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CARL 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CARL 15 0 rw Bits ...

Page 406: ...ssary to perform two consecutive read accessesand verify that the two returned values are identical 18 5 9 External input remap register LPTIMER_EIRMP Address offset 0x20 Reset value 0x0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IN1_RMP IN0_RMP rw rw Bits Fields Descriptions 31 2 Reserv...

Page 407: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved INHLCMVAL 25 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INHLCMVAL 15 0 rw Bits Fields Descriptions 31 26 Reserved Must be kept at reset value 25 0 INHLCMVAL Input high level counter max value This bit can be modified only when the LPTIMER is external input high level counter enabled The INHLCEN bit in LPTIMER_CTL1 register is 1 ...

Page 408: ...de and hardware flow control protocol CTS RTS The data frame can be transferred from LSB or MSB bit The polarity of the TX RX pins can be configured independently and flexibly All USARTs support DMA function for high speed data communication 19 2 Characteristics NRZ standard format Asynchronous full duplex communication Half duplex single wire communications Receive FIFO function Dual clock domain...

Page 409: ... RFF Transmit buffer empty TBE transfer complete TC Flags for error detection overrun error ORERR noise error NERR frame error FERR and parity error PERR Flag for hardware flow control CTS changes CTSF Flag for LIN mode LIN break detected LBDF Flag for multiprocessor communication IDLE frame detected IDLEF Flag for ModBus communication Address character match AMF and receiver timeout RTF Flags for...

Page 410: ...gister Receive Shift Register USART Control Registers CK Transimit Controler Hardware Flow Controler nRTS nCTS Receiver Controler USART Address Wakeup Unit USART Guard Time and Prescaler Register USART Status Register USART Interrupt Controler USARTDIV 8 2 OVSMOD USART Baud Rate Register UCLK Transmitter clock Receiver clock Write Buffer Read Buffer Read FiFO 19 3 1 USART frame format The USART fr...

Page 411: ...wed by the configured number of stop bits The transfer speed of a USART frame depends on the frequency of the UCLK the configuration of the baud rate generator and the oversampling mode 19 3 2 Baud rate generation The baud rate divider is a 16 bit number which consists of a 12 bit integer and a 4 bit fractional part The number formed by these two values is used by the baud rate generator to determ...

Page 412: ...ritten to the USART_TDATA register while a transmission is ongoing it will be firstly stored in the transmit buffer and transferred to the transmit shift register after the current transmission is done If a data is written to the USART_TDATA register while no transmission is ongoing the TBE bit will be cleared and set soon because the data will be transferred to the transmit shift register immedia...

Page 413: ...ate in USART_BAUD 5 Set the UEN bit in USART_CTL0 to enable the USART 6 Set the REN bit in USART_CTL0 After being enabled the receiver receives a bit stream after a valid start pulse has been detected Detection on noisy error parity error frame error and overrun error is performed during the reception of a frame When a frame is received the RBNE bit in USART_STAT is asserted an interrupt is genera...

Page 414: ...he RX pin is evaluated as 0 during a stop bit the frame error FERR bit in USART_STAT register will be set An interrupt is generated If the ERRIE bit in USART_CTL2 register is set According to the configuration of the stop bit there are the following situations 0 5 stop bit When 0 5 stop bit stop bit is not sampled 1 stop bit When 1 stop bit sampling in the middle of stop bit 1 5 stop bits When 1 5...

Page 415: ... address of USART_TDATA as the DMA destination address Set the address of data in internal sram as the DMA source address Set the number of data as the DMA transfer number Set other configurations of DMA interrupt enable priority etc Clear the TC bit in USART_STAT Enable the DMA channel for USART Wait the TC bit to be set After all of the data frames are transmitted the TC bit in USART_STAT is set...

Page 416: ...annel for USART When the number of the data received by USART reaches the DMA transfer number an end of transfer interrupt can be generated in the DMA module 19 3 6 Hardware flow control The hardware flow control function is realized by the nCTS and nRTS pins The RTS flow control is enabled by writing 1 to the RTSEN bit in USART_CTL2 and the CTS flow control is enabled by writing 1 to the CTSEN bi...

Page 417: ...ing bit DEM in the USART_CTL2 control register allows the user to activate the external transceiver control through the DE Driver Enable signal The assertion time which is programmed using the DEA 4 0 bits field in the USART_CTL0 control register is the time between the activation of the DE signal and the beginning of the START bit The de assertion time which is programmed using the DED 4 0 bits f...

Page 418: ...address bit If the ADDM bit is set and the receive frame is a 7bit data the LSB 6 bits will be compared with ADDR 5 0 If the ADDM bit is set and the receive frame is a 9bit data the LSB 8 bits will be compared with ADDR 7 0 Note If the MEN bit is set the WM bit is reset and the RWU bit is reset an idle frame is detected on the RX pin the IDLEF bit will be set If the RWU bit is set the IDLEF is not...

Page 419: ...e only activated when the TEN bit is enabled No clock pulse will be sent through the CK pin during the transmission of the start bit and stop bit The CLEN bit in USART_CTL1 can be used to determine whether the clock is output or not during the last address flag bit transmission The clock output is also not activated during idle and break frame sending The CPH bit in USART_CTL1 can be used to deter...

Page 420: ... transmitted to the infrared LED through the TX pin The SIR receive decoder receives the modulated signal from the infrared LED through the RX pin and puts the demodulated data frame to the USART receiver The baud rate should not be larger than 115200 for the encoder Figure 19 13 IrDA SIR ENDEC module Normal USART Transmit Encoder Receive Decoder SIR MODULE TX RX TX pin RX pin IREN 1 0 0 1 Infrare...

Page 421: ...n mode The half duplex communication mode is enabled by setting the HDEN bit in USART_CTL2 The LMEN CKEN bits in USART_CTL1 and SCEN IREN bits in USART_CTL2 should be cleared in half duplex communication mode Only one wire is used in half duplex mode The TX and RX pins are connected together internally The TX pin should be configured as IO pin The conflicts should be controlled by the software Whe...

Page 422: ...ts The USART can automatically resend data according to the protocol for SCRTNUM times An interframe gap of 2 5 bits time will be inserted before the start of a resented frame At the end of the last repeated character the TC bit is set immediately without guard time The USART will stop transmitting and assert the frame error status if it still receives the NACK signal after the programmed number o...

Page 423: ...is register field must be programmed to the minimum value 0x0 before the start of the block when using DMA mode With this value an interrupt is generated after the 4th received character The software must read the third byte as block length from the receive buffer In interrupt driven receive mode the length of the block may be checked by software or by programming the BL value However before the s...

Page 424: ...ster must be set The USART_RT register must be set to the value corresponding to a timeout of 2 characters time After the last stop bit is received when the receive line is idle for this duration an interrupt will be generated informing the software that the current block reception is completed In the ModBus ASCII mode the end of a block is recognized by a specific CR LF character sequence The USA...

Page 425: ... disabled before entering Deep sleep mode Before entering Deep sleep mode software must check that the USART is not performing a transfer by checking the BSY flag in the USART_STAT register The REA bit must be checked to ensure the USART is actually enabled When the wakeup event is detected the WUF flag is set by hardware and a wakeup interrupt is generated if the WUIE bit is set independently of ...

Page 426: ... together before being sent to the interrupt controller so the USART can only generate a single interrupt request to the controller at any given time Software can service multiple interrupt events in a single interrupt service routine Figure 19 17 USART interrupt mapping diagram IDLEF IDLEIE RBNE RBNEIE ORERR RBNEIE PERR PERRIE WUF WUIE LBDF LBDIE AMF AMIE RTF RTIE EBF EBIE FERR NERR ORERR ERRIE O...

Page 427: ...nterrupt is disabled 1 End of Block interrupt is enabled This bit is reserved in UART3 and UART4 26 RTIE Receiver timeout interrupt enable 0 Receiver timeout interrupt is disabled 1 Receiver timeout interrupt is enabled This bit is reserved in UART3 and UART4 25 21 DEA 4 0 Driver Enable assertion time These bits are used to define the time between the activation of the DE Driver Enable signal and ...

Page 428: ...k This bit field cannot be written when the USART is enabled UEN 1 10 PCEN Parity control enable 0 Parity control disabled 1 Parity control enabled This bit field cannot be written when the USART is enabled UEN 1 9 PM Parity mode 0 Even parity 1 Odd parity This bit field cannot be written when the USART is enabled UEN 1 8 PERRIE Parity error interrupt enable 0 Parity error interrupt is disabled 1 ...

Page 429: ...leep mode Providing that the clock source for the USART must be IRC16M or LXTAL This bit is reserved in UART3 and UART4 0 UEN USART enable 0 USART prescaler and outputs disabled 1 USART prescaler and outputs enabled 19 4 2 Control register 1 USART_CTL1 Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR 7 ...

Page 430: ... bit is reserved in UART3 and UART4 20 ABDEN Auto baud rate enable 0 Auto baud rate detection is disabled 1 Auto baud rate detection is enabled This bit is reserved in UART3 and UART4 19 MSBF Most significant bit first 0 Data is transmitted received with the LSB first 1 Data is transmitted received with the MSB first This bit field cannot be written when the USART is enabled UEN 1 18 DINV Data bit...

Page 431: ...de 1 Steady high value on CK pin outside transmission window in synchronous mode This bit field cannot be written when the USART is enabled UEN 1 9 CPH Clock phase 0 The first clock transition is the first data capture edge in synchronous mode 1 The second clock transition is the first data capture edge in synchronous mode This bit field cannot be written when the USART is enabled UEN 1 8 CLEN CK ...

Page 432: ...essed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved WUIE WUM 1 0 SCRTNUM 2 0 Reserved rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEP DEM DDRE OVRD OSB CTSIE CTSEN RTSEN DENT DENR SCEN NKEN HDEN IRLP IREN ERRIE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 23 Reserved Must be kept at reset value 22 WUIE Wakeup from Deep sleep mode interrup...

Page 433: ...he RTS pin 0 DE function is disabled 1 DE function is enabled This bit field cannot be written when the USART is enabled UEN 1 13 DDRE Disable DMA on reception error 0 DMA is not disabled in case of reception error The DMA request is not asserted to make sure the erroneous data is not transferred but the next correct received data will be transferred The RBNE is kept 0 to prevent overrun but the c...

Page 434: ... bit field cannot be written when the USART is enabled UEN 1 7 DENT DMA enable for transmission 0 DMA mode is disabled for transmission 1 DMA mode is enabled for transmission 6 DENR DMA enable for reception 0 DMA mode is disabled for reception 1 DMA mode is enabled for reception 5 SCEN Smartcard mode enable 0 Smartcard Mode disabled 1 Smartcard Mode enabled This bit field cannot be written when th...

Page 435: ...his register has to be accessed by word 32 bit This register cannot be written when the USART is enabled UEN 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BRR 15 4 BRR 3 0 rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 4 BRR 15 4 Integer of baud rate divider DIV_INT 11 0 BRR 15 4 3 0 BRR 3 0 Fraction of baud rate divi...

Page 436: ... by 2 In IrDA normal mode 00000001 can be set this value only In smartcard mode the prescaler value for dividing the system clock is stored in PSC 4 0 bits And the bits of PSC 7 5 must be kept at reset value The division factor is twice as the prescaler value 00000 Reserved do not program this value 00001 divides the source clock by 2 00010 divides the source clock by 4 00011 divides the source cl...

Page 437: ...ode the RTF flag is set if no new start bit is detected for more than the RT value after the last received character In smartcard mode the CWT and BWT are implemented by this value In this case the timeout measurement is started from the start bit of the last received character These bits can be written on the fly The RTF flag will be set if the new value is lower than or equal to the counter Thes...

Page 438: ...ister has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved REA TEA WUF RWU SBF AMF BSY r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ABDF ABDE Reserved EBF RTF CTS CTSF LBDF TBE TC RBNE IDLEF ORERR NERR FERR PERR r r r r r r r r r r r r r r r Bits Fields Descriptions 31 23 Reserved Must be kept at reset value 22 REA Receive enable acknowledge flag This b...

Page 439: ...be transmitted This bit indicates that a send break character was requested Set by software by writing 1 to the SBKCMD bit in the USART_CMD register Cleared by hardware during the stop bit of break transmission 17 AMF ADDR match flag 0 ADDR does not match the received character 1 ADDR matches the received character An interrupt is generated if AMIE 1 in the USART_CTL0 register Set by hardware when...

Page 440: ...munication Cleared by writing 1 to RTC bit in USART_INTC register The timeout corresponds to the CWT or BWT timings in smartcard mode This bit is reserved in UART3 and UART4 10 CTS CTS level This bit equals to the inverted level of the nCTS input pin 0 nCTS input pin is in high level 1 nCTS input pin is in low level 9 CTSF CTS change flag 0 No change occurred on the nCTS status line 1 A change occ...

Page 441: ...FCMD bit of the USART_CMD register 4 IDLEF IDLE line detected flag 0 No Idle Line is detected 1 Idle Line is detected An interrupt will occur if the IDLEIE bit is set in USART_CTL0 Set by hardware when an Idle Line is detected It will not be set again until the RBNE bit has been set itself Cleared by writing 1 to IDLEC bit in USART_INTC register 3 ORERR Overrun error 0 No Overrun error is detected...

Page 442: ... receiver mode Cleared by writing 1 to PEC bit in USART_INTC register 19 4 9 Interrupt status clear register USART_INTC Address offset 0x20 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved WUC Reserved AMC Reserved w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EBC RTC Reserved CTSC LBDC Reserved TCC Reserved IDLEC...

Page 443: ...he USART_STAT register 5 Reserved Must be kept at reset value 4 IDLEC Idle line detected clear Writing 1 to this bit clears the IDLEF bit in the USART_STAT register 3 OREC Overrun error clear Writing 1 to this bit clears the ORERR bit in the USART_STAT register 2 NEC Noise detected clear Writing 1 to this bit clears the NERR bit in the USART_STAT register 1 FEC Frame error flag clear Writing 1 to ...

Page 444: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TDATA 8 0 rw Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 0 TDATA 8 0 Transmit Data value The transmit data character is contained in these bits The value written in the MSB bit 7 or bit 8 depending on the data length will be replaced by the parity when transmitting with the parity is enabled PCEN bit set to 1 in the USART_CTL0 r...

Page 445: ...USART receive FIFO control and status register USART_RFCS Address offset 0xD0 Reset value 0x0000 0400 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFFINT RFCNT 2 0 RFF RFE RFFIE RFEN Reserved ELNACK r_w0 r r r rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 RFFINT Recei...

Page 446: ...O enable 7 1 Reserved Must be kept at reset value 0 ELNACK Early NACK when smartcard mode is selected The NACK pulse occurs 1 16 bit time earlier when the parity error is detected 0 Early NACKdisable when smartcard mode is selected 1 Early NACKenable when smartcard mode is selected This bit is reserved in UART3 and UART4 ...

Page 447: ... RTS The data frame can be transferred from LSB or MSB bit The polarity of the TX RX pins can be configured independently and flexibly LPUART support DMA function for high speed data communication 20 2 Characteristics NRZ standard format Asynchronous full duplex communication Half duplex single wire communications Dual clock domain Asynchronous pclk and LPUART clock Baud rate programming independe...

Page 448: ...and parity error PERR Flag for hardware flow control CTS changes CTSF Flag for multiprocessor communication IDLE frame detected IDLEF Wakeup from Deep sleep mode flag WUF Interrupt occurs at these events when the corresponding interrupt enable bits are set 20 3 Function overview The interface is externally connected to another device by the main pins listed inTable 20 1 Description of LPUART impor...

Page 449: ...PUART Interrupt Controler LPUARTDIV LPUART Baud Rate Register LPUCLK PCLK or CK_SYS or IRC16M or LXTAL Transmitter clock Receiver clock LPUART Modulation Control Register 20 3 1 LPUART frame format The LPUART frame starts with a start bit and ends up with a number of stop bits The length of the data frame is configured by the WL 1 0 bit in the LPUART_CTL0 register refer to Figure 20 2 LPUART chara...

Page 450: ...rt Stop In transmission and reception the number of stop bits can be configured by the STB 1 0 bits in the LPUART_CTL1 register STB 1 0 00 1 stop bit length STB 1 0 10 2 stop bit length In an idle frame all the frame bits are logic 1 The frame length is equal to the normal LPUART frame The break frame structure is a number of low bits followed by 2 stop bits 20 3 2 Baud rate generation The baudrat...

Page 451: ...ansmit buffer and transferred to the transmit shift register after the current transmission is done If a data is written to the LPUART_TDATA register while no transmission is ongoing the TBE bit will be cleared and set soon because the data will be transferred to the transmit shift register immediately If a frame is transmitted and the TBE bit is asserted the TC bit of the LPUART_STAT register wil...

Page 452: ...EN bit in LPUART_CTL0 After being enabled the start bit is detected when a falling edge occurs on the RX line and then samples are taken in the middle of the start bit to confirm whether the level is still 0 If the start sample is 1 the noise error flag NERR is set the start bit will be discarded and the receiver will wait for a new start bit an interrupt is generated if the ERRIE bit in LPUART_CT...

Page 453: ...checked for frame error When a frame is received if the RBNE bit is not cleared yet the last frame will not be stored in the receive data buffer The overrun error ORERR bit in LPUART_STAT register will be set An interrupt is generated if the ERRIE bit in LPUART_CTL2 register is set or if the RBNEIE is set The NERR PERR FERR and ORERR flags are always set at the same time with the RBNE in a recepti...

Page 454: ...LPUART_STAT Enable the DMA channel for LPUART Wait the TC bit to be set After all of the data frames are transmitted the TC bit in LPUART_STAT is set An interrupt occurs if the TCIE bit in LPUART_CTL0 is set When DMA is used for LPUART reception DMA transfers data from the receive data buffer of the LPUART to the internal SRAM The configuration steps are shown in Figure 20 5 Configuration step whe...

Page 455: ...nel for LPUART When the number of the data received by LPUART reaches the DMA transfer number an end of transfer interrupt can be generated in the DMA module 20 3 6 Hardware flow control The hardware flow control function is realized by the nCTS and nRTS pins The RTS flow control is enabled by writing 1 to the RTSEN bit in LPUART_CTL2 and the CTS flow control is enabled by writing 1 to the CTSEN b...

Page 456: ... idle RS485 Driver Enable The driver enable feature which is enabled by setting bit DEM in the LPUART_CTL2 control register allows the user to activate the external transceiver control through the DE Driver Enable signal The assertion time which is programmed using the DEA 4 0 bits field in the LPUART_CTL0 control register is the time between the activation of the DE signal and the beginning of th...

Page 457: ...s frame is the same as the ADDR bits in the LPUART_CTL1 register the hardware will clear the RWU bit and exits the mute mode The RBNE bit will be set when the frame that wakes up the LPUART The status bits are available in the LPUART_STAT register If the LSB 4 7 bits of an address frame defers from the ADDR bits in the LPUART_CTL1 register the hardware sets the RWU bit and enters mute mode automat...

Page 458: ...keup event is detected the WUF flag is set by hardware and a wakeup interrupt is generated if the WUIE bit is set independently of whether the MCU is in stop or active mode 20 3 10 LPUART interrupts The LPUART interrupt events and flags are listed in Table 20 3 LPUART interrupt requests Table 20 3 LPUART interrupt requests Interrupt event Event flag Enable Control bit Transmit data register empty ...

Page 459: ...GD32L23x User Manual 459 Figure 20 8 LPUART interrupt mapping diagram IDLEF IDLEIE RBNE RBNEIE ORERR RBNEIE PERR PERRIE WUF WUIE AMF AMIE FERR NERR ORERR ERRIE OR TC TCIE TBE TBEIE CTSF CTSIE LPUART_INT ...

Page 460: ...a bits WL 1 0 10 7 data bits WL 1 0 11 7 data bits This bit field cannot be written when the LPUART is enabled UEN 1 27 26 Reserved Must be kept at reset value 25 21 DEA 4 0 Driver Enable assertion time These bits are used to define the time between the activation of the DE Driver Enable signal and the beginning of the start bit It is expressed in LPUART CLK cycles This bit field cannot be written...

Page 461: ...be written when the LPUART is enabled UEN 1 8 PERRIE Parity error interrupt enable 0 Parity error interrupt is disabled 1 An interrupt will occur whenever the PERR bit is set in LPUART_STAT 7 TBEIE Transmitter register empty interrupt enable 0 Interrupt is inhibited 1 An interrupt will occur whenever the TBE bit is set in LPUART_STAT 6 TCIE Transmission complete interrupt enable If this bit is set...

Page 462: ...register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR 7 0 Reserved MSBF DINV TINV RINV rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STRP Reserved STB 1 0 Reserved ADDM Reserved rw rw rw Bits Fields Descriptions 31 24 ADDR 7 0 Address of the LPUART terminal These bits give the address of the LPUART terminal In multiprocessor communication during mut...

Page 463: ...e inverted This bit field cannot be written when the LPUART is enabled UEN 1 15 STRP Swap TX RX pins 0 The TX and RX pins functions are not swapped 1 The TX and RX pins functions are swapped This bit field cannot be written when the LPUART is enabled UEN 1 14 Reserved Must be kept at reset value 13 12 STB 1 0 STOP bits length 00 1 Stop bit 01 1 Stop bits 10 2 Stop bits 11 2 Stop bits This bit fiel...

Page 464: ... interrupt is disabled 1 Wakeup from Deep sleep mode interrupt is enabled 21 20 WUM 1 0 Wakeup mode from Deep sleep mode These bits are used to specify the event which activates the WUF Wakeup from Deep sleep mode flag in the LPUART_STAT register 00 WUF active on address match which is defined by ADDR and ADDM 01 Reserved 10 WUF active on start bit 11 WUF active on RBNE This bit field cannot be wr...

Page 465: ... will not be set when received data is not read before receiving new data and the new received data overwrites the previous content of the LPUART_RDATA register This bit field cannot be written when the LPUART is enabled UEN 1 11 Reserved Must be kept at reset value 10 CTSIE CTS interrupt enable 0 CTS interrupt is disabled 1 An interrupt will occur whenever the CTS bit is set in LPUART_STAT 9 CTSE...

Page 466: ...rd 32 bit This register cannot be written when the LPUART is enabled UEN 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved BRR 19 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BRR 15 8 rw Bits Fields Descriptions 31 20 Reserved Must be kept at reset value 19 0 BRR 19 0 The value of LPUARTDIV Note BRR 19 0 0x300 and 3 x baudrate LPUCLK 4096 x baudrate 20 4 5 Command register LPUART_CMD Addre...

Page 467: ...tions 31 23 Reserved Must be kept at reset value 22 REA Receive enable acknowledge flag This bit which is set reset by hardware reflects the receive enable state of the LPUART core logic 0 The LPUART core receiving logic has not been enabled 1 The LPUART core receiving logic has been enabled 21 TEA Transmit enable acknowledge flag This bit which is set reset by hardware reflects the transmit enabl...

Page 468: ... the AMC in the LPUART_INTC register 16 BSY Busy flag 0 LPUART reception path is idle 1 LPUART reception path is working 15 11 Reserved Must be kept at reset value 10 CTS CTS level This bit equals to the inverted level of the nCTS input pin 0 nCTS input pin is in high level 1 nCTS input pin is in low level 9 CTSF CTS change flag 0 No change occurred on the nCTS status line 1 A change occurred on t...

Page 469: ...again until the RBNE bit has been set itself Cleared by writing 1 to IDLEC bit in LPUART_INTC register 3 ORERR Overrun error 0 No Overrun error is detected 1 Overrun error is detected An interrupt will occur if the RBNEIE bit is set in LPUART_CTL0 In multibuffer communication an interrupt will occur if the ERRIE bit is set in LPUART_CTL2 Set by hardware when the word in the receive shift register ...

Page 470: ...CTSC Reserved TCC Reserved IDLEC OREC NEC FEC PEC w w w w w w w Bits Fields Descriptions 31 21 Reserved Must be kept at reset value 20 WUC Wakeup from Deep sleep mode clear Writing 1 to this bit clears the WUF bit in the LPUART_STAT register 19 18 Reserved Must be kept at reset value 17 AMC ADDR match clear Writing 1 to this bit clears the AMF bit in the LPUART_STAT register 16 10 Reserved Must be...

Page 471: ...2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RDATA 8 0 r Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 0 RDATA 8 0 Receive Data value The received data character is contained in these bits The value read in the MSB bit 7 or bit 8 depending on the data length will be the received parity bit if receiving with the...

Page 472: ...t 0xC0 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EPERR Reserved HCM rc_w0 rw Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 EPERR Early parity error flag This flag will be set as soon as the parity bit has been detected which is before RBNE fla...

Page 473: ...col converter and interface Both master and slave functions with the same interface Bi directional data transfer between master and slave Supports 7 bit and 10 bit addressing and general call addressing Multiple 7 bit slave addresses 2 address 1 with configurable mask Programmable setup time and hold time Multi master capability Supports standard mode up to 100 kHz and fast mode up to 400 kHz and ...

Page 474: ...m the bus Master the device which initiates a transfer generates clock signals and terminates a transfer Slave the device addressed by a master Multi master more than one master can attempt to control the bus at the same time without corrupting the message Arbitration procedure to ensure that if more than one master tries to control the bus simultaneously only one is allowed to do so and the winni...

Page 475: ...aster or a slave thus there re 4 operation modes for an I2C device Slave transmitter Slave receiver Master transmitter Master receiver Data validation The data on the SDA line must be stable during the HIGH period of the clock The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW see Figure 21 2 Data validation One clock pulse is generated for each dat...

Page 476: ... is enabled by software the I2C slave always responses to a General Call Address 0x00 The I2C block support both 7 bit and 10 bit address modes Data and addresses are transferred as 8 bit bytes MSB first The first byte s following the START condition contain the address one in 7 bit mode two in 10 bit mode The address is always transmitted in master mode A 9th clock pulse follows the 8 clock cycle...

Page 477: ... bit address Master Receive when HEAD10R 0 In 10 bit addressing mode if the master reception follows a master transmission between the same master and slave the address read sequence can be RESTART header of 10 bit address in read direction as is shown in Figure 21 8 I2C communication flow with 10 bit address Master Receive when HEAD10R 1 Figure 21 7 I2C communication flow with 10 bit address Mast...

Page 478: ...of the SCL or the SDA line is internally changed only if it remains stable for more than DNF 3 0 x tI2CCLK This allows to suppress spikes with a programmable length of 1 to 15 of tI2CCLK 21 3 4 I2C timings The PSC 3 0 SCLDELY 3 0 and SDADELY 3 0 bits in the I2C_TIMING register must be configured in order to guarantee a correct data hold and setup time used in I2C communication If the data is alrea...

Page 479: ...han the maximum of tVD DAT When SS 0 after tSDADELY delay the slave had to stretch the clock before the data writing to I2C_TDATA register SCL is low during the data setup time The setup time is tSCLDELY SCLDELY 1 tPSC tSCLDELY effects tSU DAT SCLDELY must match condition as follows SCLDELY tr max tSUDAT min PSC 1 tI2CCLK 1 In master mode the SCL clock high and low levels must be configured by pro...

Page 480: ...its are START STOP NACKEN in I2C_CTL1 register I2CBSY TBE TI RBNE ADDSEND NACK TCR TC STPDET BERR LOSTARB and OUERR in I2C_STAT register Additionally when the SMBus is supported PECTRANS in I2C_CTL1 register PECERR TIMEOUT and SMBALT in I2C_STAT are also impacted In order to perform the software reset I2CEN must be kept low during at least 3 APB clock cycles This is ensured by writing software seq...

Page 481: ..._RDATA register If RBNE 1 indicates that the previous received data byte has not been read the SCL line is stretched low until I2C_RDATA is read The stretch is inserted between the 8th and 9th SCL pulse before Acknowledge pulse Figure 21 12 Data reception I2C_RDATA SCL Shift register xx data1 xx data2 xx RBNE data0 data1 data2 ACK pulse ACK pulse read data0 read data1 SCL Stretch Hardware transfer...

Page 482: ...en to a non zero value TCR is cleared by software When the BYTENUM counter is reloaded with the last number of bytes RELOAD bit must be cleared When RELOAD 0 in master mode the counter can be used in two modes Automatic end mode AUTOEND 1 in the I2C_CTL1 register In this mode once the number of bytes programmed in the BYTENUM 7 0 bit field has been transferred the master automatically sends a STOP...

Page 483: ...ates after the ADDSEND is set The bit will let the slave to know whether to act as a transmitter or receiver SCL line stretching The clock stretching is used in slave mode by default SS 0 the SCL line can be stretched low if necessary The SCL will be stretched in following cases The SCL is stretched when the ADDSEND bit is set and released when the ADDSEND bit is cleared In slave transmitting mode...

Page 484: ...ing slave byte control mode the reload mode must be enabled by setting the RELOAD bit in I2C_CTL1 register In order to get control of each byte BYTENUM 7 0 in I2C_CTL1 register must be configured as 1 in the ADDSEND interrupt service routine and reloaded to 1 after each byte received The TCR bit in I2C_STAT register will be set when a byte is received the slave stretchs the SCL low between the 8th...

Page 485: ...interrupt will be generated The NACK bit in I2C_STAT register will be set when a NACK is received And an interrupt is generated if the NACKIE bit is set in the I2C_CTL0 register The TI bit in I2C_STAT register will not be set when a NACK is received The STPDET bit in I2C_STAT register will be set when a STOP is received If the STPDETIE in I2C_CTL0 register is set an interrupt will be generated Whe...

Page 486: ...n slave transmitter if a TI event is needed in order to generate a TI event both the TI bit and the TBE bit must be set Figure 21 14 Programming model for slave transmitting when SS 0 IDLE Master generates START condition Master sends Address Slave sends Acknowledge SCL stretched by slave Slave sends DATA 2 Master sends Acknowledge Data transmission Slave sends DATA N 1 Master sends Acknowledge Sl...

Page 487: ...to I2C_TDATA Set TI Write DATA 3 to I2C_TDATA Write DATA 4 to I2C_TDATA Write DATA N to I2C_TDATA Set TI I2C Line State Hardware Action Software Flow Slave sends DATA 1 Master sends Acknowledge Write DATA N 1 to I2C_TDATA DATA N 1 will not be sent Clear STPDET Write DATA 1 to I2C_TDATA Set TI Slave sends DATA N Master don t send ACK Set TI TBE and NACK Clear NACK Set TBE Slave receiver When the I2...

Page 488: ...nchronization the low level of the clock is counted starting from the SCL low level internal detection by the SCLL 7 0 counter the high level of the clock is counted by the SCLH 7 0 counter starting from the SCL high level internal detection The I2C detects its SCL low level after a tSYNC1 delay depending on the SCL falling edge SCL input analog and digital noise filter and SCL synchronization to ...

Page 489: ...set The slave address will be sent after the START condition when the I2CBSY bit I2C_STAT register is detected as 0 When the arbitration is lost the master changes to slave mode and the START bit will be cleared by hardware When the slave address has been sent the START bit will be cleared by hardware In 10 bit addressing mode if the master receives a NACK after the transmission of 10 bit header t...

Page 490: ... The TC bit is cleared when the START STOP bit is set If a NACK is received a STOP condition is automatically generated the NACK is set in I2C_STAT register if the NACKIE bit is set an interrupt will be generated Note When the RELOAD bit is 1 the AUTOEND has no effect Figure 21 18 Programming model for master transmitting N 255 IDLE Master generates START condition Master sends Address Slave sends...

Page 491: ... Set TI Write DATA 2 to I2C_TDATA Write DATA 3 to I2C_TDATA Write DATA N to I2C_TDATA Master sends DATA N 1 Slave sends Acknowledge Set TI Master sends DATA N Slave sends Acknowledge Set TC Master receiver In master receiving mode the RBNE bit in I2C_STAT register will be set when a byte is received If the RBNEIE bit is set in I2C_CTL0 register an interrupt will be generated If the number of bytes...

Page 492: ...TA 1 Master sends Acknowledge Data transmission Slave sends DATA N Master don t send ACK Master generates STOP condition Software initialization Set RBNE Set RBNE Read DATA x Set RBNE Read DATA 1 Slave sends DATA N 1 Master sends Acknowledge Set RBNE Read DATA N set STOP I2C Line State Hardware Action Software Flow Set START Read DATA N 1 AUTOEND 0 BYTENUM 7 0 N ...

Page 493: ...e sends DATA N Master sends Acknowledge Set RBNE Set RBNE TC Read DATA x Set RBNE Read DATA 1 Slave sends DATA N 1 Master sends Acknowledge Set RBNE Read DATA N Read DATA N 1 Set STOP 21 3 9 SMBus support The System Management Bus abbreviated to SMBus or SMB is a single ended simple two wire bus for the purpose of lightweight communication Most commonly it is found in computer motherboards for com...

Page 494: ...e mode the Slave Byte Control mode must be enabled by setting SBCTL bit in I2C_CTL0 register Host Notify protocol When the SMBHAEN bit in the I2C_CTL0 register is set the SMBus supports the Host Notify protocol The host will acknowledge the SMBus Host address When this protocol is used the device acts as a master and the host as a slave Time out feature SMBus has a time out feature which resets de...

Page 495: ...alculator in I2C block to perform Packet Error Checking for I2C data A PEC packet error code byte is appended at the end of each transfer The byte is calculated as CRC 8 checksum calculated over the entire message including the address and read write bit The polynomial used is x8 x2 x 1 the CRC 8 ATM HEC algorithm initialized to zero Setting the PECEN bit in the I2C_CTL0 register will enable the P...

Page 496: ...detection The BUSTOA 11 0 bits must be programmed with the timer reload value to enable the tIDLE check in order to obtain the tIDLE parameter To detect SCL and SDA high level timeouts the TOIDLE bit must be set Then set TOEN in the I2C_TIMEOUT register to enable the timer If the high level time of both SCL and SDA is greater than BUSTOA 1 x 4 x tI2CCLK the TIMEOUT flag is set in the I2C_STAT regi...

Page 497: ... ACK control is not required then PECTRANS can be set to 1 and BYTENUM can be programmed according to the number of bytes to be received Note After the RELOAD bit is set the PECTRANS cannot be changed Figure 21 22 SMBus Master Transmitter and Slave Receiver communication flow Start Slave address ACK DATA0 ACK DATA N 1 ACK Stop data transfer N 1 bytes From master to slave From slave to master W 0 P...

Page 498: ...M will be closed again and the MCU will not be wake up Only an address match interrupt ADDMIE 1 can wakeup the MCU If the clock source of I2C is the system clock or WUEN 0 IRC16M will not switched on after receiving start signal When wakeup from Deep sleep mode is enabled the digital filter must be disabled and the SS bit in I2C_CTL0 must be cleared Before entering Deep sleep mode I2CEN 0 the I2C ...

Page 499: ...rupt event Event flag Enable control bit I2C_RDATA is not empty during receiving RBNE RBNEIE Transmit interrupt TI TIE STOP condition detected in slave mode STPDET STPDETIE Transfer complete reload TCR TCIE Transfer complete TC Address match ADDSEND ADDMIE Not acknowledge received NACK NACKIE Bus error BERR ERRIE Arbitration Lost LOSTARB Overrun Underrun error OUERR PEC error PECERR Timeout error ...

Page 500: ...s 31 24 Reserved Must be kept at reset value 23 PECEN PEC Calculation Switch 0 PEC Calculation off 1 PEC Calculation on 22 SMBALTEN SMBus Alert enable 0 SMBA pin is not pulled down device mode or SMBus Alert pin SMBA is disabled host mode 1 SMBA pin is pulled down device mode or SMBus Alert pin SMBA is enabled host mode 21 SMBDAEN SMBus device default address enable 0 Device default address is dis...

Page 501: ...l in slave mode 0 Slave byte control is disabled 1 Slave byte control is enabled 15 DENR DMA enable for reception 0 DMA is disabled for reception 1 DMA is enabled for reception 14 DENT DMA enable for transmission 0 DMA is disabled for transmission 1 DMA is enabled for transmission 13 Reserved Must be kept at reset value 12 ANOFF Analog noise filter disable 0 Analog noise filter is enabled 1 Analog...

Page 502: ... is enabled 3 ADDMIE Address match interrupt enable in slave mode 0 Address match ADDSEND interrupt is disabled 1 Address match ADDSEND interrupt is enabled 2 RBNEIE Receive interrupt enable 0 Receive RBNE interrupt is disabled 1 Receive RBNE interrupt is enabled 1 TIE Transmit interrupt enable 0 Transmit TI interrupt is disabled 1 Transmit TI interrupt is enabled 0 I2CEN I2C peripheral enable 0 I...

Page 503: ...bytes have been transferred the TCR bit in I2C_STAT register will be set This bit is set and cleared by software 23 16 BYTENUM 7 0 Number of bytes to be transferred These bits are programmed with the number of bytes to be transferred When SBCTL 0 these bits have no effect Note These bits should not be modified when the START bit is set 15 NACKEN Generate NACK in slave mode 0 an ACK is sent after r...

Page 504: ...set this bit can not be modified 10 TRDIR Transfer direction in master mode 0 Master transmit 1 Master receive Note When the START bit is set this bit can not be modified 9 0 SADDRESS 9 0 Slave address to be sent SADDRESS 9 8 Slave address bit 9 8 If ADD10EN 0 these bits have no effect If ADD10EN 1 these bits should be written with bits 9 8 of the slave address to be sent SADDRESS 7 1 Slave addres...

Page 505: ... address Note When ADDRESSEN is set this bit should not be written 7 1 ADDRESS 7 1 7 bit address or bits 7 1 of a 10 bit address Note When ADDRESSEN is set this bit should not be written 0 ADDRESS0 Bit 0 of a 10 bit address Note When ADDRESSEN is set this bit should not be written 21 4 4 Slave address register 1 I2C_SADDR1 Address offset 0x0C Reset value 0x0000 0000 This register can be accessed b...

Page 506: ...ote When ADDRESS2EN is set these bits should not be written 0 Reserved Must be kept at reset value 21 4 5 Timing register I2C_TIMING Address offset 0x10 Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PSC 3 0 Reserved SCLDELY 3 0 SDADELY 3 0 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCLH 7 0 SCLL 7 0 rw rw Bits Fields Descri...

Page 507: ...0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EXTOEN Reserved BUSTOB 11 0 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOEN Reserved TOIDLE BUSTOA 11 0 rw rw rw Bits Fields Descriptions 31 EXTOEN Extended clock timeout detection enable When a cumulative SCL stretch time is greater than tLOW EXT a timeout error will be occurred tLOW EXT BUST...

Page 508: ...register I2C_STAT Address offset 0x18 Reset value 0x0000 0001 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved READDR 6 0 TR r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2CBSY Reserved SMBALT TIMEOUT PECERR OUERR LOSTAR B BERR TCR TC STPDET NACK ADDSEN D RBNE TI TBE r r r r r r r r r r r r r rw rw Bits Fields Descriptions 31 24 Reserved Must be ke...

Page 509: ...C does not match with the content of I2C_PEC register Then a NACK is automatically sent It is cleared by software by setting the PECERRC bit and cleared by hardware when I2CEN 0 0 Received PEC and content of I2C_PEC match 1 Received PEC and content of I2C_PEC don t match I2C will send NACK regardless of NACKEN bit 10 OUERR Overrun Underrun error in slave mode In slave mode with SS 1 when an overru...

Page 510: ...t Acknowledge flag This flag is set by hardware when a NACK is received It is cleared by software by setting NACKC bit and cleared by hardware when I2CEN 0 0 ACK is received 1 NACK is received 3 ADDSEND Address received matches in slave mode This bit is set by hardware when the received slave address matched with one of the enabled slave addresses It is cleared by software by setting ADDSENDC bit ...

Page 511: ... STPDET C NACKC ADDSEN DC Reserved w w w w w w w w w Bits Fields Descriptions 31 14 Reserved Must be kept at reset value 13 SMBALTC SMBus Alert flag clear Software can clear the SMBALT bit of I2C_STAT by writing 1 to this bit 12 TIMEOUTC TIMEOUT flag clear Software can clear the TIMEOUT bit of I2C_STAT by writing 1 to this bit 11 PECERRC PEC error flag clear Software can clear the PECERR bit of I2...

Page 512: ... 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PECV 7 0 r Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 PECV 7 0 Packet Error Checking Value that calculated by hardware when PEC is enabled PECV is cleared by hardware when I2CEN 0 21 4 10 Receive data register I2C_RDATA Address offset 0x24 Reset value 0x0000 0000 This register can be accessed by word 3...

Page 513: ...I2C_CTL2 Address offset 0x90 Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDM 6 0 Reserved rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 9 ADDM 6 0 Defines which bits of ADDRESS 7 1 are compared with an incoming address byte and which bits are ignored ...

Page 514: ...th full duplex or simplex mode Separate transmit and receive buffer 16 bits wide in SPI1 Data frame size can be 8 or 16 bits in SPI1 Bit order can be LSB or MSB Software and hardware NSS management Hardware CRC calculation transmission and checking Transmission and reception using DMA SPI TI mode supported SPI NSS pulse mode supported Separate transmit and receive 32 bit FIFO with DMA capability o...

Page 515: ... 1 SPI signal description Pin name Direction Description SCK I O Master SPI clock output Slave SPI clock input MISO I O Master Data reception line Slave Data transmission line Master with bidirectional mode Not used Slave with bidirectional mode Data transmission and reception line MOSI I O Master Data transmission line Slave Data reception line Master with bidirectional mode Data transmission and...

Page 516: ...The SPI is connected to external devices through 6 pins in Quad SPI mode Table 22 2 Quad SPI signal description Pin name Direction Description SCK O SPI clock output MOSI I O Transmission Reception data 0 MISO I O Transmission Reception data 1 IO2 I O Transmission Reception data 2 IO3 I O Transmission Reception data 3 NSS O NSS output 22 5 SPI function overview 22 5 1 SPI clock timing and data for...

Page 517: ...configured by the FF16 bit in the SPI_CTL0 register Data length is 16 bits if FF16 1 otherwise is 8 bits Data order is configured by LF bit in SPI_CTL0 register and SPI will first send the LSB if LF 1 or the MSB if LF 0 The data order is fixed to MSB first in TI mode Figure 22 3 SPI1 timing diagram in normal mode SCK CKPH 0 CKPL 0 SCK CKPH 0 CKPL 1 SCK CKPH 1 CKPL 0 SCK CKPH 0 CKPL 1 LF 1 FF16 0 M...

Page 518: ... configured by LF bit in SPI_CTL0 register and SPI will first send the LSB if LF 1 or the MSB if LF 0 The data order is fixed to MSB first in TI mode When the SPI_DATA register is accessed data frames are always right aligned into either a byte if the data fits into a byte or a half word During communication only bits within the data frame are clocked and transferred Figure 22 5 SPI0 data frame ri...

Page 519: ...cleared the RXFIFO empty means the RXFIFO level is less than half of its capacity The meaning of RXFIFO full is the opposite If the RXFIFO empty or full appears below and there is no special explanation the meaning is the same as this Data packing When the data frame size is less than or equal to 8 bits data packing mode is automatically enabled when BYTEN is set as 0 The double data frame pattern...

Page 520: ...eral purpose IO as NSS pin to realize more flexible NSS 22 5 4 SPI operation modes Table 22 3 SPI operation modes Mode Description Register configuration Data pin usage MFD Master full duplex MSTMOD 1 RO 0 BDEN 0 BDOEN Don t care MOSI Transmission MISO Reception MTU Master transmission with unidirectional connection MSTMOD 1 RO 0 BDEN 0 BDOEN Don t care MOSI Transmission MISO Not used MRU Master r...

Page 521: ...O Not used STB Slave transmission with bidirectional connection MSTMOD 0 RO 0 BDEN 1 BDOEN 1 MOSI Not used MISO Transmission SRB Slave reception with bidirectional connection MSTMOD 0 RO 0 BDEN 1 BDOEN 0 MOSI Not used MISO Reception Figure 22 6 A typical full duplex connection Master MFD MISO MOSI SCK NSS Slave SFD MISO MOSI SCK NSS Figure 22 7 A typical simplex connection Master Receive Slave Tra...

Page 522: ...its in the SPI_CTL0 register 3 Program the frame format LF bit in the SPI_CTL0 register 4 Program data format DZ bits in the SPI_CTL2 register and the access size for the SPI_DATA register BYTEN bit in the SPI_CTL2 register 5 Program the NSS mode SWNSSEN and NSSDRV bits in the SPI_CTL0 register according to the application s demand as described above in NSS function section 6 If TI mode is used se...

Page 523: ...e application writes a data into the transmit buffer TXFIFO In slave mode the transmission starts when SCK clock signal begins to toggle at SCK pin and NSS level is low so application should ensure that data is already written into transmit buffer TXFIFO before the transmission starts in slave mode When SPI begins to send a data frame it first loads this data frame from the data buffer TXFIFO to t...

Page 524: ... data overrun fault will occur The slave reception mode SRU or SRB is similar to the reception sequence of full duplex mode regardless of the TBE flag SPI TI mode SPI TI mode takes NSS as a special frame header flag signal and its operation sequence is similar to normal mode described above The modes described above MFD MTU MRU MTB MRB SFD STU SRU STB and SRB are still supported in TI mode While i...

Page 525: ... of time before releasing the pin This time is called 𝑇𝑑 𝑇𝑑 is decided by PSC 2 0 bits in SPI_CTL0 register Td Tbit 2 5 Tpclk 22 1 For example if PSC 2 0 010 𝑇𝑑is 9 Tpclk In slave mode the slave also monitors the NSS signal and sets an error flag FERR if it detects an incorrect NSS behavior for example toggles at the middle bit of a byte NSS pulse mode operation sequence This function is controlle...

Page 526: ...ion modes in Quad SPI mode quad write and quad read decided by QRD bit in SPI_QCTL register Quad write operation SPI works in quad write mode when QMOD is set and QRD is cleared in SPI_QCTL register In this mode MOSI MISO IO2 and IO3 are all used as output pins SPI begins to generate clock on SCK line and transmit data on MOSI MISO IO2 and IO3 as soon as data is written into SPI_DATA TBE is cleare...

Page 527: ...o generate SCK clocks so the written data can be any value Once SPI starts transmission it always checks SPIEN and TBE status at the end of a frame and stops when condition is not met So dummy data should always be written into SPI_DATA to generate SCK The operation flow for receiving in quad mode is shown below 1 Configure clock prescaler clock polarity phase etc in SPI_CTL0 and SPI_CTL1 register...

Page 528: ...XLVL 1 0 00 and confirm TRANS 0 Then disable the SPI by clearing SPIEN bit At last read data until RXTVL 1 0 00 For SPI1 wait for the last RBNE flag and then receive the last data Confirm that TBE 1 and TRANS 0 At last disable the SPI by clearing SPIEN bit MTU MTB STU STB For SPI0 wait until TXLVL 1 0 00 and confirm TRANS 0 Then disable the SPI by clearing SPIEN bit For SPI1 write the last data in...

Page 529: ...in SPI_QCTL register and SPIEN bit in SPI_CTL0 register are cleared 22 5 5 DMA function The DMA frees the application from data writing and reading process during transfer to improve the system efficiency DMA function in SPI is enabled by setting DMATEN and DMAREN bits in SPI_CTL1 register To use DMA function application should first correctly configure DMA modules then configure SPI module accord...

Page 530: ...ls the CRCERR flag will be set For SPI1 if DMA function is enabled application doesn t need to operate CRCNT bit and hardware will automatically process the CRC transmitting and checking For SPI0 a CRC format transaction usually takes one more data frame to communicate at the end of data sequence However when setting an 8 bit data frame checked by 16 bit CRC two more frames are necessary to send t...

Page 531: ...the CONFERR is set the SPIEN bit and the MSTMOD bit are cleared by hardware the SPI is disabled and the device is forced into slave mode The SPIEN and MSTMOD bit are write protection until the CONFERR is cleared The CONFERR bit of the slave cannot be set In a multi master configuration the device can be in slave mode with CONFERR bit set which means there might have been a multi master conflict fo...

Page 532: ...ter Control Logic Slave Control Logic TX Buffer Shift Register RX Buffer Control Registers 16 bits SYSCLK 16 bits LSB MSB PAD PAD O I O I PAD O I PAD O I APB There are five sub modules to support I2S function including control registers clock generator master control logic slave control logic and shift register All the user configuration registers are implemented in the control registers module in...

Page 533: ...length are configured by the DTLEN bits and CHLEN bit in the SPI_I2SCTL register Since the channel length must be greater than or equal to the data length four packet types are available They are 16 bit data packed in 16 bit frame 16 bit data packed in 32 bit frame 24 bit data packed in 32 bit frame and 32 bit data packed in 32 bit frame The data buffer for transmission and reception is 16 bit wid...

Page 534: ...SB MSB LSB I2S_WS Figure 22 20 I2S Phillips standard timing diagram DTLEN 10 CHLEN 1 CKPL 1 I2S_CK I2S_SD 32 bit data frame 1 channel left frame 2 channel right MSB MSB LSB I2S_WS When the packet type is 32 bit data packed in 32 bit frame two write or read operations to or from the SPI_DATA register are needed to complete the transmission of a frame In transmission mode if a 32 bit data is going t...

Page 535: ...its are zeros Figure 22 23 I2S Phillips standard timing diagram DTLEN 00 CHLEN 1 CKPL 0 I2S_CK I2S_SD 16 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 16 bit 0 MSB Figure 22 24 I2S Phillips standard timing diagram DTLEN 00 CHLEN 1 CKPL 1 I2S_CK I2S_SD 16 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 16 bit 0 MSB When the packet type is 16 bit data packed i...

Page 536: ...LEN 1 CKPL 1 I2S_CK I2S_SD 32 bit data frame 1 channel left frame 2 channel right MSB MSB LSB I2S_WS Figure 22 29 MSB justified standard timing diagram DTLEN 01 CHLEN 1 CKPL 0 I2S_CK I2S_SD 24 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 8 bit 0 MSB Figure 22 30 MSB justified standard timing diagram DTLEN 01 CHLEN 1 CKPL 1 I2S_CK I2S_SD 24 bit data frame 1 channel left frame ...

Page 537: ...I2S_WS 24 bit data MSB LSB Figure 22 34 LSB justified standard timing diagram DTLEN 01 CHLEN 1 CKPL 1 I2S_CK I2S_SD 8 bit 0 frame 1 channel left frame 2 channel right I2S_WS 24 bit data MSB LSB When the packet type is 24 bit data packed in 32 bit frame two write or read operations to or from the SPI_DATA register are needed to complete the transmission of a frame In transmission mode if a 24 bit d...

Page 538: ...nd the long frame synchronization mode are available and configurable using the PCMSMOD bit in the SPI_I2SCTL register The SPI_DATA register is handled in the exactly same way as that for I2S Phillips standard The timing diagrams for each configuration of the short frame synchronization mode are shown below Figure 22 37 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 0 ...

Page 539: ...PL 1 I2S_CK I2S_SD 24 bit data MSB I2S_WS MSB frame 1 frame 2 8 bit 0 Figure 22 43 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 0 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB frame 1 frame 2 16 bit 0 Figure 22 44 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 1 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB frame 1 frame 2 16 bit 0 Th...

Page 540: ...L 0 I2S_CK I2S_SD 32 bits MSB I2S_WS MSB LSB frame 1 frame 2 13 bits Figure 22 48 PCM standard long frame synchronization mode timing diagram DTLEN 10 CHLEN 1 CKPL 1 I2S_CK I2S_SD 32 bits MSB I2S_WS MSB LSB frame 1 frame 2 13 bits Figure 22 49 PCM standard long frame synchronization mode timing diagram DTLEN 01 CHLEN 1 CKPL 0 I2S_CK I2S_SD 24 bit data MSB I2S_WS MSB frame 1 frame 2 13 bits 8 bit 0...

Page 541: ..._CK I2S_MCK MCKOEN The block diagram of I2S clock generator is shown as Figure 22 53 Block diagram of I2S clock generator The I2S interface clocks are configured by the DIV bits the OF bit the MCKOEN bit in the SPI_I2SPSC register and the CHLEN bit in the SPI_I2SCTL register The source clock is the system clock CK_SYS The I2S bitrate can be calculated by the formulas shown in Table 22 5 I2S bitrat...

Page 542: ...ls for each operation mode Table 22 7 Direction of I2S interface signals for each operation mode Operation mode I2S_MCK I2S_CK I2S_WS I2S_SD Master transmission Output or NU 1 Output Output Output Master reception Output or NU 1 Output Output Input Slave transmission Input or NU 1 Input Input Output Slave reception Input or NU 1 Input Input Input 1 NU means the pin is not used by I2S and can be us...

Page 543: ...ta in the transmit buffer is loaded into the shift register and the TBE flag goes back high Software should write the next audio data into SPI_DATA register before the current data finishes otherwise the audio data transmission is not continuous For all standards except PCM the I2SCH flag is used to distinguish which channel side the data to transfer belongs to The I2SCH flag is refreshed at the m...

Page 544: ...3 Clear the I2SEN bit I2S slave transmission sequence The transmission sequence in slave mode is similar to that in master mode The difference between them is described below In slave mode the slave has to be enabled before the external master starts the communication The transmission sequence begins when the external master sends the clock and when the I2S_WS signal requests the transfer of data ...

Page 545: ...itor the state of the I2S bus Transmit buffer empty flag TBE This bit is set when the transmit buffer is empty the software can write the next data to the transmit buffer by writing the SPI_DATA register Receive buffer not empty flag RBNE This bit is set when receive buffer is not empty which means that one data is received and stored in the receive buffer and software can read the data by reading...

Page 546: ...I2S mode the I2S monitors the I2S_WS signal and an error flag will be set if I2S_WS toggles at an unexpected position I2S interrupt events and corresponding enabled bits are summed up in the Table 22 8 I2S interrupt Table 22 8 I2S interrupt Interrupt flag Description Clear method Interrupt enable bit TBE Transmit buffer empty Write SPI_DATA register TBEIE RBNE Receive buffer not empty Read SPI_DAT...

Page 547: ...15 BDEN Bidirectional enable 0 2 line unidirectional transmit mode 1 1 line bidirectional transmit mode The information transfers between the MOSI pin in master and the MISO pin in slave 14 BDOEN Bidirectional transmit output enable When BDEN is set this bit determines the direction of transfer 0 Work in receive only mode 1 Work in transmit only mode 13 CRCEN CRC calculation enable 0 CRC calculati...

Page 548: ...evel depends on SWNSS bit This bit has no meaning in SPI TI mode 8 SWNSS NSS pin selection in NSS software mode 0 NSS pin is pulled low 1 NSS pin is pulled high This bit has an effect only when the SWNSSEN bit is set This bit has no meaning in SPI TI mode 7 LF LSB first mode 0 Transmit MSB first 1 Transmit LSB first This bit has no meaning in SPI TI mode 6 SPIEN SPI enable 0 SPI peripheral is disa...

Page 549: ...st be kept at reset value 14 TXDMA_ODD Odd bytes in TX DMA channel only for SPI0 In data packing mode this bit is set if the total number of data to transmit by DMA is odd It has effect only when DMATEN is set and data packing mode enable data size is less than or equal to 8 bit and write access to SPI_DATA is 16 bit wide This field can be written only when SPI is disabled 0 The total number of da...

Page 550: ...s generated when the RBNE bit is set 5 ERRIE Errors interrupt enable 0 Error interrupt is disabled 1 Error interrupt is enabled An interrupt is generated when the CRCERR bit or the CONFERR bit or the RXORERR bit or the TXURERR bit is set 4 TMOD SPI TI mode enable 0 SPI TI mode disabled 1 SPI TI mode enabled 3 NSSP SPI NSS pulse mode enable 0 SPI NSS pulse mode disable 1 SPI NSS pulse mode enable 2...

Page 551: ..._w0 r r Bits Fields Descriptions 31 13 Reserved Must be kept at reset value 12 11 TXLVL 1 0 TXFIFO level only for SPI0 00 Empty 01 1 4 full 10 1 2 full 11 Full Note The FIFO level here refers to the current actual storage of the FIFO Here the FIFO is considered full when the FIFO level is greater than 1 2 10 9 RXLVL 1 0 RXFIFO level only for SPI0 00 Empty 01 1 4 full 10 1 2 full 11 Full This field...

Page 552: ...he SPI_STAT register followed by a write access to the SPI_CTL0 register 4 CRCERR SPI CRC error bit 0 The SPI_RCRC value is equal to the received CRC data at last 1 The SPI_RCRC value is not equal to the received CRC data at last This bit is set by hardware and is able to be cleared by writing 0 3 2 Reserved Must be kept at reset value 1 TBE Transmit buffer TXFIFO empty 0 Transmit buffer TXFIFO is...

Page 553: ...uffer are 8 bits If the Data frame format is set to 16 bit data the SPI_DATA 15 0 is used for transmission and reception transmit buffer and receive buffer are 16 bit Note In fact SPI0 hardware determines the size of each access to SPI_DATA only based on the BYTEN bit in SPI_CTL1 regardless of the size of the software s current operation 22 11 5 CRC polynomial register SPI_CRCPOLY Address offset 0...

Page 554: ... based on CRC8 standard and saves the value in RCRC 7 0 In addition to this the calculation is based on CRC16 standard and saves the value in RCRC 15 0 The hardware computes the CRC value after each received bit when the TRANS is set a read to this register could return an intermediate value This register is reset when the CRCEN bit in SPI_CTL0 register or the SPIxRST bit in RCU reset register is ...

Page 555: ...lues This register is reset when the CRCEN bit in SPI_CTL0 register or the SPIxRST bit in RCU reset register is set 22 11 8 I2S control register SPI_I2SCTL Address offset 0x1C Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved I2SSEL I2SEN I2SOPMOD 1 0 PCMSM...

Page 556: ...KPL Idle state clock polarity 0 The idle state of I2S_CK is low level 1 The idle state of I2S_CK is high level This bit should be configured when I2S mode is disabled This bit is not used in SPI mode 2 1 DTLEN 1 0 Data length 00 16 bits 01 24 bits 10 32 bits 11 Reserved These bits should be configured when I2S mode is disabled These bits are not used in SPI mode 0 CHLEN Channel length 0 16 bits 1 ...

Page 557: ... mode is disabled This bit is not used in SPI mode 7 0 DIV 7 0 Dividing factor for the prescaler Real divider value is DIV 2 OF DIV must not be 0 These bits should be configured when I2S mode is disabled These bits are not used in SPI mode 22 11 10 Quad SPI mode control register SPI_QCTL of SPI0 Address offset 0x80 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 3...

Page 558: ... quad wire write mode 1 SPI is in quad wire read mode This bit should be only be configured when SPI is not busy TRANS bit cleared This bit is only available in SPI0 0 QMOD Quad SPI mode enable 0 SPI is in single wire mode 1 SPI is in Quad SPI mode This bit should only be configured when SPI is not busy TRANS bit cleared This bit is only available in SPI0 ...

Page 559: ...transfer is supported and data can be accessed in the input and output FIFO 23 2 Characteristics DES TDES and AES encryption decryption algorithms are supported Multiple modes are supported respectively in DES TDES and AES including Electronic codebook ECB Cipher block chaining CBC Counter mode CTR Galois counter mode GCM Galois message authentication code mode GMAC Counter with CBC MAC CCM Cipher...

Page 560: ...sor The same swapping operation should be also performed on the processor output data before they are collected Note the least significant data always occupies the lowest address location no matter which data type is configured because the system memory is little endian Figure 23 1 DATAM No swapping and Half word swapping and Figure 23 2 DATAM Byte swapping and Bit swapping illustrate the 128 bit ...

Page 561: ...CTR GCM GMAC CCM CFB and OFB modes to XOR with data blocks They are independent of plaintext and ciphertext and the DATAM value will not affect them Note the initialization vector registers CAU_IV0 1 H L can only be written when BUSY is 0 otherwise the write operations are invalid 23 4 Cryptographic acceleration processor The cryptographic acceleration unit implements DES and AES acceleration proc...

Page 562: ... configured three different keying options are allowed 1 Three same keys The three keys KEY3 KEY2 and KEY1 are completely equal which means KEY3 KEY2 KEY1 FIPS PUB 46 3 1999 and ANSI X9 52 1998 refers to this option It is easy to understand that this mode is equivalent to DES 2 Two different keys In this option KEY2 is different from KEY1 and KEY3 is equal to KEY1 which means KEY1 and KEY2 are ind...

Page 563: ...trated in Figure 23 4 DES TDES ECB encryption Figure 23 4 DES TDES ECB encryption SWAP CAU_DI DATAM DEA encrypt DEA encrypt DEA decrypt KEY1 KEY2 KEY3 SWAP CAU_DO Plaintext Ciphertext DES TDES ECB decryption The 64 bit input ciphertext is first obtained after data swapping according to the data type When the TDES algorithm is configured the input data block is read in the DEA and decrypted using K...

Page 564: ...n decrypted using KEY2 After that the output is fed back directly to the last DEA and encrypted with KEY3 The result is then used as the next initialization vector and exclusive ORed with the next plaintext data block to process next encryption The above operations are repeated until the last plaintext block is encrypted Note if the plaintext message does not consist of an integral number of data ...

Page 565: ... XORed with the initialization vector which is the same as that used during encryption At the same time the first ciphertext is then used as the next initialization vector and exclusive ORed with the next result after DEA blocks The above operations are repeated until the last ciphertext block is decrypted Note if the ciphertext message does not consist of an integral number of data blocks the fin...

Page 566: ...3 KEY2 when the key size is configured as 128 KEY3 KEY2 KEY1 when the key size is configured as 192 and KEY3 KEY2 KEY1 KEY0 when the key size is configured as 256 The thorough explanation of the key used in the AES is provided in FIPS PUB 197 November 26 2001 and the explanation process is omitted in this manual AES ECB mode encryption The 128 bit input plaintext is first obtained after data swapp...

Page 567: ...yption The last round key obtained from the above operation is then used as the first round key in the decryption After the key derivation the 128 bit input ciphertext is first obtained after data swapping according to the data type The input data block is read in the AEA and decrypted using keys prepared above The output is then swapped back according to the data type again and a 128 bit plaintex...

Page 568: ... is read in the AEA and encrypted using the 128 192 256 bit key The result is then used as the next initialization vector and exclusive ORed with the next plaintext data block to process next encryption The above operations are repeated until the last plaintext block is encrypted Note if the plaintext message does not consist of an integral number of data blocks the final partial data block should...

Page 569: ...ccording to the data type The input data block is read in the AEA and decrypted using keys prepared above At the same time the first ciphertext is then used as the next initialization vector and exclusive ORed with the next result after AEA blocks The first initialization is obtained directly from the CAU_IV0 1 registers The above operations are repeated until the last ciphertext block is decrypte...

Page 570: ...the same Then decryption operation acts exactly in the same way as the encryption operation Only the 32 bit LSB of the 128 bit initialization vector represents the counter which means the other 96 bits are unchanged during the operation and the initial value should be set to 1 Nonce is 32 bit single use random value and should be updated to each communication block And the 64 bit initialization ve...

Page 571: ...ed and saved internally to be used later a Clear the CAUEN bit to make sure CAU is disabled b Configure the ALGM 3 0 bits to 1000 c Configure GCM_CCMPH 1 0 bits to 00 d Configure key registers and initialization vectors e Enable CAU by writing 1 to CAUEN bit f Wait until CAUEN bit is cleared by hardware and then enable CAU again for following phases 2 GCM AAD additional authenticated data phase Th...

Page 572: ... tag q Disable the CAU Note The key should be prepared at the beginning when a decryption is performed AES GMAC mode The AES Galois message authentication code mode is also supported to authenticate the message It is processing based on the AES GCM mode while the encryption decryption phase is by passed AES CCM mode The AES combined cipher machine mode which is similar to AES GCM mode also allows ...

Page 573: ...ive data The size of the AAD must be a multiple of 128 bits DMA can also be used j Repeat i until all header data are supplied wait until BUSY bit is cleared 3 CCM encryption decryption phase This phase must be performed after CCM AAD phase In this phase the message is authenticated and encrypted decrypted Like GCM the CCM chaining mode can be applied on a message composed only by plaintext authen...

Page 574: ...key length with the KEYM bits in the CAU_CTL register if AES algorithm is chosen 4 Configure the CAU_KEY0 3 H L registers according to the algorithm 5 Configure the DATAM bit in the CAU_CTL register to select the data swapping type 6 Configure the algorithm DES TDES AES and the chaining mode ECB CBC CTR GCM GMAC CCM CFB OFB by writing the ALGM 3 0 bit in the CAU_CTL register 7 Configure the encryp...

Page 575: ... CAU by set the CAUEN bit as 1 in the CAU_CTL register 14 If the INF bit in the CAU_STAT0 register is 1 then write data blocks into the CAU_DI register The data can be transferred by DMA CPU during interrupts no DMA or interrupts 15 Wait for ONE bit in the CAU_STAT0 register is 1 then read the CAU_DO registers The output data can also be transferred by DMA CPU during interrupts no DMA or interrupt...

Page 576: ... enabled by OINTEN with a 0 value the OINTF is also asserted Note Unlike that of Input FIFO interrupt the value of CAUEN will never affect the situation of OSTA and OINTF 23 8 CAU suspended mode It is possible to suspend a data block if another new data block with a higher priority needs to be processed in CAU The following steps can be performed to complete the encryption decryption acceleration ...

Page 577: ...read of the CAU_DO register and before the next CAU_DI write access so that the message is suspended at the end of a block processing 2 Disable the CAU by clearing the CAUEN bit in the CAU_CTL register 3 Save the configuration including the key size data type operation mode direction GCM CCM phase and the key values When it is CBC CTR GCM GMAC CCM CFB or OFB chaining mode the initialization vector...

Page 578: ... be kept at reset value 23 20 NBPILB 3 0 Number of bytes padding in last block of payload 0000 all bytes are valid no padding 0001 one padding byte of last block 1111 15 padding bytes of last block 19 ALGM 3 Encryption decryption algorithm mode bit 3 18 Reserved Must be kept at reset value 17 16 GCM_CCMPH 1 0 GCM CCM phase 00 prepare phase 01 AAD phase 10 encryption decryption phase 11 tag phase 1...

Page 579: ...CAU_KEY1 Initialization vectors CAU_IV0 1 are not used 0011 DES CBC with only CAU_KEY1 Initialization vectors CAU_IV0 is used to XOR with data blocks 0100 AES ECB with CAU_KEY0 1 2 3 Initialization vectors CAU_IV0 1 are not used 0101 AES CBC with CAU_KEY0 1 2 3 Initialization vectors CAU_IV0 1 are used to XOR with data blocks 0110 AES_CTR with CAU_KEY0 1 2 3 Initialization vectors CAU_IV0 1 are us...

Page 580: ... bit 0 No processing This is because CAU is disabled by CAUEN 0 or the processing has been completed No enough data or no enough space in the input output FIFO to perform a data block 1 CAU is processing data or key derivation 3 OFU Output FIFO is full 0 Output FIFO is not full 1 Output FIFO is full 2 ONE Output FIFO is not empty 0 Output FIFO is empty 1 Output FIFO is not empty 1 INF Input FIFO i...

Page 581: ...7 6 5 4 3 2 1 0 DI 15 0 rw Bits Fields Descriptions 31 0 DI 31 0 Data input Write these bits will write data to IN FIFO read these bits will return IN FIFO value if CAUEN is 0 or it will return an undefined value 23 9 4 Data output register CAU_DO Address offset 0x0C Reset value 0x0000 0000 The data output register is a read only register It is used to receive plaintext or ciphertext results from ...

Page 582: ...r OUT FIFO data is disabled 1 DMA for OUT FIFO data is enabled 0 DMAIEN DMA input enable 0 DMA for IN FIFO data is disabled 1 DMA for IN FIFO data is enabled 23 9 6 Interrupt enable register CAU_INTEN Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OIN...

Page 583: ...ISTA r r Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 OSTA OUT FIFO interrupt status 0 OUT FIFO interrupt status not pending 1 OUT FIFO interrupt status pending 0 ISTA IN FIFO interrupt status 0 IN FIFO interrupt not pending 1 IN FIFO interrupt flag pending 23 9 8 Interrupt flag register CAU_INTF Address offset 0x1C Reset value 0x0000 0000 This register has to be accessed b...

Page 584: ...In AES 128 mode KEY2H 31 0 KEY2L 31 0 is used as AES_KEY 0 63 and KEY3H 31 0 KEY3L 31 0 is used as AES_KEY 64 127 In AES 192 mode KEY1H 31 0 KEY1L 31 0 is used as AES_KEY 0 63 KEY2H 31 0 KEY2L 31 0 is used as AES_KEY 64 127 and KEY3H 31 0 KEY3L 31 0 is used as AES_KEY 128 191 In AES 256 mode KEY0H 31 0 KEY0L 31 0 is used as AES_KEY 0 63 KEY1H 31 0 KEY1L 31 0 is used as AES_KEY 64 127 KEY2H 31 0 KE...

Page 585: ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY1H 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY1H 15 0 w CAU_KEY1L Address offset 0x2C Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY1L 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY1L 15 0 w CAU_KEY2H Address offset 0x30 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY2H 31 16 w 15 ...

Page 586: ... KEY3H 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY3H 15 0 w CAU_KEY3L Address offset 0x3C Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY3L 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY3L 15 0 w Bits Fields Descriptions 31 0 KEY0 3 H L The key for DES TDES AES 23 9 10 Initial vector registers CAU_IV0 1 H L Address offset 0x40 to 0x4C Reset value 0x0000 0000 Th...

Page 587: ...9 18 17 16 IV0H 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IV0H 15 0 rw CAU_IV0L Address offset 0x44 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IV0L 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IV0L 15 0 rw CAU_IV1H Address offset 0x48 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IV1H 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IV1H ...

Page 588: ... 0 CTXx 15 0 rw Bits Fields Descriptions 31 0 CTXx 31 0 The internal status of the CAU core Read and save the register data when a high priority task is coming to be processed and restore the saved data back to the registers to resume the suspended processing Note These registers are used only when GCM GMAC or CCM mode is selected 23 9 12 GCM mode context switch register x CAU_GCMCTXSx x 0 7 Addre...

Page 589: ...atus of the CAU core Read and save the register data when a high priority task is coming to be processed and restore the saved data back to the registers to resume the suspended processing Note These registers are used only when GCM or GMAC mode is selected ...

Page 590: ... RCU_APB2EN register needs to be set to 1 before that producing 2 5V reference voltage and connecting to VREF pin When VREFEN is disabled off chip reference voltage could be injected to VREF pin to source ADC DAC If there is no VREF pin refer to datasheet the VREF is connected to VDDA and the VREFEN bit must keep 0 When using precision internal reference voltage and a bypass capacitor about 1uF or...

Page 591: ...bit and reset HIPM bit in the VREF_CS register the user must wait until VREFRDY bit is set indicating that the voltage reference output has reached its expected value 24 4 Register definition VREF base address 0x4001 0030 24 4 1 Control and status register VREF_CS Address offset 0x00 Reset value 0x0000 0002 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23...

Page 592: ...04 Reset value 0x0000 00xx This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved VREFCAL 5 0 rw Bits Fields Descriptions 31 6 Reserved Must be kept at reset value 5 0 VREFCAL VREF calibration These bits are automatically initialized after reset with the trimming value stored in the Fl...

Page 593: ...ible or invisible The SLCD controller can support up to 32 segments and 8 commons 25 2 Characteristics Configurable frame frequency Blinking of individual segments or all segments Supports Static 1 2 1 3 1 4 1 6 and 1 8 duty Supports 1 2 1 3 and 1 4 bias Double buffer up to 8x32 bits registers to store SLCD_DATAx The contrast can also be adjusted by configuring dead time Optional voltage output dr...

Page 594: ... and common voltages 25 3 2 Clock generator SLCD input clock is the same as RTCCLK 3 different clock sources LXTAL IRC32K and HXTAL divided by 32 can be selected by RTCSRC bits in RCU_BDCTL register The input clock frequency varies from 32KHz to 1MHz The SLCD controller uses the input clock signal from the integrated clock divider to generate the timing for common and segment lines The SLCD clock ...

Page 595: ...er BLKMOD 01 allows to blink individual segment on SEG0 with COM0 with BLKMOD 10 all commons on SEG0 are blinking with BLKMOD 11 all segments with all commons are blinking and with BLKMOD 00 blinking is disabled The blink frequency is generated from SLCD clock and selected with BLKDIV bit in SLCD_CFG registers The resulting BLINK frequency is calculated by fBLINK fSLCD 2 BLKDIV 3 25 3 After a blin...

Page 596: ...e inactive inactive inactive COM2 inactive inactive active inactive inactive inactive inactive inactive COM3 inactive inactive inactive active inactive inactive inactive inactive COM4 inactive inactive inactive inactive active inactive inactive inactive COM5 inactive inactive inactive inactive inactive active inactive inactive COM6 inactive inactive inactive inactive inactive inactive active inact...

Page 597: ...VSLCD VSS VSLCD 3 4VSLCD 1 2VSLCD 1 4VSLCD VSS VSLCD 3 4VSLCD 1 2VSLCD 1 4VSLCD VSS DEAD time The dead time is using DTD bits in SLCD_CFG register It inserts VSS after each even frame The number of phase inserted is defined by DTD bits The application can adjust the contrast according to the configuration of dead time Figure 25 4 SLCD dead time 1 3 Bias 1 4 Duty Odd frame Even frame Dead time Odd ...

Page 598: ...ix supplies SLCD voltage The SLCD voltage levels are generated by the VSLCD pin or by the internal voltage step up converter depending on the VSRC bit in the SLCD_CTL register When using the internal voltage the VSLCD value can be selected from VSLCD0 to VSLCD7 by the CONR 2 0 bits in the SLCD_CFG register Refer to the product datasheet for the VSLCDx values The application can adjust the contrast...

Page 599: ...ver The voltage output driver can only be configured when the SLCD controller is not activated 25 3 7 VSLCD voltage monitoring The VSLCDEN bit in the ADC_CTL1 register is used to measure the VSLCD voltage Since the VSLCD voltage may be higher than VDDA in order to ensure the normal operation of the ADC the internal VSLCDrail1 analog voltage is connected to the ADC_IN19 input channel The VSLCDrail1...

Page 600: ...7 COMS Common segment pad select This bit is used to common segment pad selection When duty selects 1 8 or 1 6 SLCD_COM 7 4 pad is always select SLCD_COM 7 4 function whatever this bit is set or reset 0 SLCD_COM 7 4 pad select SLCD_COM 7 4 1 SLCD_COM 7 4 pad select SLCD_SEG 31 28 6 5 BIAS 1 0 Bias select Bias is the number of voltage levels used when driving a SLCD It is defined as 1 number of vol...

Page 601: ...onfiguration register SLCD_CFG Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PSC 3 0 DIV 3 0 BLKMOD 1 0 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BLKDIV 2 0 CONR 2 0 DTD 2 0 PULSE 2 0 UPDIE Reserved SOFIE HDEN rw rw rw rw rw rw rw Bits Fields Descriptions 31 26 Reserved Must be kept at reset...

Page 602: ...CD 1024 12 10 CONR 2 0 Contrast ratio When chosing the internal voltage source VSRC 0 these bits specify the VSLCD voltage It ranges from VSLCD0 to VSLCD7 typical 2 65 V to 3 67V Refer to the product datasheet for the VSLCDx values When chosing the external voltage source VSRC 1 these bits is invalid 000 VSLCD0 001 VSLCD1 010 VSLCD2 011 VSLCD3 100 VSLCD4 101 VSLCD5 110 VSLCD6 111 VSLCD7 9 7 DTD 2 ...

Page 603: ...is bit is set and cleared by software 0 Permanent high drive disabled The time during which RL is enabled is configured by the PULSE 2 0 1 Permanent high drive enabled RL is always switched on and the PULSE 2 0 is invalid 25 4 3 Status flag register SLCD_STAT Address offset 0x08 Reset value 0x0000 0020 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 604: ...isters the application should set this bit to transfer the data to the second buffer This bit stays set until the transfer is complete the SLCD_DATAx register is write protected during this time 0 No effect 1 Request SLCD data update 1 SOF Start of frame flag This bit is set by hardware at the beginning of a new frame It is cleared by writing 1 to the SOFC bit in the SLCD_STATC register 0 No effec...

Page 605: ...ame flag clear Set this bit to clear the SOF flag in the SLCD_STAT register 0 No effect 1 Clear SOF flag 0 Reserved Must be kept at reset value 25 4 5 Display data registers SLCD_DATAx x 0 7 Address offset 0x14 0x08 x Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATAx 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATAx 15 ...

Page 606: ...ion achieves some current control by working together with a PWM output of a timer and the DAC 26 2 Characteristic Rail to rail comparators Configurable hysteresis Configurable speed and consumption Each comparator has configurable analog input source DAC several I O pins The whole or sub multiple values of internal reference voltage Window comparator Outputs with blanking source Outputs to an IO ...

Page 607: ...ured in analog mode in the GPIOs registers before they are selected as CMPs inputs Considering pin definitions in Datasheet the CMP output must be connected to corresponding alternate IOs A variety of timer inputs can be internally connected to the CMP output to realize the following functions Input capture for timing measures Emergency shut down of PWM signals using break function Cycle by cycle ...

Page 608: ...een the CMP power consumption versus propagation delay which is adjusted by configuring bits PM 1 0 in CMPx_CS register The CMP works fastest with highest power consumption when PM 2 b00 while works slowest with lowest power consumption when PM 2 b11 26 3 4 CMP windows mode If the WEN bit in CMP1_CS register is set comparator windows mode is enabled Input plus of comparator 1 is connected with inp...

Page 609: ...moment of PWM period a timer output compare signal is selected as blanking source by software The complementary of the blanking signal is ANDed with the comparator output so as to output the comparator expected result Figure 26 3 The CMP outputs signal blanking PWM signal Blanking window signal Current signal Current threshold CMP outputs raw singal CMP outputs final singal ...

Page 610: ...us register CMPx_CS can be protected from writing by setting LK bit to 1 The CMPx_CS register including the LK bit will be read only and can only be reset by the MCU reset This write protection function is useful in some applications such as thermal protection and over current protection ...

Page 611: ...1 CMP0_CS 31 0 bits are read only 30 OUT CMP0 output state bit This is a copy of CMP0 output state which is read only 0 Non inverting input below inverting input and the output is low 1 Non inverting input above inverting input and the output is high 29 24 Reserved Must be kept at reset value 23 SEN Voltage scaler enable bit This bit is set and cleared by software This bit enable the outputs of th...

Page 612: ...CMP0 output 0 Output is not inverted 1 Output is inverted 14 13 OSEL 1 0 CMP0 output selection These bits are used to select the destination of the CMP0 output 00 no selection 01 TIMER1 channel3 input capture 10 TIMER2 channel0 input capture 11 LPTIMER channel0 input capture 12 7 Reserved Must be kept at reset value 6 4 MSEL 2 0 CMP0 input minus selection bit 000 VREFINT 4 001 VREFINT 2 010 VREFIN...

Page 613: ...output state which is read only 0 Non inverting input below inverting input and the output is low 1 Non inverting input above inverting input and the output is high 29 24 Reserved Must be kept at reset value 23 SEN Voltage scaler enable bit This bit is set and cleared by software This bit enable the outputs of the VREFINT divider which is treated as the minus input of the Comparator 1 0 disable ba...

Page 614: ...ese bits are used to select the destination of the CMP0 output 00 no selection 01 TIMER1 channel3 input capture 10 TIMER2 channel0 input capture 11 LPTIMER channel1 input capture 12 11 Reserved Must be kept at reset value 10 8 PSEL 2 0 CMP1 input plus selection bit 000 PA3 001 PB4 010 PB5 011 PB6 100 PB7 All other values reserved 7 Reserved Must be kept at reset value 6 4 MSEL 2 0 CMP1 input minus...

Page 615: ...ow speed low power 1 WEN Windows mode enable bit 0 Input plus of Comparator 1 is not connected to Comparator 0 1 Input plus of Comparator 1 is connected with input plus of Comparator 0 0 EN CMP1 enable 0 disable CMP1 1 enable CMP1 ...

Page 616: ...ontroller Support up to 8 configurable bidirectional endpoints Support double buffered bulk isochronous endpoints Support USB 2 0 Link Power Management Each endpoint supports control bulk isochronous or interrupt transfer types exclude endpoint 0 endpoint 0 only support control transfer Support USB suspend resume operations dedicated 512 byte SRAM used for data packet buffer Integrated USB PHY USB...

Page 617: ...nal or external crystal oscillator by a programmable prescaler then multiplicating the frequency through PLL Regard two frequency division of 16MHz internal oscillator as the input of the PLL then 6 frequencies doubling the clock Regard 8MHz external oscillator as the input of the PLL then 6 frequencies doubling the clock Note Regardless of using internal or external crystal oscillator to generate...

Page 618: ...ration Endpoint buffer descriptor table To indicate where the endpoint related buffer is located how large it is or how many bytes must be transmitted USBD implements an endpoint buffer descriptor table which defines the buffer address and length and which is also located in the endpoint data packet buffer The endpoint buffer descriptor is used as a communication port between the application firmw...

Page 619: ...ndpoints The double buffered feature is used to improve bulk transfer performance To implement the new flow control scheme the USB peripheral should know which packet buffer is currently in use by the application software so to be aware of any conflict Since in the USBD_EPxCS register there are two data toggle bits TX_DTG and RX_DTG but only one is used by USBD for hardware data handling due to th...

Page 620: ...tions IN 0 1 EPxTBADDR EPxTBCNT buffer description table locations EPxRBADDR EPxRBCNT buffer description table locations 1 0 EPxRBADDR EPxRBCNT buffer description table locations EPxTBADDR EPxTBCNT buffer description table locations Endpoint memory requests arbitration As the USBD is connected to the APB1 bus through an APB1 interface so USB APB1 interface will accept memory requests coming from t...

Page 621: ...D OUT and SETUP transaction USBD handles these two tokens more or less in the same way the differences in the handling of SETUP packets will be detailed in the following section about control transfer After the received endpoint is configured and enabled host will send OUT SETUP token to the device When receiving the token USBD will access the endpoint buffer descriptor to initialize the endpoint ...

Page 622: ...s It is aware of the number and direction of data stages by interpreting the contents of SETUP transaction and is required to set the unused direction endpoint 0 status to STALL except the last data stage At the last data stage the application software set the opposite direction endpoint 0 status to NAK This will keep the host waiting for the completion of the control operation If the operation co...

Page 623: ...her buffer The DTOG bit indicates which buffer that the USB peripheral is currently using The application software initializes the DTOG according to the first buffer to be used At the end of each transaction the RX_ST or TX_ST bit is set depending on the enabled direction regardless of CRC errors or buffer overrun conditions if errors occur the ERRIF bit will be set At the same time The USB periph...

Page 624: ...ll go into the suspend state if there is no activity on the USB bus for more than 3ms A suspended device wakes up if RESUME signaling is detected USBD also supports software initiated remote wakeup To initiate remote wakeup the application software must enable all clocks and clear the suspend bit after MCU is waked up This will cause the hardware to generate a remote wakeup signal upstream Setting...

Page 625: ... 5 Wait for the reset interrupt RSTIF 6 In the reset interrupt initialize default control endpoint 0 to start enumeration process and program USBD_ADDR to set the device address to 0 and enable USB module function 7 Configure endpoint 0 and prepare to receive SETUP packet Endpoint initialization sequence 1 Program USBD_EPxTBADDR or USBD_EPxRBADDR registers with transmission or reception data buffe...

Page 626: ...gramming USBD_EPxCS register 3 Wait for successful transfer interrupt STIF 4 In the interrupt handler application can get the transaction type by reading the STEUP bit in USBD_EPxCS register Then application will read the data payload from the endpoint data buffer with the start address defined in USBD_EPxRBAR register Last application will interpret the data and process the corresponding transact...

Page 627: ...ted when packet memory overrun underrun 1 Interrupt generated when PMOUIF bit in USBD_INTF register is set 13 ERRIE Error interrupt enable 0 Error interrupt disabled 1 Interrupt generated when ERRIF bit in USBD_INTF register is set 12 WKUPIE Wakeup interrupt enable 0 Wakeup interrupt disabled 1 Interrupt generated when WKUPIF bit in USBD_INTF register is set 11 SPSIE Suspend state interrupt enable...

Page 628: ... resume request 3 SETSPS Set suspend The software should set suspend state when SPSIF bit in USBD_INTF register is set 0 Not set suspend state 1 Set suspend state 2 LOWM Low power mode When set this bit the USB goes to low power mode at suspend state If resume from suspend state the hardware reset this bit 0 No effect 1 Go to low power mode at suspend state 1 CLOSE Close state When this bit is set...

Page 629: ...SPSIF Suspend state interrupt flag When no traffic happen in 3ms hardware set this bit to indicate a SUSPEND request The software writes 0 to clear this bit 10 RSTIF USB reset interrupt flag Set by hardware when the USB RESET signal is detected The software writes 0 to clear this bit 9 SOFIF Start of frame interrupt flag Set by hardware when a new SOF packet arrives The software writes 0 to clear ...

Page 630: ...e that at the least two consecutive SOF have been received 12 11 SOFLN 1 0 SOF lost number Increment every ESOFIF happens by hardware Cleared once the reception of SOF 10 0 FCNT 10 0 Frame number counter The Frame number counter incremented every SOF received 27 7 4 USBD device address register USBD_DADDR Address offset 0x4C Reset value 0x0000 This register can be accessed by half word 16 bit or w...

Page 631: ... kept at reset value 27 7 6 USBD endpoint x control and status register USBD_EPxCS x 0 7 Address offset 0x00 to 0x1C Reset value 0x0000 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RX_ST RX_DTG RX_STA 1 0 SETUP EP_CTL 1 0 EP_KCTL TX_ST TX_DTG TX_STA 1 0 EP_ADDR 3 0 rc_w0 t t r rw rw rc_w0 t t rw Bits Fields Descriptions 15 RX_ST Reception s...

Page 632: ...1 for non isochronous endpoint Used to implement the flow control for double buffered endpoint Used to swap buffer for isochronous endpoint 5 4 TX_STA 1 0 Status bits for transmission transfers Refer to the table below 3 0 EP_ADDR Endpoint address Used to direct the transaction to the target endpoint Table 27 4 Reception status encoding RX_STA 1 0 Meaning 00 DISABLED ignore all reception requests ...

Page 633: ...4 3 2 1 0 EPTXBAR 15 1 EPTXBA R 0 rw rw Bits Fields Descriptions 15 1 EPTXBAR 15 1 Endpoint transmission buffer address Start address of the packet buffer containing data to be sent when receive next IN token 0 EPTXBAR 0 Must be set to 0 27 7 8 USBD endpoint x transmission buffer byte count register USBD_EPxTBCNT x can be in 0 7 Address offset USBD_BADDR x 16 4 USB local Address USBD_BADDR x 8 2 T...

Page 634: ... the endpoint at the next OUT SETUP token 0 EPRBAR 0 Must be set to 0 27 7 10 USBD endpoint x reception buffer byte count register USBD_EPxRBCNT x can be in 0 7 Address offset USBD_BADDR x 16 12 USB local Address USBD_BADDR x 8 6 This register can be accessed by half word 16 bit or word 32 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BLKSIZ BLKNUM 4 0 EPRCNT 9 0 rw rw r Bits Fields Descriptions 15 BL...

Page 635: ...State value received with last ACKed LPM token 3 REMWK bRemoteWake value This bit contains the bRemoteWake value received with last ACKed LPM token 2 Reserved Must be kept at reset value 1 LPMACK LPM token acknowledge enable 0 the valid LPM token will be NYETed 1 the valid LPM token will be ACKed The NYET ACK will be returned only on a successful LPM transaction No errors in both the EXT token and...

Page 636: ...9 8 7 6 5 4 3 2 1 0 DPUEN Reserved rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 DPUEN DP pull up control 0 Disable the embedded pull up on the DP line disconnect to host 1 Enable the embedded pull up on the DP line connect to host 14 0 Reserved Must be kept at reset value ...

Page 637: ... no effect 28 2 List of terms Table 28 2 List of terms Glossary Descriptions Word Data of 32 bit length Half word Data of 16 bit length Byte Data of 8 bit length IAP in application programming Writing 0 has no effect IAP is the ability to re program the Flash memory of a microcontroller while the user program is running ICP in circuit programming ICP is the ability to program the Flash memory of a...

Page 638: ...GD32L23x User Manual 638 29 Revision history Table 29 1 Revision history Revision No Description Date 1 0 Initial Release Oct 21 2021 ...

Page 639: ...y business industrial personal and or household applications only The Products are not designed intended or authorized for use as components in systems designed or intended for the operation of weapons weapons systems nuclear installations atomic energy control instruments combustion control instruments airplane or spaceship instruments transportation instruments traffic signal instruments life su...

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