Fujitsu MB91150 Series, Hardware Manual, Page: 95 / 512

79
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
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Delaying reset generation
Once the watchdog timer is activated, the program must periodically write A5
H
and 5A
H
to the
watchdog reset delay register (WPR).
The watchdog reset flip-flop stores the falling edge of the tap selected by the time-base timer. If
this flip-flop is not cleared at the second falling edge, a reset is generated.
Figure 3.11-4 "Watchdog timer operation" shows the timing of watchdog timer operation.
Figure 3.11-4 Watchdog timer operation
■
Causes of reset delays other than programs
The following cause the watchdog timer to automatically delay generation of a reset:
1. Stop or sleep state
2. DMA transfer
3. A break occurs when the emulator debugger or the monitor debugger is being used.
4. The INTE instruction is executed.
5. Step trace trap (a break occurs at each instruction by specifying 1 for T in the PS register)
Notes:
• There is no rule for the writing interval between the first A5
H
and the next 5A
H
. The watchdog
reset can be delayed only when the interval between two instances of writing 5A
H
is within
the time specified by the WT bit and A5
H
is written at least once between these two
instances of writing 5A
H
.
• If a value other than 5A
H
is written after the first A5
H
, the first A5
H
written is invalidated. In
this case, A5
H
must be written again.
■
Time-base timer
The time-base timer is used for supplying clock pulses to the watchdog timer and for waiting for
oscillation stabilization. For GCR CHC = 1, the cycle of the operating clock
φ
is two cycles of X0.
For GCR CHC = 0, it is one cycle of X0.
Figure 3.11-5 Time-base timer configuration
Time-base timer overflow
Watchdog flip-flop
WPR write
Watchdog activation Watchdog clear Watchdog reset generation
1/2
1
1/2
2
1/2
3
1/2
18
1/2
19
1/2
20
1/2
21
. . . . . .