Fujitsu MB91150 Series, Hardware Manual, Page: 382 / 512

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CHAPTER 17 DMA CONTROLLER
17.3.2 MAC control status register (DACSR)
The DMAC control status register (DACSR) is an internal register in the DMAC that
controls the entire DMAC and indicates its status.
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DMAC control status register (DACSR)
The register configuration of the DMAC control status register (DACSR) is given below.
[Bits 31, 27, 23, 19, 15, 11, 7, and 3] DERn (DMA error)
Indicates that an error has occurred at the DMA request source of channel n and that DMA
transfer processing has been terminated.
0: No error has occurred.
1: An error has occurred.
Whether an error is detected depends on the DMA request source. Some DMA request
sources have no error detection.
- Upon a reset, the bits in the register are initialized to 0.
- Although these bits can be read and written, they can be set only to 0.
- Read/modify/write instructions always return a reading value of 1.
[Bits 30, 26, 22, 18, 14, 10, 06, and 02] DEDn (DMA end)
Indicates that DMA transfer over channel n has ended.
0: DMA transfer operation has not ended.
1: The counter has been reset to 0, or an error occurred at the transfer request source.
- Upon a reset, the bits in the register are initialized to 0.
31 30 29 28 27 26 25 24
00000204
H
R/W R/W R/W R/W R/W R/W R/W R/W
23 22 21 20 19 18 17 16
R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8
R/W R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value: 00000000
H
DER7 DED7 DIE7 DOE7
DOE5 DIE5 DED5 DER5
DOE3 DIE3 DER3 DED3
DOE1 DIE1 DER1
DED1
DED6
DED4
DED2
DED0
DIE6
DIE4
DIE2
DIE0 DOE0
DER6
DER4
DER2
DER0
DOE6
DOE4
DOE2