Fujitsu MB91150 Series, Hardware Manual, Page: 157 / 512

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CHAPTER 4 BUS INTERFACE
4.5.6 Automatic Wait Cycle
This section describes the operations of the automatic wait cycle.
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Automatic wait cycle timing chart
Figure 4.5-14 "Sample timing chart for an automatic wait cycle" shows an example of automatic
wait cycle timing under the following conditions:
• Bus width: 16 bits
• Access type: Reading/writing in half words
Figure 4.5-14 Sample timing chart for an automatic wait cycle
[Operation]
• Automatic wait cycles can be implemented by setting the WTC bits of the AMD register in
each chip select area.
• In the above example, the WTC bits are set to 001 to insert one wait bus cycle between
normal bus cycles. The bus cycle includes three clock cycles (two clock cycles for normal
bus cycle plus one clock cycle for wait cycle).
Up to seven clock cycles can be set for one automatic wait cycle (accordingly, one normal
bus cycle contains nine clock cycles).
CLK
A23-00
D31-16
RD
WR0,WR1
(DACK0)
(DEOP0)
BA1 BA1 BA2 BA1 BA1 BA2
wait wait
#0 #2
#2,3
#0:1
Read
Write