Fujitsu MB91150 Series, Hardware Manual, Page: 369 / 512

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CHAPTER 16 I
2
C INTERFACE
[bit 8] INT (INTerrupt)
This bit is a transfer-end interrupt-request flag bit.
When this bit is 1, the SCL line is kept at L-level. When this bit is cleared by writing 0, the
SCL line is released, and transfer of the next byte is performed. When a start or stop
condition is generated in master mode, this bit is reset to 0.
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Contention among SCC, MSS, and INT bits
In simultaneous write operations of the SCC, MSS, and INT bits, transfer of the next byte, start-
condition generation, and stop-condition generation compete with each other. In this case, the
priority order becomes as follows:
1. Transfer of the next byte and stop-condition generation
• When an attempt is made to set the INT bit and the MSS bit to 0 by writing, the writing of
the MSS bit is given priority, and a stop condition is generated.
2. Transfer of the next byte and start-condition generation
• When an attempt is made to set the INT to 0 and the SCC bit to 1, writing the SCC bit is
given priority, and a start condition is generated.
3. Start-condition and stop-condition generation
• Do not simultaneously set the SCC bit to 1 and the MSS bit to 0.
(During writing)
0 Clears the transfer-end interrupt-request flag.
1 Inapplicable
(For Read)
0 Transfer has not completed.
1 When the transfer of 1 byte, including the acknowledge bit, ends, and one of the
following conditions is met, this bit is set.
•
Bus master is selected.
• The slave is addressed.
• General call address is received.
• Arbitration Lost occurred.
• When another system is using the bus, an attempt is made to generate a start
condition.