Fujitsu MB91150 Series, Hardware Manual, Page: 372 / 512

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CHAPTER 16 I
2
C INTERFACE
16.3.3 Address Register (IADR)/Data Register (IDAR)
The address register (IADR) is used to specify a slave address.
The data register (IADR) is used to perform serial transfer.
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Address register (IADR)
The address register (IADR) has the following bit configuration:
[bits 14 to 8] slave address (A6 to A0)
This register specifies a slave address. After address data is received in slave mode, it is
compared with that of the DAR register. If both values match, Acknowledge is transmitted to
the master.
■
Data register (IDAR)
The data register (IDAR) has the following bit configuration:
[bit 7 to 0] data bit (D7 to D0)
This data register is used to perform serial transfer, during which data is transferred starting
from the MSB. At the time of data reception (TRX=1), the output data value becomes 1.
This register has a double buffer on the writing side. When the bus is in use (BB=1), data to
be written is loaded into the serial transfer register at each byte transfer. Because the data of
the serial transfer register is directly read during data reading, received data is valid only
when the INT bit is set.
R/W: Can be read and written
0000_0122
H
Address
Bit15
−
−
Bit14
A6
R/W
Bit13
A5
R/W
Bit12
A4
R/W
Bit11
A3
R/W
Bit10
A2
R/W
Bit9
A1
R/W
Bit8
A0
R/W
Initial value -XXXXXXX
B
R/W: Can be read and written
0000_0125
H
Address
Bit7
D7
R/W
Bit6
D6
R/W
Bit5
D5
R/W
Bit4
D4
R/W
Bit3
D3
R/W
Bit2
D2
R/W
Bit1
D1
R/W
Bit0
D0
R/W
Initial value XXXXXXXX
B
: