Crystal CS4281, Programming Manual

Page: 14 / 231

CS4281 Programming Manual
DS308PRM1 14
Confidential Draft 3/7/00
Sound System - The Sound System is comprised of the SSC, the SRCs, and enabled for all peripherals.
The Sound System controls all logic in the
ABITCLK
domain.
TC - Two contexts.
Terminal Count. Terminal Count is part of a standard 8327 DMA controller and indicates, through
interrupts, when a programmed count rolls under. Either stops DMA operation or causes Current
Address and Count registers to reload if in auto initialize mode.
Target Codec. Target Codec is a bit the AC-Link interface section,
ACCTL.TC
. Determines which
codec (primary or secondary) and associated address and data registers (AC-Link slots 1 and 2) go
out on the
ASDOUT
line.
HTC - Half Terminal Count. Half Terminal Count is new to the CS4281 and indicates when the current
count (DCCn) counted half way down. Both
TC
and
HTC
interrupts support standard ping-pong
buffer architectures.
DMAn/FIFOn - Four DMAn/FIFOn pairs support four independent streams. The suffix ‘n’ designates
one of the four pairs, 0 through 3. The pairs cannot be split up. Therefore, the four pairs are
DMA0/FIFO0, DMA1/FIFO1, DMA2/FIFO2, DMA3/FIFO3. The DMAn engine supports transfer
of data between the corresponding FIFOn and the PCI bus in both DMA mode and Polled FIFO
mode. In Polled FIFO mode, the DMAn format register (DMRn) is used to convert the PC memory
audio data format to and from the internal 20-bit signed data format.
Formatter - The formatter converts sits between the FIFO memory and the PCI bus. It converts the host
memory data format to and from the CS4281-internal/Codec data format of 20-bit little-endian 2’s
complement. The DMRn register sets the format for a particular DMAn/FIFOn combination and is
utilized in both DMA and Polled FIFO modes.
DMA/Polled FIFO Modes - Audio data can be transferred between host memory and the FIFO memory
in two ways: DMA or Polled FIFO. The mode is set in the DMRn register along with the data format.
In the DMA mode, the DMAn bus-mastering engine, once enabled and configured, acquires the bus
and transfers audio without host software intervention. The DMAn engine transfers playback data
from host memory to FIFOn whenever space is available in the FIFO and transfers record data from
FIFOn to host memory whenever FIFOn has a sample (trying to keep the FIFO empty). In Polled
FIFO mode, host software is responsible for transferring audio data between host memory and
FIFOn via the Polled Data Register FPDRn. Generally host software sets up the FIFOn controller to
cause an interrupt when a certain FIFO depth is reached (
FSICn.FIC
bits). When interrupted, host
software would then fill or empty FIFOn accordingly.
Base Address - Refer to the PCI configuration space memory assigned to the CS4281. The main Base
Address is BA0, which defined a 4 k address space that provides access to all CS4281 internal
registers used to configure the part. The other rarely used Base Address is BA1, which holds the
FIFO memory and other internal memories that are only accessed in debug or test modes.
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