Crystal CS4281, Programming Manual

Page: 110 / 231

Confidential Draft 3/7/00
CS4281 Programming Manual
110 DS308PRM1
11.6 FIFO Hardware Implementation
The DMA engine configuration creates a 1 to 1 cor-
respondence between host buffers and FIFOs. The
FIFO configuration extends the correspondence to
the AC-Link data slots. The FIFO RAM starting
address is mapped into PCI memory space by the
PCI configuration Base Address 1. The FIFO RAM
is accessible from the PCI bus anytime that DMA
is not the bus master. This lets host software snoop
the DMA operation for debug and test purposes.
The FIFO-to-slot assignments are controlled by the
FIFO control registers. Each FIFO is composed of
a left and a right half that can be separately routed
to/from the AC-Link slots. The FIFO-to-slot as-
signment
FCRn.LS/RS
bits determine the direction
of the FIFO half connected to the AC-link slots.
The
DMRn.TR[1:0]
bits determine the direction of
transfers between the PCI bus and the FIFO for
both Polled and DMA modes. Both sides of the
FIFO must be programmed for the same FIFO di-
rection (PC bus to FIFO to AC Link, or AC link to
FIFO to PC bus).
In the CS4281, the starting addresses and sizes are
adjustable, so host software can fine tune the FIFO
depth for different applications. The FIFO depth
and offset can only be changed when the FIFO is
inactive (
FCRn.FEN
= 0). Each FIFO is defined by
a starting offset and length in stereo samples. The
default design will allocate 32 samples for each
stream. Each sample will be capable of holding
stereo 40-bit audio data, so the physical RAM size
is: (see Figure 37)
Logically (to host software), each sample will
appear as two double words in the host address
space. The PCI side will be able to control exactly
which channel of the sample pair gets read or
written. FIFO pointers do not move when the host
accesses the FIFO RAM directly. The formatter
converts the 20-bit internal FIFO data to the PCI-
bus 32-bit double-word little-endian format. The
logical RAM size is: (see Figure 38)
The FIFO RAM architecture is illustrated in
Figure 39.
The FCRn registers contain the Physical Address
Offset,
FCRn.OF[6:0]
and FIFO Size,
FCRn.SZ[6:0]
.
Seven bits for each covers the entire FIFO RAM
ending at location 127. These bits can only be
changed when the FIFO is disabled (
FCRn.FEN
clear).
The FIFO data is accessed by the Sound System
Controller (SSC) connected to the AC Link, or the
DMAn controller/formatter that transfers data
to/from the PCI bus. The SSC writes to FIFO’s
based on the AC-Link slot assignments (which de-
termine direction). The DMAn writes to FIFO’s
based on the
DMRn.TR[1:0]
transfer direction bits.
Figure 37. FIFO Hardware Physical RAM Size equation
Figure 38. FIFO Hardware Logical RAM Size equation
20
bits
channel
------------------ 2
channels
sample
---------------------
×
32
samples
stream
-------------------
×
4
streams
×
5120
bits
=
3
bytes
channel
------------------ 2
channels
sample
---------------------
×
32
samples
stream
-------------------
×
4
streams
×
768
bytes
=
4
bytes
channel
------------------ 2
channels
sample
---------------------
×
32
samples
stream
-------------------
×
4
streams
×
1024
bytes
=
D
ra
ft