Crystal CS4281, Programming Manual

Page: 186 / 231

Confidential Draft 3/7/00
CS4281 Programming Manual
186 DS308PRM1
20.3.2 General Purpose I/O Register (GPIOR)
Address: Host BA0: 3E8h, Read-Write
PCI CFG: 0E8h, Read-Write if CWPR configured, otherwise Read-Only
Default: 00000000h
Definition: Vaux powered. The General Purpose I/O register provides a host port for accessing extended
general-purpose I/O pins. This register is unaffected by the PCI
RST#
signal. The default value is
set by a Vaux POR signal. In addition to functionality in this register, these pins can generate a
host interrupt through the Host Interrupt Mask (HIMR) and Host Interrupt Status (HISR)
Registers. See the Interrupt Subsystem section for more details, and the figures below. They can
also generate PME# events. See Figure 18 in PCM# Assertion section for PME# conceptual logic.
Bit Descriptions:
VDNS
VOLDN
input Status: This bit reflects the status of the
VOLDN
input pin. If configured as
sticky (
VDNST
=1),
VDNS
reads one when the
VOLDN
pin goes active (edge sensitive - edge
defined by polarity bit
VDNPO
), and is cleared by writing a 0 to
VDNS
.
If configured as level sensitive (
VDNST
=0), this bit reflects the current state of the
VOLDN
pin
qualified by the polarity bit
VDNPO
.
VUPS
VOLUP
input Status: This bit reflects the status of the
VOLUP
input pin. If configured as
sticky (
VUPST
=1),
VUPS
reads one when the
VOLUP
pin goes active (edge sensitive - edge
defined by polarity bit
VUPPO
), and is cleared by writing a 0 to
VUPS
.
If configured as level sensitive (
VUPST
=0), this bit reflects the current state of the
VOLUP
pin
qualified by the polarity bit
VUPPO
.
GP1S
ASDIN2/GPIO1
input Status: Assuming this pin is not configured for
ASDIN2
, this bit reflects
the status of the
ASDIN2/GPIO1
pin. If
ASDIN2/GPIO1
is an output, this bit reflects the actual
state of the pin. If
ASDIN2/GPIO1
is an input:
If configured as sticky (
GP1ST
=1), this bit reads one when the
ASDIN2/GPIO1
pin goes active
(edge sensitive - edge defined by polarity bit
GP1PT
), and is cleared by writing a 0 to
GP1S
.
If configured as level sensitive (
GP1ST
=0), this bit reflects the current state of the
ASDIN2/GPIO1
pin qualified by the polarity bit
GP1PT
.
See the Serial Port Power Management Control (SPMC) register description of ASDI2E bit.
GP3S
GPIO3
input Status: This bit reflects the status of the
GPIO3
pin. If
GPIO3
is an output, this bit
reflects the actual state of the pin. If
GPIO3
is an input:
If configured as sticky (
GP3ST
=1), this bit reads one when the
GPIO3
pin goes active (edge
sensitive - edge defined by polarity bit
GP3PT
), and is cleared by writing a 0 to
GP3S
.
If configured as level sensitive (
GP3ST
=0), this bit reflects the current state of the
GPIO3
pin
qualified by the polarity bit
GP3PT
.
GPSS GP_INT input Secondary Status. A general purpose input pin on the Secondary Codec
(
ASDIN2
) caused slot 12, GP_INT to set (
SLT12M2.GP_INT
= 1). Writing
GPSS
= 0 clears the
locally stored copy; however, since the interrupt condition occurred in the Secondary Codec,
the condition must be removed through the Secondary Codec (
ACCTL.TC
= 1) GPIO Pin
Sticky register, Index 54h. See Figure 52.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GP3W GP3ST GP3PT GP3OE GP1W GP1ST GP1PT GP1OE VUPW VUPST VUPPO VUPLT VDNW VDNST VDNPO VDNLT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP3D GP1D GPPS GPSS GP3S GP1S VUPS VDNS
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