Crystal CS4281 Page 114 Programming Manual Download

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Confidential Draft

3/7/00

CS4281 Programming Manual

114

DS308PRM1

Summary of Contents for CS4281

Page 1: ...opyright Cirrus Logic Inc 2000 All Rights Reserved P O Box 17847 Austin Texas 78760 512 445 7222 FAX 512 445 7581 http www cirrus com CS4281 Programming Manual 3 7 00 Confidential Draft3 7 00 MAR 00 D...

Page 2: ...perty of Cirrus Logic Inc and implies no license under patents copyrights trademarks or trade secrets No part of this publication may be copied reproduced stored in a retrieval system or transmitted i...

Page 3: ...rted Cycles 45 5 1 3 Error Conditions 45 5 1 4 Protocol Support 45 5 2 Master Interface Properties 46 5 2 1 Generated Cycles 46 5 2 2 Cycles Not Generated 46 5 3 Configuration Space 47 5 3 1 Configura...

Page 4: ...ing Registers 80 10 4 1 Host Interrupt Status Register HISR 80 10 4 2 Host Interrupt Control Register HICR 81 10 4 3 Host Interrupt Mask Register HIMR 82 10 4 4 ISA Interrupt Enable Register IIER 83 1...

Page 5: ...gister SBRR 141 16 2 4 Sound Blaster Read Data Port SBRDP 142 16 2 5 Sound Blaster Write Data Port SBWDP 142 16 2 6 Sound Blaster Write Buffer Status SBWBS 143 16 2 7 Sound Blaster Read Buffer Status...

Page 6: ...M Data Port FMDP 180 19 1 4 Bank 1 Address Port B1AP 180 19 1 5 Bank 1 Data Port B1DP 180 20 PERIPHERAL DEVICES 181 20 1 Hardware Volume Control 181 20 2 Clock Control 182 20 2 1 Clock Control Registe...

Page 7: ...CDA 218 22 5 8 AC 97 Input Slot Valid Register ACISV 219 22 5 9 AC 97 Status Address Register ACSAD 219 22 5 10 AC 97 Status Data Register ACSDA 220 22 5 11 Slot 12 Output Register for AC Link Codec S...

Page 8: ...Confidential Draft 3 7 00 CS4281 Programming Manual 8 DS308PRM1 D r a f t...

Page 9: ...upt Conceptual Logic 86 Figure 22 Polled FIFO Interrupt Conceptual Logic 87 Figure 23 Formatter Block Diagram 89 Figure 24 8 bit PCI Data Transfers 90 Figure 25 16 Bit PCI Data Transfers 90 Figure 26...

Page 10: ...gic 189 Figure 50 ASDIN2 GPIO1 Conceptual Logic 190 Figure 52 AC Link Slot 12 GP_INT Conceptual Logic 190 Figure 51 VOLUP VOLDN GPIO Conceptual Logic 191 Figure 53 MIDI UART Architecture 193 Figure 54...

Page 11: ...lation 150 Table 19 Stereo SB TC to Sample Frequency Translation 152 Table 20 Sound Blaster Direct Registers 153 Table 21 Sound Blaster Mixer indirect registers 158 Table 22 SB Pro Mixer All Read Valu...

Page 12: ...Confidential Draft 3 7 00 CS4281 Programming Manual 12 DS308PRM1 D r a f t...

Page 13: ...hannel but DMRn SWAPC can swap the channels making DMA Channel 1 the FIFO Right Channel With respect to the FM synthesizer an FM sound or voice is termed a channel and can be generated with up to four...

Page 14: ...Formatter The formatter converts sits between the FIFO memory and the PCI bus It converts the host memory data format to and from the CS4281 internal Codec data format of 20 bit little endian 2 s com...

Page 15: ...odec Specifica tion version 2 1 This document specifies the programming manual for the CS4281 This document also describes the CS4281 s system interfaces configuration meth ods programmable options op...

Page 16: ...ntrol DLL Clock Control Formatter DMA Controller FM Synthesizer Playback SRC Capture SRC Sound System Controller AC Link Interface MIDI Port Game Port Hardware Volume Control Control Block Sound Syste...

Page 17: ...ec then up to three streams are supported simultaneously from one AC Codec stereo audio in and two stereo audio out 4 channel streams Some modem configurations will use a single Au dio Modem codec suc...

Page 18: ...t Audio In AC Link Figure 3 Audio Modem Codec Host Modem Block Diagram PORTABLE DOCKING STATION CPU North Bridge Host Memory PCI Bus South Bridge Bridge buffer CS4297A CS4297A CS4281 Audio Out Audio I...

Page 19: ...1 channel data and using one stream send it through the CS4281 to a CS4298 97A 99 that supports an S PDIF output The second method is using a filter on the host to decompress the 5 1 streams into 6 c...

Page 20: ...eg ister The formatter converts the PC bus audio data to the internal 20 bit signed format For playback FIFOn sends a signal to the DMAn engine indicat ing FIFOn is not full The DMAn engine responds b...

Page 21: ...pins are set by the Codec it self The SSC knows which FIFOn to connect to Slot y via slot mapping IDs in the FIFOn FCRn register If the Record SRC is configured for the same slot IDs as FIFOn the audi...

Page 22: ...0 specification Figure 8 illustrates the standard connection of one AC 97 codec to the CS4281 where the Codec sup plies the master clock ABITCLK to the CS4281 Two AC 97 codecs are supported as long a...

Page 23: ...JACY JBCX JBCY JAB1 JAB2 JBB1 JBB2 Joystick MIDI Port BIT_CLK SYNC SDATA_OUT SDATA_IN RESET 24 576 MHz CS4297 97A 12 288 MHz 48 kHz ASDIN2 BIT_CLK SYNC SDATA_OUT SDATA_IN RESET CS4297A AC 97 2 0 CS42...

Page 24: ...Confidential Draft 3 7 00 CS4281 Programming Manual 24 DS308PRM1 D r a f t...

Page 25: ...a like from Mahler with all the bugs fixed It will sport a new testability section and use a new gated clock tech nique to save power The Peripheral Devices are the various support stuff This section...

Page 26: ...not guaranteed at these extremes RECOMMENDED OPERATING CONDITIONS PCIGND CGND CRYGND 0 V all voltages with respect to 0 V Parameter Symbol Min Typ Max Unit Power Supplies PCIVDD VAUX CVDD CRYVDD VDD5...

Page 27: ...en drain outputs Parameter Symbol Min Max Unit Switching Current High Note 5 0 Vout 1 4 1 4 Vout 2 4 3 1 Vout 3 3 IOH 44 Equation A mA mA Switching Current Low Note 5 Vout 2 2 2 2 Vout 0 55 0 71 Vout...

Page 28: ...out Equation C mA mA mA Switching Current Low Note 7 Vcc Vout 0 6 Vcc 0 6 Vcc Vout 0 1 Vcc 0 18 Vcc Vout 0 IOL 16 Vcc 26 7 Vout Equation D mA mA mA Low Clamp Current 3 Vin 1 ICL mA High Clamp Current...

Page 29: ...iven it should be tied to power or ground depending on the particular function If an I O pin is not driven and programmed as an input it should be tied to power or ground through its own resistor Para...

Page 30: ...floated when RST is active Note ASDOUT and ASYNC are not affected by RST Parameter Symbol Min Max Unit PCICLK cycle time tcyc 30 ns PCICLK high time thigh 11 ns PCICLK low time tlow 11 ns PCICLK to s...

Page 31: ...40 7 45 ns ABITCLK input low time tclk_low 36 40 7 45 ns ABITCLK input rise fall time trfclk 2 6 ns ASDIN ASDIN2 valid to ABITCLK falling tsetup 10 ns ASDIN ASDIN2 hold after ABITCLK falling thold 10...

Page 32: ...ernal pull up resistor Parameter Symbol Min Max Units EECLK Low to EEDAT Data Out Valid tAA 0 7 0 s Start Condition Hold Time tHD STA 5 0 s EECLK Low tLEECLK 10 s EECLK High tHEECLK 10 s Start Conditi...

Page 33: ...ecifications are valid for audio sample rate of 48 kHz Other sample rates will have somewhat worse performance 3 4 Implied Functional Specs Implied functional specifications are the un tabu lated expe...

Page 34: ...Confidential Draft 3 7 00 CS4281 Programming Manual 34 DS308PRM1 D r a f t...

Page 35: ...64 CGND 3 65 ASDIN2 GPI01 66 PME 67 VAUX 68 CRYVDD 69 VOLUP 70 VOLDN 71 CRYGND 72 VDD5REF 73 ABITCLK 74 ASDOUT 75 ASDIN 76 ASYNC 77 ARST 78 EECLK GPOUT PCREQ 79 EEDAT GPIO2 PCGNT 80 30 PCIGND 5 29 AD...

Page 36: ...QB 15 IRQC 14 TRDY 13 IRDY 12 FRAME 11 C BE 2 10 CGND 1 9 CVDD 1 8 AD 16 7 AD 17 6 AD 18 5 PCIVDD 3 4 PCIGND 3 3 AD 19 2 AD 20 1 AD 21 50 JACY 49 JACX 48 TEST 47 PCIVDD 7 46 PCIGND 7 45 AD 0 44 AD 1 4...

Page 37: ...ndicates even parity across AD 31 0 and C BE 3 0 for both address and data phases The signal is delayed one PCI clock from either the address or data phase for which parity is generated FRAME Cycle Fr...

Page 38: ...t Input Active Low GNT is driven by the system arbiter to indicate to the device that the PCI bus has been granted PERR Parity Error Input Output Active Low PERR is used for reporting data parity erro...

Page 39: ...is active The bus controller drives CLKRUN low when it wants to stop the PCICLK As an output driven low to request that the PCICLK be activated or not stopped If not used this pin must have a weak pul...

Page 40: ...then the MIDIIN and four joystick button pins determine the test mode This pin has super hysteresis input buffer TESTSEL Test Mode Select Input with Pullup This pin selects the active test mode while...

Page 41: ...trol Up Input Input Output with Pullup Active Low input Volume down button control input This pin has an internal pullup and is internally debounced VOLUP and VOLDN together going low cause the master...

Page 42: ...ata Output This is the serial output pin for the internal MIDI port CVDD 2 1 Core Power Power 3 3 Volt core power pins CGND 3 1 Core Ground Ground Core ground reference pins 4 3 5 Serial Codec Interfa...

Page 43: ...pose IO Pin 1 Input Output Serial data input for Secondary AC 97 2 0 compatible codec or general purpose input selected via the SPMC ASDI2E bit This pin is powered from the VAUX power pin to support w...

Page 44: ...Confidential Draft 3 7 00 CS4281 Programming Manual 44 DS308PRM1 D r a f t...

Page 45: ...Cycles Dual Address Cycle 5 1 3 Error Conditions There are no target abort error conditions signaled 5 1 4 Protocol Support Configuration Space Accesses Byte enables are supported byte word doubleword...

Page 46: ...esses Byte enables are supported No bursting disconnect after first data phase if a burst access is attempted 5 2 Master Interface Properties 5 2 1 Generated Cycles Memory Read Memory Write I O Read 5...

Page 47: ...Cycles R O 0 Bit 2 Bus Master Enable R W default 0 Bit 1 Memory Space Enable R W default 0 Bit 0 I O Space Enable R O 0 04h Class Code R O 040100h Class 04h multimedia device Sub class 01h audio Inte...

Page 48: ...000 default Bit 5 Device specific init R O 1 Bit 4 Auxiliary power R O 0 default Bit 3 PME clock R O 0 Bit 2 0 Version R O 010 Rev 1 1 compliant Next Item Ptr R O 00h Capability ID R O 01h 40h Data R...

Page 49: ...initialize this register before use Bit Descriptions CWP 15 0 Configuration Write Protect Configuration space addresses 0E4h through 0FFh are read only unless the CWP bits are set to 4281h This provid...

Page 50: ...Ch Read Write if CWPR configured otherwise Read Only PCI CFG 02Ch Read Only Default 00000000h Definition Vaux powered The Subsystem Vendor ID Subsystem ID Pre load register provides a host port for in...

Page 51: ...h are memory mapped into host address space Both interface blocks can be located anywhere in 32 bit physical address space as defined by the address pro grammed into the two base address registers in...

Page 52: ...1Ch DBC0 DMA Engine 0 Base Count Register Core PCI 99 120h DCA1 DMA Engine 1 Current Address Register Core PCI 98 124h DCC1 DMA Engine 1 Current Count Register Core PCI 100 128h DBA1 DMA Engine 1 Base...

Page 53: ...ower Management Control Vaux Vaux 71 3E8h GPIOR GPIO Pin Interface Register Vaux Vaux 186 3ECh SPMC Serial Port Power Management Control ASDIN2 enable Vaux Vaux 212 3F0h CFLR Configuration Load Regist...

Page 54: ...mand Slot Disable for secondary link RO Core Peri 217 4B0h CFGI Configuration Interface Register EEPROM interface Core Ctrl 223 4B4h Reserved 4BCh 4D8h Reserved 4DCh SLT12M2 Slot 12 Monitor Register 2...

Page 55: ...mple Rate Capture SRC Core Ctrl 168 74Ch SSCR Sound System Control Register Core Ctrl 169 750h Reserved 754h FMLVC FM Synthesis Left Volume Control Core Ctrl 170 758h FMRVC FM Synthesis Right Volume C...

Page 56: ...bits are affected by the PCI RST reset signal Offset Name Description Power From Size Page 06h PCIST PCI Status Core word 66 34h CAPPTR Capabilities Pointer RO Core byte 67 40h CAPID Capabilities ID...

Page 57: ...are loaded into the CFLR register at PCI config location F0h where F0h and F1h are Inky s CFL1 and CLF2 respectively Bytes at locations F2h and F3h are new to the CS4281 These four bytes can also be l...

Page 58: ...SSPM FMEN 1 Enable Joystick if needed SSPM JSEN 1 Wait for clock stabilization CLKCR1 DLLRDY CLKCR1 CLKON 1 Enable ASYNC generation ACCTL ESYN 1 Wait for Codec ready ACSTS CRDY ACSTS2 CRDY2 Enable Va...

Page 59: ...h DAC bit Setup interrupts DCRn TC half TC or both for ping pong buffer HIMR HICR Enable FIFOn FCRn FEN Enable AC Link Output Slot Valid Bits ACOSV 8 2 2 Sound System Record The following DMA sequence...

Page 60: ...slot pairs and the appropriate six output slot valid bits ACOSV must be set when everything else is configured The following list describes what registers inside the AC 97 co decs need to be configur...

Page 61: ...2 xxxEh xxxFh REF ANL DAC set Set CS4294 to Mode 3 and bypass mixer DDM Write secondary codec Index 5Eh 0103h In general the output mixer would not be used on the surround channels Write Command regis...

Page 62: ...or BIOS pre load This register is unaffected by the PCI RST signal The default value is set by a Vaux POR signal The BIOS can pre load this register by writing to it in configuration space The followi...

Page 63: ...er management when changing between states thereby having all power management controlled through software Assuming the CS4281 is pro grammed to manage power automatically the fol lowing would be a ty...

Page 64: ...ove Ta ble where the CS4281 is automatically controlling the power to the CS4281 Remove VDD RST Active D0uninitialized D0active D3hot D3cold D1 Soft Reset Power State changed from D3 to D0 Hard Reset...

Page 65: ...wo status bits GPI OR GPPS for the primary codec and GPIOR GPSS for the secondary codec These bits can generate a PCI interrupt which is maskable through the HICR register The interrupt is cleared by...

Page 66: ...0 indicating the CS4281 doesn t support user definable features FBBC Fast Back to Back Capable Read only bit set to 0 indicating the CS4281 doesn t support fast back to back transactions DPED PERR De...

Page 67: ...3 3 Capabilities ID Address PCI CFG 40h Read Only BA0 340h Read Only Default 01h Definition This register holds a value identifying the register block as belonging to PCI power management Bit Descript...

Page 68: ...100 mA 011 160 mA 100 220 mA 101 270 mA 110 320 mA 111 375 mA spec maximum DSI Device Specific Initialization Set to 1 to indicate the CS4281 needs to be programmed to be useful Note that Microsoft op...

Page 69: ...n enables or disables the capability to assert PME When read indicates the current PME assertion capability When IISR VAUXS 1 the PMEEN bit is unaffected by the PCI RST signal When IISR VAUXS 0 the PM...

Page 70: ...BPCCE Bus Power Clock Control Enable Reads return zeros The last PCI standard power management register is part of a facility allowing a device to describe its pow er consumption in the power manageme...

Page 71: ...trol status register Writes 0 Don t generate a wake up event reset default 0 to 1 transition Generate a wake up event D1ART D1 ARST enable When the PS 1 0 bits are in the D1 state and D1ART is set the...

Page 72: ...ing to the AC Link is driven active similar to setting SPMC RSTN 0 D2DLL D2 DLL disable When the PS 1 0 bits are in the D2 state and D2DLL is set the DLL is turned off powered down similar to CLKCR1 D...

Page 73: ...down Codecs compliant with the AC 97 2 0 specification use this mechanism to signal a wake up event to the AC 97 controller GP_INT being set in SLT12M or SLT12M2 when the AC Link is powered up See Fig...

Page 74: ...s the affect that the power down bit EPPMC FPDN and chip reset have on each block within the CS4281 For some internal blocks the affect of these two signals are the same for oth er blocks their affect...

Page 75: ...its are clear or when ABITCLK is off These bits are forced clear by the EPPMC FPDN power down bit PCI RST signal or core POR signal In power down or reset State machine in reset includes the Sound Sys...

Page 76: ...core POR signal This block also internally resets when ABITCLK goes away In power down or reset ABITCLK don t care ASYNC ASDOUT forced low ASDIN ASDIN2 ignored Reset state machines Registers held in r...

Page 77: ...upts Host MIDI Status Register MIDSR reads clear the transmit and receive interrupts Interrupts are normally generated on the PCI INTA pin ISA interrupts are available for mother board CS4281 devices...

Page 78: ...ogic Diagram DCRn and HDSRn ISA IRQC Pin PCI CFG IISR IRQC0 IRQC1 IRQC2 IRQC3 IIER ICEN ISA IRQB Pin PCI CFG IISR IRQB0 IRQB1 IRQB2 IRQB3 IIER IBEN ISA IRQA Pin PCI CFG IISR IRQA0 IRQA1 IRQA2 IRQA3 II...

Page 79: ...an be configured through the GPIOR register to cause interrupts Four pins have this capability GPIO3 ASDIN2 GPIO1 VOLUP VOLDN All GPIO interrupts are cleared by writing a 0 to the appropriate status b...

Page 80: ...ing the FIFOI flag Cleared by reading the associated FCHSn register for the FIFO s that caused the interrupt DMA 3 0 DMAn engine interrupt status A 1 indicates the DMAn that s causing the DMAI flag Cl...

Page 81: ...4 2 Host Interrupt Control Register HICR Address BA0 008h Read Write Default 00000000h Definition Core powered The Host Interrupt Control register provides a host write port for EOI and discrete mask...

Page 82: ...ndividual DMA engine GPPIM General Purpose Input from Primary AC 97 Link ASDIN slot 12 GP_INT interrupt mask GPSIM General Purpose Input from Secondary AC 97 Link ASDIN2 slot 12 GP_INT interrupt mask...

Page 83: ...be non zero Note that in backward compatible sockets IRQA was the PCI signal SERR IRQB was a Core VDD power supply and IRQC was a Core ground pin Bit Descriptions ICEN IRQC ISA interrupt Enable 0 IRQC...

Page 84: ...tion Flags These bits are read writable and available in config and host memory space They have no direct affect on the operation of the CS4281 and may be used by host software when communicating with...

Page 85: ...be 0 since channels are atomic If DBAn BAL1 0 then the 32 bit sample is 32 bit aligned and the DMA engine will do 1 PCI access per sample transferring both channels simultaneously If DBAn BAL1 1 then...

Page 86: ...11 1 2 Host Interrupts in FIFO Polling Mode Host interrupts can also be generated for Polled FIFO modes All interrupts are masked through the Host Interrupt Mask Register HIMR and the inter rupt stat...

Page 87: ...he FIFOs Internal to the CS4281 audio data is always 20 bit signed 2 s complement integers Audio samples can be either monaural or binaural that is stereophonic Monaural audio data is a sin gle channe...

Page 88: ...ght then left opposite to normal operation When the formatter reads mono data from the FIFO it must read both sides of the FIFO left and right Channel Valid signals so the FIFO read pointer moves The...

Page 89: ...1 Ch2 Byte Swizzler 32 bit Temp Register OE FIFO RAM OE Byte Swizzler Ch1 Ch2 40 40 32 32 PCI BUS DMA engine Ch1 Valid Ch2 Valid Left Ch Valid Right Ch Valid 40 32 bit Shadow Register 1 0 Capture DMA...

Page 90: ...FIFO or 2 PCI cycles or 2 PCI cycles msb msb msb msb 1 2 1 2 8 bit Ch2 8 bit Ch1 8 bit Ch2 8 bit Ch1 8 bit Ch2 8 bit Ch1 8 bit Ch1 8 bit Ch2 Figure 24 8 bit PCI Data Transfers 31 23 15 7 0 PCI Bus or...

Page 91: ...e Swizzler formats Channel One properly and sends the data on to the FIFO When the second channel arrives the DMA engine indi cates that Ch2 is valid the Byte Swizzler formats Channel Two properly and...

Page 92: ...the write pointer If the formatter gets two Ch1 valid signals in a row the new data replaces the old data in the FIFO and it still waits for the other channel The same is true when reading the FIFO Wi...

Page 93: ...mples mis aligned For 20 bit formats the Byte Swizzler changes host memory format into FIFO format as depicted in Figure 33 for stereo little endian Figure 35 for ste reo big endian and Figure 36 for...

Page 94: ...H 16BitC2 L L ChL LChr R ChH R ChL RChr L ChH Figure 32 16 Bit Little Endian Formats 31 23 15 7 byte 3 byte 2 byte 1 byte 0 0 0 19 20 39 20BitC1 H 20BitC1 L 20 bit signed FIFO data Host Memory 20BitC1...

Page 95: ...transfer 20BitC1 r 20BitC1 L 20BitC1 H 20BitC2 r 20BitC2 L 20BitC2 H L ChL LChr R ChH R ChL RChr L ChH 31 23 15 7 byte 3 byte 2 byte 1 byte 0 0 0 19 20 39 20BitL H 20BitL L 20 bit signed FIFO data Ho...

Page 96: ...sferred at a time even if other samples fit within the double word alignment 11 4 DMA Control Register Operation DMA operations are setup as follows The host Address Register is set to point at the da...

Page 97: ...tereo format if BAL0 0 the sample is word aligned and the DMA controller will transfer complete samples in one PCI bus cycle If BAL0 1 the sample is mis aligned and the DMA controller will transfer th...

Page 98: ...by address increment decrement and is just the upper word of the linear 32 bit address CAH 7 0 Current Address lower word Upper byte CAL 7 0 Current Address lower word Lower byte DMRn SIZE20 DMRn SIZ...

Page 99: ...ts occur on roll unders When any byte of this register is loaded the same Current Count register byte is loaded This register also reloads the DMA Current Count Register during auto initialize operati...

Page 100: ...f transfers to go 1 When the count transitions from 00000000 to FFFFFFFFh TC for this engine is generated If auto initialize is set DMRn AUTO then the DMA Base Count register DBCn will be loaded into...

Page 101: ...r By Channel When set this bit forces stereo data to be transferred one channel at a time across the PCI bus for 8 and 16 bit data formats When clear the DMA controller decides whether to transfer ste...

Page 102: ...1 disables a FIFO channel on the AC Link side SIZE8 Sample is 8 bit This bit and the SIZE20 bit cannot both be active SIZE8 takes precedence over SIZE20 TYPE 1 0 Transfer Mode Select used in DMA and P...

Page 103: ...nable When set an interrupt is generated on Half TC midway through buffer when used in DMA mode To support ping pong buffers both HTCIE and TCIE should be set which will cause interrupts at both the h...

Page 104: ...n DMRn SWAPC is set CH2P Channel 2 Pending This bit is set when DMAn is requesting the second channel data This bit is always clear when sending mono data or when stereo samples are transferred as an...

Page 105: ...If RS 4 0 matches a channel in one of the sample rate converters SRC the SRC is placed between this FIFO and the AC Link Only one FIFO can be linked to an SRC playback or record SRCSA Said another way...

Page 106: ...erRun Interrupt Enable When set an interrupt can be generated on an underrun condition FSCIE FIFO Sample Count Interrupt Enable When set a interrupt can be generated when the FIFO Interrupt Count equa...

Page 107: ...hen set for FIFO to host direction will just go in the bit bucket the FIFO controller will ignore the data Data transfers are atomic based on the attached DMRn TBC bit If data transfers are atomic on...

Page 108: ...s been written at the current FIFO write pointer location The write pointer will not be incremented until the other channel is received IOR 3 0 Internal Overrun Flag Set when one channel written to a...

Page 109: ...be swapped LS 4 0 RS 4 0 AC 97 Input Slot AC 97 Codec AC 97 Slot Function 10 3 Primary Left PCM Record 11 4 Primary Right PCM Record 12 5 Primary Phone Line 1 ADC 13 6 Primary Mic ADC 14 7 Primary res...

Page 110: ...th in stereo samples The default design will allocate 32 samples for each stream Each sample will be capable of holding stereo 40 bit audio data so the physical RAM size is see Figure 37 Logically to...

Page 111: ...ting the FSICn FOR bit This bit remains set until the host reads FSICn A FIFO could be empty under two conditions if it was just turned on or if the FIFO is active and data was read from the FIFO fast...

Page 112: ...LCI3 The SSC gets AC Link primary slot 4 and sends it to FIFO1 right channel FIFO1 controller sets RCI1 Now both bits are set write pointer moved both status bits cleared The SSC gets AC Link secondar...

Page 113: ...flag is used to manage the read pointer when a FIFO is empty The Move Read Pointer FCHS MRPn flag stores the fact that the read pointer is one location behind where is should be When new data is plac...

Page 114: ...Confidential Draft 3 7 00 CS4281 Programming Manual 114 DS308PRM1 D r a f t...

Page 115: ...sters to support Sound Blaster FM and the Gameport The custom I O trapping is designed to support three different types of legacy DMA DDMA PC PCI and CrystalClear Legacy CCLS When configured for DDMA...

Page 116: ...raph The shared 8237 registers are problematic Most of these registers are write only and the CS4281 handles them by eavesdropping snooping on I O write transactions and storing the captured data in a...

Page 117: ...ns The DLY number does not include the normal clocks required by the bus interface logic For example if the but interface logic normally takes 5 PCICLKs to complete the transaction and DLY 3 0 3 then...

Page 118: ...d write transactions The DLY number does not include the normal clocks required by the bus interface logic For example if the but interface logic normally takes 5 PCICLKs to complete the transaction a...

Page 119: ...will take 8 cycles Up to 15 clocks can be added IODC 1 0 I O Decode Control These two bits control how many I O address bits are decoded for the trap range 0 0 Decode SA15 down to SA2 bits of I O add...

Page 120: ...A 15 4 DmaBase Start Address Starting PCI I O space address of the trap range For Crystal DMA this address should be set to 0 For DDMA this address should be set similar to the motherboard chipset for...

Page 121: ...bits are used to selectively mask off the lower four bits of address accompanying an I O transaction After the mask operation is performed the resulting address is compared against SA 15 0 if they ar...

Page 122: ...te access to the Base Current Count and Base Current Address DMA registers not the Address Page register 0 Write trapping disabled reset default 1 Write trapping enabled C1WSE CCLS 1 Write Snoop Enabl...

Page 123: ...series of steps which starts with telling the host to retry the cycle Then for the Status register the CS4281 reads the real 8237 location 08h combines the other engine status with the proper status b...

Page 124: ...bal I O trapping enabled if IISR GTD is clear EDMA 1 0 Enable DMA Trapping Defines the DMA trapping logic behavior 00 No DMA trapping use new DMA support reset default 01 CCLS Legacy DMA proprietary 8...

Page 125: ...PFF determines 00h read Ch 0 Current Address 3DCA0 16 bit 1 byte at a time IOTCC BPFF determines 01h write Ch 0 Base Current Count 3 DBC0 16 bit 1 byte at a time IOTCC BPFF determines 01h read Ch 0 Cu...

Page 126: ...y registers Single Mask and Mode where the lower two bits determine the mapping to CS4281 DMAn registers DCRn and DMRn respectively Trapping for these registers is controlled through the IOTCC C3WSE b...

Page 127: ...8237 location 08h CS4281 stores legacy 08h data in DLSR register Legacy bits in DLSR are read only therefore writing this register combines host status with CS4821 DMA status Host retries the read of...

Page 128: ...ter at location 08h is not supported This write only register enables disables the entire DMA chip sets priority and DRQ DACK polarity No game should ever hit this register since it affects the operat...

Page 129: ...See the PC PCI section for functional details Dma Base Access Name 1 Host Reg Comment 08h write Command no trap CS4281 currently doesn t support 08h 3Status DLSR Request Pending and TC status 09h wri...

Page 130: ...ses to DmaBase 00 through DmaBase 0Fh for read and write operations The CS4281 DMA engine registers are setup to operate like DDMA therefore the I O Trap mechanism only redirects the I O based on the...

Page 131: ...the PC PCI engine is enabled The following bits are related to PC PCI operation BIOS should set CFLR CB1 1 0 bits to indicate that PC PCI is used and which channel IOTPCP register setup to read and wr...

Page 132: ...ating in normal mode If no other DMAn en gines need access to the PCI bus when PCGNT is de asserted the Legacy DMAn engine reasserts the PCREQ with the encoded data and waits for an other grant on PCG...

Page 133: ...ne can reassert PCREQ with serial data after PCGNT goes high The memory write cycle length can vary The I O read cycle length is based on the CS4281 A playback sequence is illustrate in Figure 46 in w...

Page 134: ...amming Manual DS308PRM1 134 Confidential Draft 3 7 00 PCICLK PCREQ PCGNT FRAME IRDY A D A AD 31 0 C BE C C BE 3 0 DEVSEL TRDY Cycle Type mem Read CS4281 I O Write BE D Figure 46 PC PCI Playback Sequen...

Page 135: ...t 2 This bit is always 0 since the CS4281 does not support any DMA channel above 3 RDC1 Requested DMA Engine bit 1 This bit is a copy of IOTCR DMA1 RDC0 Requested DMA Engine bit 0 This bit is a copy o...

Page 136: ...rom the host PC PCI agent and the PC PCI engine automatically clears VL when a DMA transfer completes or is terminated 14 1 3 PC PCI Control Register PCPCR Address BA0 608h Read Write Default 0000h De...

Page 137: ...e Legacy Base Count Current high DBCn BCH 7 0 DCCn BCH 7 0 05h read Legacy Current Count high DCCn BCH 7 0 06h write Base Count bits 16 23 bit bucket optional in DDMA 06h read Current Count bits 16 23...

Page 138: ...CS4281 IOTDMA register base and let the host DDMA engine know where the CS4281 DDMA engine is mapped The Host DDMA engine traps Legacy DMA requests and redirects the request to as many as 4 DDMA engi...

Page 139: ...e appropriate function Sound Blaster ADPCM is supported by a ADPCM engine in the DSP controller Full ADPCM 2 1 ADPCM4 decompression is supported The ADPCM 3 1 ADPCM2 6 and 4 1 ADPCM2 are decompressed...

Page 140: ...Bbase 0 Left FM Register Address Port Write 730h SBbase 1 Left FM Data Port Read Write 734h SBbase 2 Right FM Status Port Read 738h SBbase 2 Right FM Register Address Port Write 738h SBbase 3 Right FM...

Page 141: ...simultaneously using PC word accesses Bit Descriptions MD 7 0 Mixer Data 16 2 3 Sound Blaster Reset Register SBRR Address BA0 708h Write Only I O SBbase 6 Default 000000FFh Definition Controls Sound B...

Page 142: ...Read Data 16 2 5 Sound Blaster Write Data Port SBWDP Address BA0 710h Write Only I O SBbase C D Default 00000000h Definition Write data port for Sound Blaster Command and data access When SBWBS WBE 1...

Page 143: ...d Buffer Status SBRBS Address BA0 714h Read Only I O SBbase E F SB Reset Default 0000002Ah will change to AAh after delay POR Default 00000000h SSCR SB 0 Definition Read status port for Sound Blaster...

Page 144: ...mple from 6 kHz to 48 kHz 16 4 Sound Blaster Mixer This block communicates with the SB DSP block as well as the PCI interface and AC link Some of its data is required by the DSP and also a few DSP com...

Page 145: ...aster Volume Mono Out Disable When set register 0x06 is NOT updated The Sound Blaster mixer supports independent volume controls for the FM and the PCM PSRC path Since the CS4281 mixes FM digitally be...

Page 146: ...rollable through the SSCR register bits MVCS MVLD MVAD MVMD See text for more information Table 14 Sound Blaster Mixer Mapping to AC 97 Registers SB Volume Value Master Volume Line CD Volume Voice FM...

Page 147: ...tch from PCI to ISA interrupts HIMR IIER Turn on Sound Blaster and FM SSCR SB 1 SSPM FMEN 1 Disable Host Interrupts from legacy DMA DCRn interrupt enable bits 0 Setup and turn on legacy I O trapping f...

Page 148: ...c1 mic2 line_in cd video aux line_out hp_out mono_out PCM playback PCM capture mic line_in cd C S 4 2 8 1 A C 9 7 p a r t MIC MIX CD VOL LINE VOL INPUT SELECT MASTER VOL VOICE VOL FM VOL MIC MIX LINE...

Page 149: ...er command The Data Available bit is used to indicate when the CS4281 has responded to a SB command with the required data Reading this register also clears any Sound Blaster generated interrupts The...

Page 150: ...27 0 36 225 110 6849 6857 0 12 224 111 6896 6919 0 33 222 112 6944 6950 0 09 221 113 6993 7014 0 30 219 114 7042 7046 0 05 218 115 7092 7111 0 27 216 116 7142 7144 0 03 215 117 7194 7211 0 24 213 118...

Page 151: ...29 16000 0 80 3 195 16393 16516 0 75 93 196 16666 16696 0 18 92 197 16949 17067 0 69 90 198 17241 17258 0 10 89 199 17543 17655 0 64 87 200 17857 17860 0 02 86 201 18181 18286 0 58 84 202 18518 18506...

Page 152: ...2 0 31 151 208 10416 10378 0 36 148 Table 19 Stereo SB TC to Sample Frequency Translation 209 10638 10593 0 42 145 210 10869 11025 1 44 4 211 11111 11025 0 77 4 212 11363 11378 0 13 135 213 11627 1163...

Page 153: ...nment bits in the FCRn associated with the legacy DMAn engine This forces the playback SRC to be connected to the proper FIFO Host soft ware must set the Playback SRC mapping to the de sired slots typ...

Page 154: ...Descriptions MAD 7 0 Mixer Address 17 2 2 Sound Blaster Mixer Data Register SBMDR Address BA0 704h Read Write I O SBbase 5 Default 00000011h Definition The data port for reading and writing the select...

Page 155: ...scriptions SBR Reset control bit 17 2 4 Sound Blaster Read Data Port SBRDP Address BA0 70Ch Read Only I O SBbase A B Default 000000AAh Definition Read data port for Sound Blaster Command and data acce...

Page 156: ...ase C D SB Reset Default 000000AAh will change to 2Ah after delay POR Default 0000002Ah SSCR SB 0 Definition Write status port for Sound Blaster Command and Data write access Bit Descriptions WBB Writ...

Page 157: ...n Read status port for Sound Blaster Command and Data read access When bit 7 is a 1 new read data is available in the data read port Reading this register also clears all Sound Blaster generated inter...

Page 158: ...Mixer Mapping onto the AC 97 CS4281 Mixer The Sound Blaster Mixer is mapped onto the AC 97 generic mixer and the digital portion on board the CS4281 chip as described in the follow ing table Since the...

Page 159: ...The CS4281 will write the appropriate volume to the Master Input Volume depending on which in put is selected by the Input Setting Register The Input Select to AC Link translations are in Table 25 The...

Page 160: ...ine In Volume Master Input Volume x10 15 8 x10 7 0 4 Master Volume mapping is software controllable through the SSCR register bits MVCS MVLD MVAD MVMD See text for more information Table 23 Sound Blas...

Page 161: ...s from legacy DMA DCRn interrupt enable bits 0 Setup and turn on legacy I O trapping for SB FM and Game Port IOTSB IOTFM and IOTGP If PC PCI set up PC PCI registers and I O Trap for PC PCI IOTPCP and...

Page 162: ...c1 mic2 line_in cd video aux line_out hp_out mono_out PCM playback PCM capture mic line_in cd C S 4 2 8 1 A C 9 7 p a r t MIC MIX CD VOL LINE VOL INPUT SELECT MASTER VOL VOICE VOL FM VOL MIC MIX LINE...

Page 163: ...81 is still busy executing a Sound Blaster command The Data Available bit is used to indicate when the CS4281 has responded to a SB command with the required data Reading this register also clears any...

Page 164: ...120 7352 7349 0 04 209 121 7407 7420 0 18 207 122 7462 7456 0 08 206 123 7518 7529 0 15 204 Table 27 Mono SB TC to Sample Frequency Translation 124 7575 7567 0 11 203 125 7633 7642 0 12 201 126 7692 7...

Page 165: ...20000 19948 0 26 77 TC SB Mono Fs Gershwin Fs Percent Error DACSR ADCSR Table 27 Mono SB TC to Sample Frequency Translation Continued 207 20408 20480 0 35 75 208 20833 20757 0 37 74 209 21276 21333 0...

Page 166: ...2 0 31 151 208 10416 10378 0 36 148 Table 28 Stereo SB TC to Sample Frequency Translation 209 10638 10593 0 42 145 210 10869 11025 1 44 4 211 11111 11025 0 77 4 212 11363 11378 0 13 135 213 11627 1163...

Page 167: ...set the capture sample rate converter is enabled When clear the CSRC is powered down however the output latch is still used if the SRC is assigned a slot number PSRCEN When set the playback sample ra...

Page 168: ...te ADCSR Address BA0 748h Default 00000000h Definition Selects the sample rate for the Capture SRC which contains audio data from the AC Link which is from an ADC Bit Descriptions SRAD 7 0 ADC sample...

Page 169: ...received from ASDIN slots 3 and 4 Slot IDs 10 and 11 resp on the AC Link are transferred by the SSC to the Wavetable interface in the digital mixer It is host software s responsibility to make sure t...

Page 170: ...mute 18 1 6 FM Right Volume Control FMRVC Address BA0 758h Default 00000000h Definition Controls the right channel FM mute and volume that is mixed into the PCM stream after the playback SRC Bit Desc...

Page 171: ...l to mute 18 1 8 PCM Playback Right Volume Control PPRVC Address BA0 764h Default 00000000h Definition Controls the volume for right PCM playback and is primarily used to control Voice PCM and FM volu...

Page 172: ...lot 0 is sent to the AC Link slot See Table 29 CLSS 4 0 Capture Left SRC Slot assignment When this AC Link slot has valid data the data is sent to the left capture SRC first Once through the SRC the d...

Page 173: ...lot 3 and slot 4 data will always be valid The Serial port engine will pass the data to the SSC Most of the time host software won t be recording Therefore slot 3 and 4 data will always be valid but n...

Page 174: ...Host Wavetable Stream Archi tecture The FM Synthesis block generates a stereo 48 kHz audio stream This stream after volume control through FMVC is digitally mixed with PCM data which also has volume...

Page 175: ...C data after sample rate conversion 18 3 Sample Rate Converters Their are two stereo sample rate converters one for playback and one for capture Each is enabled by setting the SSPM PSRCEN bit and SSPM...

Page 176: ...78 2848 8629 2 103 1648 14912 6 252 4032 6095 2 177 2832 8678 0 102 1632 15058 8 251 4016 6119 5 176 2816 8727 3 101 1616 15207 9 250 4000 6144 0 175 2800 8777 1 100 1600 15360 0 249 3984 6168 7 174 2...

Page 177: ...848 28981 1 202 3232 7604 0 127 2032 12094 5 52 832 29538 5 201 3216 7641 8 126 2016 12190 5 51 816 30117 6 200 3200 7680 0 125 2000 12288 0 50 800 30720 0 199 3184 7718 6 124 1984 12387 1 49 784 313...

Page 178: ...d educational software FM mixing will occur in the CS4281 with the data stream going to the DACs in the AC 97 Codec The digital mixer after the playback SRC will combine PCM and FM data after applying...

Page 179: ...y 0 address 0x4 is set to one BUSY The FM Synthesis core requires a wait time between when an address is written to the address register and when data is written to the data register The BUSY bit when...

Page 180: ...Descriptions FMAD 7 0 FM Register Indirect Address 19 1 5 Bank 1 Data Port B1DP Address BA0 73Ch Read Write Default 00000000h Definition Data port for accessing the FM register last addressed by an a...

Page 181: ...Mono Out Volume register at 06h SSCR MVMD 0 The volume up down step size is programmable with the default being 2 counts per step SSCR HVS1 0 Two counts on a standard AC 97 Codec translates to 3 dB s...

Page 182: ...ereby keeping hardware volume changes synchronized with the host soft ware sliders values If the AC Link is down no ABITCLK the hardware volume values are frozen VOLUP VOLDN button changes are ignored...

Page 183: ...op DLL reset default 1 DLL running SWCE Software Clock Enable This bit is the master enable disable for the core clocks Clearing this bit without clearing DLLP allows a reduced power state without the...

Page 184: ...lso resets logic in the serial port engine and allows PME support from the ASDIN ASDIN2 lines See Figure 18 in PCM Assertion section for PME conceptual logic DLLRDY locks goes high to the clock source...

Page 185: ...volume is changed The VO LUP VOLDN pins are powered from the VAUX sup ply thereby supporting the wake up capability PME assertion from the D3cold power off state Conceptual logic for the VOLUP VOLDN p...

Page 186: ...y the polarity bit VUPPO GP1S ASDIN2 GPIO1 input Status Assuming this pin is not configured for ASDIN2 this bit reflects the status of the ASDIN2 GPIO1 pin If ASDIN2 GPIO1 is an output this bit reflec...

Page 187: ...VOLDN pin pullup 1 Disable VOLDN pin pullup VDNPO Volume Down input Polarity 0 active low 1 active high VDNST Volume Down input Sticky 1 VOLDN input pin is latched for edge sensitive inputs and prese...

Page 188: ...inputs GP1W GPIO1 Wake When set GPIO1 can cause a wake up event asserts PME GP1ST must be set sticky for this bit to be effective and the pin must not be configured for ASDIN2 GP3OE Output Enable GPI...

Page 189: ...olume does an update To clear the interrupt VxxS must be written zero for the par ticular pin causing the interrupt If software wants total control over the master vol ume then the update disable bits...

Page 190: ...GP1IM Generate a PME event HISR GP1I Internal ASDIN2 function SPMC ASDI2E OR with other interrupt sources Q Q SET CLR D Vdd Figure 50 ASDIN2 GPIO1 Conceptual Logic Writing 0 to GPPS clears GPPS HIMR...

Page 191: ...VxxS clears 1 0 VxxST VxxST VxxS VxxW HIMR VxxIM Generate a PME event HISR VxxI xx UP or DN VAUX SSCR HVC VxxLT 1 enable 0 disable 20 k 1 0 VxxLT Hardware Volume Control Logic vol_up_change vol_down_c...

Page 192: ...Confidential Draft 3 7 00 CS4281 Programming Manual 192 DS308PRM1 D r a f t...

Page 193: ...the MPU 401 can be coded into the driver to provide full MPU 401 interface to other software applications expecting an MPU 401 interface Therefore in Windows and a DOS box the MPU 401 support can be...

Page 194: ...ter an interrupt can be generated The interrupt conceptual logic is shown in Figure 54 Since the interface is always in UART mode All writes to the Transmit Port MIDWP are placed in the transmit buffe...

Page 195: ...ble receive interrupts reset default 1 Enable MIDI receive interrupts TIE MIDI Transmit Interrupt Enable This bit controls generation of host interrupts by the MIDI output port 0 Disable transmit inte...

Page 196: ...RBE Receive Buffer Empty This bit returns the empty not empty status of the MIDI receive FIFO 0 FIFO not empty 1 FIFO empty reset default TBE This bit is sticky and is set when the TBF flag transitio...

Page 197: ...space will return the last byte written 20 4 6 MIDI Read Port MIDRP Address BA0 49Ch Read Only Default 00000000h Definition MIDI receive FIFO Port Bit Descriptions MRD 7 0 MIDI Read Data This byte is...

Page 198: ...stance and an external capacitor Host software on the personal computer continually reads the timer pulse outputs and determines joystick position depending on the width of the pulses The state of the...

Page 199: ...output value for the BX coordinate input associated with the JBCX pin 0 Charge point reached now discharged reset default 1 Charging in progress comparator trip point not reached yet CBY BY Coordinate...

Page 200: ...e joystick is powered from 5 V 0 0 Slowest speed trip point 3 00 V 1 00 original IBM joystick logic 0 1 Medium slow speed trip point 2 52 V 1 31 original IBM joystick logic 1 0 Medium fast speed trip...

Page 201: ...device is configured by default as follows CS4281 Default Configuration Subsystem ID fields ID and Vendor ID 00000000h Configuration Load Register CFLR 00000000h After a hardware reset if the SPMC EE...

Page 202: ...ange of the data line during the time that the clock line is high is used to indicate start and stop conditions The EEPROM device read access sequence is shown in the figure below The timing follows t...

Page 203: ...EPROM on the EEDAT pin On writes EEN enables the DOUT and CLK bits onto the CS4281 EEDAT and EECLK pins DOUT When DIN EEN 1 the EEDAT pin is driven low when this bit is a zero and when this bit is a o...

Page 204: ...n Location Notes 0 Header Version Constant 55h N A Abort if read byte not 55h 1 Subsystem vendor ID low byte Offsets 2Ch FCh Write FCh visible at 2Ch 2 Subsystem vendor ID high byte Offsets 2Dh FDh Wr...

Page 205: ...state machine waits for the next available frame sets the tag bits in slot 0 for slots 1 and 2 valid copies the address from ACCAD to slot 1 copies the data from ACCDA to slot 2 and then automatically...

Page 206: ...section details which FIFO audio channels are mapped to which AC Link slots Reg Name BA0 Address Description General Configuration registers SSPM 740h AC Link engine enable SERMC 420h Loopbacks Target...

Page 207: ...0B AC 97 primary link input slot 5 12 0C AC 97 primary link input slot 6 13 0D AC 97 primary link input slot 7 14 0E AC 97 primary link input slot 8 15 0F AC 97 primary link input slot 9 16 10 AC 97...

Page 208: ...ext frame comes along ASYNC going high the latched data is transferred to register AODSD1 2 The AODSD1 2 registers contain read only bits NDS 11 3 which when high indicate data should not be sent in t...

Page 209: ...cs containing modem functionality will treat a cold power up as a warm power up to maintain internal registers 22 3 Loopback Modes The CS4281 has numerous loopback modes that support and enhance the l...

Page 210: ...CR LPSRC SERMC SLB SERMC PLB AFE Control 56h LB 101 LB 010 LB 101 LB 010 Figure 60 Bus Centric Loopback Modes ADC DAC D I E J A F B G Codec ADC DAC D I E J A F B G Codec AC Link Engine CSRC PSRC FIFO...

Page 211: ...n ACCTL TC is set and specify the particular secondary codec attached Since these bits support the secondary codecs they should never be 00 LOVF Loopback Output Valid Frame bit This bit is OR d with t...

Page 212: ...circuit This register is unaffected by the PCI RST signal The default value is set by a Vaux POR signal Host software should initialize this register before use Bit Descriptions RSTN Reset NOT This bi...

Page 213: ...ide the Codec enables the particular test of interest ASYNC is controlled by the ASYN bit and ARST by the RSTN bit 0 Normal ASDOUT generation reset default 1 Force ASDOUT valid with no clocking depend...

Page 214: ...is port 0 0 1 AC 97 format 22 4 4 Serial Port Configuration Register 2 SERC2 Address BA0 42Ch Read Only Default 00000003h Definition Lists the configuration of the primary input port for backwards com...

Page 215: ...alid command data slot 1 Write the ACCAD and ACCDA registers 2 Set TC bit if the 2nd codec in a dual CS4298 system is to be addressed otherwise clear it 3 Set this bit DCV 4 The serial port will dynam...

Page 216: ...d until the current set is read 4 Read ACSAD and ACSDA registers upon seeing this bit set 5 Read of the ACSDA register will automatically clear reset this bit 22 5 3 AC 97 Output Slot Valid Register A...

Page 217: ...e next frame frame after these bits were received These bits are copied from ASDIN Slot 1 where NDS11 is bit 3 NDS10 is bit 4 and so on up to NDS3 is bit 11 0 Send data in the next frame if correspond...

Page 218: ...in ACCTL selects the target codec in dual codec configurations Bit Descriptions CI 6 0 Control Register Index This 7 bit field addresses the 64 16 bit registers in the AC 97 control register address s...

Page 219: ...Register ACSAD Address BA0 478h Read Only Default 00000000h Definition The address register field for an AC 97 input frame on the first AC 97 link the ASDIN pin The contents of this register will not...

Page 220: ...ster for AC Link Codec SLT12O Address BA0 41Ch Read Write Default 00000000h Definition The AC Link Slot 12 GPIO outputs bits These bit positions match the slot 12 recommendation in the AC 97 2 1 Audio...

Page 221: ...position in Slot 12 GP_INT GPIO Interrupt Slot 12 bit 0 Indicates that at least one of the Primary codec s GPIO pins has generated an interrupt The rising edge of GP_INT is stored in GPIOR GPPS and c...

Page 222: ...ble through HIMR GPSIM and clearable by writing a zero GPIOR GPSS which clears the CS4281 interrupt The ability to cause a PME event is maskable through SPMC GISPEN and must be cleared by writing a ze...

Page 223: ...al codec system The contents of this register are dynamically updated with each AC 97 input frame Bit Descriptions ISV 12 3 Slot Valid bits These bits sense the slot valid bits in the AC 97 input data...

Page 224: ...ister will not be overwritten by another input frame s valid data unless the valid status bit is cleared in ACSTS2 by a read of this register Side Effect When this register is read the valid status bi...

Page 225: ...Test Mode 4 Input XOR Tree Test A simplified entry procedure is provided The Boundary Test Mode is entered by asserting the TEST pin high with the TESTSEL pin high The part will remain in the Boundar...

Page 226: ...back to the capture SRC input This test mode internally sets the SSCR LPSRC bit All other registers associated with the stream must be setup properly for this test mode to work 7 Primary AC Link Loop...

Page 227: ...with an internal pullup or pulldown will have that pullup or pulldown disconnected so that the real input leakage can be measured 4 Input level XOR tree All pins with an input buffer have their input...

Page 228: ...256 abitclk and clk512 The other joystick button pins are the scan input signals and the other joystick coordinate pins are the scan output signals The PCICLK pin is the scan clock for the pci_clk sca...

Page 229: ...uto initialize PLAY Playback direction CAPT Capture direction DMA DMA mode POLL Polled FIFO mode DRU DMA Request Ungated Gate signal from FIFO to stop start DMA engine FEN FIFO Enable TMR Table Munge...

Page 230: ...hese registers provide a read only port for observing internal state machine operation and critical signal operation Currently undefined unused Bit Descriptions A 31 0 Observation state signals See se...

Page 231: ...d Setting a Special Test Mode in a card that doesn t support that test mdoe could damage the device The TMS register is reset by the PCI RST signal and the Vaux POR signal Bit Descriptions TS 4 0 Test...

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