Crystal CS4281, Programming Manual, Page: 111 / 231

CS4281 Programming Manual
DS308PRM1 111
Confidential Draft 3/7/00
The number of samples currently available in a
FIFO are found in
FSICn.FSC[6:0]
. A FIFO arbiter
controls whether the SSC data or DMAn controller
data (from the Formatter) gets access to the FIFO
RAM.
The FIFOn controllers maintain status for their par-
ticular FIFOs. Three conditions are flagged and can
generate interrupts to the host. The FIFOn control-
ler generates a pulse and sets the FIFO Sample
Count Reached,
FSICn.FSCR
, bit when the
FSICn.FIC
count matches the number of samples
currently available in the FIFO (
FSICn.FSC
bits).
Host software can set the
FSICn.FIC
bits to generate
an interrupt/status on an empty FIFO, half/way
through the FIFO, a full FIFO, or anywhere in-be-
tween. This bits can generate an interrupt if un-
masked and are cleared by reading the
corresponding FSICn register.
If a FIFOn is full and new data is sent to FIFOn, the
FIFOn controller blocks the write forcing the data
in the bit bucket. The FIFOn write pointer is NOT
changed. The FIFO controller then generates an
overrun condition/pulse by setting the
FSICn.FOR
bit. This bit remains set until the host reads FSICn.
A FIFO could be empty under two conditions, if it
was just turned on or if the FIFO is active and data
was read from the FIFO faster than data is written
into the FIFO. If FIFOn is empty and no data was
ever in the FIFO, the FIFOn controller sends a sig-
nal to the data bus buffer forcing zero to be read. If
FIFOn is empty and old data exists in the FIFO, the
FIFOn controller responds based on
FCRn.DACZ
. If
DACZ
(DAC Zero) is set, the FIFOn controller
sends a signal to the data bus buffer forcing zero to
be read. If
DACZ
is clear, the FIFOn controller al-
lows a read to occur from the last location that was
read with valid data. The read pointer is NOT
changed. On reading an empty FIFOn, the FIFOn
controller generates an underrun condition/pulse
by setting the
FSICn.FUR
bit. This bit remains set
until the host reads FSICn.
The FIFO controller maintains read and write
pointers for sample pairs only; however, a
mechanism is provided that allows a single
20-bit signed
0 19 20 39
Left Right
20-bit signed
msb
msb
0
1
2
3
4
127
5
FIFO
Physical Address
fifo_addr[7:0]
Host
Logical Address
BA1+000
BA1+008h
BA1+010h
BA1+018h
BA1+020h
BA1+028h
BA1+3F8h
BA1+004
End of
RAM
BA1+3FCh
Figure 39. FIFO Memory Architecture
D
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