Crystal CS4281, Programming Manual

Page: 47 / 231

CS4281 Programming Manual
DS308PRM1 47
Confidential Draft 3/7/00
5.3 Configuration Space
The following table specifies the primary PCI configuration space for the CS4281.
Byte 3 Byte 2 Byte 1 Byte 0 Offset
Device ID: R/O, 6005h for CS4281
6XXXh range is reserved for Crystal
Vendor ID: R/O, 1013h (Cirrus Logic’s PCI ID) 00h
Status Register, bits 15-0:
Bit 15: Detected Parity Error: Error Bit
Bit 14: Signalled SERR: R/O: 0
Bit 13: Received Master Abort: Error Bit
Bit 12: Received Target Abort: Error Bit
Bit 11: Signalled Target Abort: R/O 0
Bit 10-9: DEVSEL Timing: R/O, 01 (medium)
Bit 8: Data Parity Error Detected: Error Bit
Bit 7: Fast Back to Back Capable: R/O 0
Bit 6: User Definable Features: R/O 0
Bit 5: 66MHz Bus: R/O 0
Bit 4: New Capabilities: R/O 1
Bit 3-0: Reserved: R/O 0000
Reset Status State: 0210h
Write of 1 to any error bit position clears it.
Command Register, bits 15-0:
Bit 15-10: Reserved, R/O 000000
Bit 9: Fast B2B Enable: R/O 0
Bit 8: SERR Enable: R/O 0
Bit 7: Wait Control: R/O 0
Bit 6: Parity Error Response: R/W, default 0
Bit 5: VGA Palette Snoop: R/O 0
Bit 4: MWI Enable: R/O 0
Bit 3: Special Cycles: R/O 0
Bit 2: Bus Master Enable: R/W, default 0
Bit 1: Memory Space Enable: R/W, default 0
Bit 0: I/O Space Enable: R/O 0
04h
Class Code: R/O 040100h
Class 04h (multimedia device), Sub-class 01h (audio), Interface 00h
Revision ID: R/O 01h 08h
BIST: R/O 0
Header Type:
Bit 7: R/O 0
Bit 6-0: R/O 0 (type 0) Latency Timer:
Bit 7-3: R/W,default 0
Bit 2-0: R/O 0
Cache Line Size:
R/O 0
0Ch
Base Address Register 0
Device Control Register space, memory mapped. 4 kByte size
Bit 31-12: R/W, default 0. Compare address for register space accesses
Bit 11 - 4: R/O 0, specifies 4 kByte size
Bit 3: R/O 0, Not Prefetchable (Cacheable)
Bit 2-1: R/O 00, Location Type - Anywhere in 32 bit address space
Bit 0: R/O 0, Memory space indicator
10h
Base Address Register 1
Device Memory Array mapped into host system memory space, 64 kByte size
Bit 31-16: R/W, default 0. Compare address for memory array accesses
Bit 15 - 4: R/O 0, specifies 64 kByte size
Bit 3: R/O 0, Not Prefetchable (Cacheable)
Bit 2-1: R/O 00, Location Type - Anywhere in 32 bit address space
Bit 0: R/O 0, Memory space indicator
14h
Base Address Register 2: R/O 00000000h, Unused 18h
Base Address Register 3: R/O 00000000h, Unused 1Ch
Base Address Register 4: R/O 00000000h, Unused 20h
Base Address Register 5: R/O 00000000h, Unused 24h
Table 3. PCI Configuration Space
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