Crystal CS4281, Programming Manual

Page: 30 / 231

Confidential Draft 3/7/00
CS4281 Programming Manual
30 DS308PRM1
PCI INTERFACE PINS
(T
A
= 0 to 70° C; PCIVDD = CVDD = VAUX = CRYVDD = 3.3 V; VDD5REF =
5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V; Timing reference levels = 1.4 V
Notes: 14. For Active/Float measurements, the Hi-Z or “off” state is when the total current delivered is less than or
equal to the leakage current. Specification is guaranteed by design, not production tested.
15. RST# is asserted and de-asserted asynchronously with respect to PCICLK.
16. All PCI output drivers are asynchronously floated when RST# is active. Note ASDOUT and ASYNC are
not affected by RST#.
Parameter Symbol Min Max Unit
PCICLK cycle time t
cyc
30 - ns
PCICLK high time t
high
11 - ns
PCICLK low time t
low
11 - ns
PCICLK to signal valid delay - bused signals t
val
2 11 ns
PCICLK to signal valid delay - point to point t
val(p+p)
2 12 ns
Float to active delay (Note 14) t
on
2 - ns
Active to Float delay (Note 14) t
off
- 28 ns
Input Set up Time to PCICLK - bused signals t
su
7 - ns
Input Set up Time to PCICLK - point to point t
su(p+p)
10, 12 - ns
Input hold time for PCICLK t
h
0 - ns
Reset active to output float delay (Notes 14, 15, 16) t
rst-off
- 25 ns
RST#
OUTPUTS
Hi-Z
INPUTS
Valid
Input
t
on
t
off
t
su
t
h
OUTPUTS
Valid
t
val
t
rst-off
PCICLK
Figure 12. PCI Timing Measurement Conditions
D
ra
ft