Crystal CS4281, Programming Manual

Page: 58 / 231

Confidential Draft 3/7/00
CS4281 Programming Manual
58 DS308PRM1
• V
AUX
power requirements. BIOS should
set
IISR.VAC[2:0]
to indicate how much
current is pulled from the V
AUX
supply in
D3
cold
. This current number includes any
attached codecs and circuitry and is not
just the CS4281.
• Unknown bit. The
IISR.AUXP
bit is
reflected in the
PMC.AUXP
bit. However,
exact definition of this bit is unknown at
this time.
• When finished writing the vendor defined
config space, set CWPR = 0000h (disable
further writes)
8.2 Sound System Start-Up
Configuration
The following operations should be used in starting
up the Sound System side, after PCI Configuration
start-up. The following data does not address actu-
ally sending data to or from the codec.
• Remove reset from AC Link;
SPMC.RSTN
= 1
• If two codecs present, enable
ASDIN2
and set
secondary codec ID;
SPMC.ASDIN2E
= 1,
SERMC.TCID[1:0]
• Turn on Sound System clocks based on
ABITCLK
; CLKCR1 = 0030h
• Set enables for sections that are needed in the
SSPM register:
• Enable AC Link;
SSPM.ACLEN
= 1
• Enable SRCs if needed;
SSPM.PSRCEN
=
SSPM.CSRCEN
= 1
• Enable FM if needed;
SSPM.FMEN
= 1
• Enable Joystick if needed;
SSPM.JSEN
= 1
• Wait for clock stabilization;
CLKCR1.DLLRDY
=
CLKCR1.CLKON
= 1
• Enable
ASYNC
generation;
ACCTL.ESYN
= 1
• Wait for Codec ready (
ACSTS.CRDY
/
ACSTS2.CRDY2
)
• Enable Valid Frame output (
ACCTL.VFRM
) on
ASDOUT
• Wait until Codec calibration is finished; Codec
register 26h (lower 4 bits)
• Configure/Initialize Codec mixer registers;
both codecs written through ACCAD/ACCDA
+ ACCTL
• Primary Codec registers read from
ACSAD/ACSDA
• Secondary Codec registers read from
ACSAD2/ACSDA2
• Initialize CS4281 volume registers for 0 dB,
unmuted; FMxVC = PPxVC = 0000h
• Initialize any GPIO register use; GPIOR
• Initialize AC-Link features:
• Variable Sample-Rate support;
SERMC.ODSEN1
/
SERMC.ODSEN2
• PME# generation from GP_INT bit
(
SLT12M.GP_INT
/
SLT12M2.GP_INT
);
SPMC.GIPPEN
/
SPMC.GISPEN
• Interrupt generation from GP_INT bit;
HIMR.GPPIM
/
HIMR.GPSIM
(setting bit
disables function)
• Slot 12 Output bits; SLT12O
• Initialize SSCR register features
• Initialize
DACZ
and
PSH
• Enable Hardware Volume Control if
desired;
SSCR.HVC
• Setup which Codec and registers affected
by hardware volume;
MVCS, MVLD, MVAD,
MVMD
• If hardware volume enabled, write the
Codec master volume register to initialize
the CS4281 hardware volume control.
• Maybe, initialize all FIFO sizes and offsets
(must be globally managed).
D
ra
ft