Crystal CS4281, Programming Manual

Page: 223 / 231

CS4281 Programming Manual
DS308PRM1 223
Confidential Draft 3/7/00
VSTS2 Valid Status: This set/reset bit support dynamic status capture from the second AC ‘97 input
data stream, according to the following rules:
1) A valid status data slot (slot 2 tag) in a given input frame will set this bit
2) The status address and data will be stored in the ACSAD2 and ACSDA2 registers
3) Subsequent valid status address and data slots will be ignored until the current set is read
4) Read ACSAD2 and ACSDA2 registers upon seeing this bit set
5) Read of the ACSDA2 register will automatically clear/reset this bit
22.5.15 AC ‘97 Input Slot Valid Register 2 (ACISV2)
Address: BA0: 4F4h, Read-Only
Default: 00000000h
Definition: Status register for the input slot valid signals for the AC ‘97 tag phase (slot 0) on the second AC
‘97 link (the
ASDIN2
pin) in a dual codec system. The contents of this register are dynamically
updated with each AC ‘97 input frame.
Bit Descriptions:
ISV[12:3] Slot Valid bits: These bits sense the slot valid bits in the AC ‘97 input data stream.
0 = Slot not valid
1 = Slot valid
22.5.16 AC ‘97 Status Address Register 2 (ACSAD2)
Address: BA0: 4F8h, Read-Only
Default: 00000000h
Definition: The address register field for an AC 97 input frame on the second AC 97 link (the
ASDIN2
pin) in
a dual codec system. The contents of this register will not be overwritten by another input frame’s
valid address unless the valid status bit is cleared in ACSTS2 by a read of ACSDA2.
Bit Descriptions:
SI[6:0] Status Register Index: This 7 bit field returns the captured status address returned in slot 1 of
the AC 97 input frame.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISV12 ISV11 ISV10 ISV9 ISV8 ISV7 ISV6 ISV5 ISV4 ISV3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SI6 SI5 SI4 SI3 SI2 SI1 SI0
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