Crystal CS4281, Programming Manual

Page: 9 / 231

CS4281 Programming Manual
DS308PRM1 9
Confidential Draft 3/7/00
LIST OF FIGURES
Figure 1. CS4281 Internal Block Diagram .......................................................... 16
Figure 2. Basic Audio Configuration Diagram .................................................... 17
Figure 3. Audio/Modem Codec Host-Modem Block Diagram ............................. 18
Figure 4. Dual-Codec Docking Station Block Diagram ....................................... 18
Figure 5. Dual-Codec 8-Channel Audio Out Diagram ........................................ 19
Figure 6. Playback Data Flow Diagram .............................................................. 20
Figure 7. Capture Data Flow Diagram ................................................................ 21
Figure 8. Single Codec Connection Diagram ..................................................... 22
Figure 9. Dual Codec Connection Diagram ........................................................ 23
Figure 10. 5 V AC Characteristics ...................................................................... 27
Figure 11. 3.3 V AC Characteristics ................................................................... 28
Figure 12. PCI Timing Measurement Conditions ............................................... 30
Figure 13. AC ’97 Configuration Timing Diagram ............................................... 31
Figure 14. EEPROM Timing ............................................................................... 32
Figure 15. PCI Memory Block Diagram .............................................................. 51
Figure 16. 6-Channel Playback Block Diagram .................................................. 60
Figure 17. Typical Power State Diagram ............................................................ 64
Figure 18. PME# Conceptual Logic .................................................................... 73
Figure 19. VAUX Powered Circuitry ................................................................... 74
Figure 20. Interrupt Architecture ......................................................................... 78
Figure 21. DMA Interrupt Conceptual Logic ....................................................... 86
Figure 22. Polled FIFO Interrupt Conceptual Logic ............................................ 87
Figure 23. Formatter Block Diagram .................................................................. 89
Figure 24. 8-bit PCI Data Transfers ................................................................... 90
Figure 25. 16-Bit PCI Data Transfers ................................................................. 90
Figure 26. 20-Bit PCI Playback Data Transfers ................................................. 91
Figure 27. 20-Bit Little-Endian PCI Capture Data Transfers .............................. 91
Figure 28. Formatter Playback Flow .................................................................. 92
Figure 29. Playback Formatter Byte Swizzler .................................................... 93
Figure 30. Playback Formatter Channel Swizzler .............................................. 93
Figure 31. 8-Bit Formats ..................................................................................... 94
Figure 32. 16-Bit Little-Endian Formats .............................................................. 94
Figure 33. 20-Bit Stereo Little-Endian Formats .................................................. 94
Figure 34. 16-Bit Big-Endian Formats ................................................................ 95
Figure 35. 20-Bit Stereo Big-Endian Formats .................................................... 95
Figure 36. 20-Bit Playback Mono Formats ......................................................... 95
Figure 37. FIFO Hardware Physical RAM Size equation ................................ 110
Figure 38. FIFO Hardware Logical RAM Size equation ................................... 110
Figure 39. FIFO Memory Architecture .............................................................. 111
Figure 40. CCLS Mode Register Conceptual Logic ......................................... 127
Figure 41. CCLS Single-Mask Register Conceptual Logic ............................... 127
Figure 42. CCLS All-Mask Register Conceptual Logic ..................................... 128
Figure 43. PC-PCI Serial Engine-Passing Protocol ......................................... 132
Figure 44. PC-PCI CS4281-Supported Serial Engines .................................... 132
Figure 45. PC/PCI Capture Sequence ............................................................. 133
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