Crystal CS4281, Programming Manual

Page: 56 / 231

Confidential Draft 3/7/00
CS4281 Programming Manual
56 DS308PRM1
7.3 Config Space Map
The standard PCI Config space is mapped out in
Table 3 on page 47. The registers below are further
described on their listed pages. The vendor defined
registers located between addresses E4h and FFh
are write protected by the Configuration Write
Protection register (CWPR) located at address
EEh. In this register, the
CWP
bits must equal
4281h for the other vendor-defined registers to be
writable. Any other value will make the registers
between E4h and FFh read-only. The CWPR
register (EEh-FFh) is always read/writable. The
PCI config registers are mapped into the register
space (BA0) between 300h and 3FFh at the same
offset. For all Vaux-powered registers, see the
register description for which bits are affected by
the PCI
RST#
reset signal.
Offset Name Description
Power
From
Size Page
06h PCIST PCI Status Core word 66
34h CAPPTR Capabilities Pointer - RO Core byte 67
40h CAPID Capabilities ID - RO Core byte 67
41h NIP Next Item Pointer - RO Core byte 67
42h PMC Power Management Capabilities - RO Core word 68
44h PMCS Power Management Control/Status Vaux word 69
46h PCI-PCI Bridge Support Extensions - RO Core byte 70
47h Power Data - RO Core byte 70
48h-DFh Reserved Reserved
E0h CWPR Configuration Write Protect Register Vaux dword 49
E4h EPPMC Extended PCI Power Management Control Vaux dword 74
E8h GPIOR GPIO Pin Interface Register Vaux dword 186
ECh SPMC Serial Port Power Management Control (& ASDIN2 enable) Vaux dword 212
F0h CFLR Configuration Load Register (EEPROM or BIOS) Vaux dword 62
F4h IISR ISA Interrupt Select Register (plus BIOS flags) Vaux dword 84
F8h TMS Test Register - Reserved
FCh SSVID Subsystem ID register Vaux dword 50
Table 6. Config Space Map
D
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ft