Crystal CS4281, Programming Manual

Page: 173 / 231

CS4281 Programming Manual
DS308PRM1 173
Confidential Draft 3/7/00
18.2 Sound System Functional Description
The Sound System Controller (SSC) moves data
from the AC Link to and from the FIFO’s and
SRCs. Figure 47 illustrates the flow of data be-
tween the AC-Link engine and the FIFO memory.
The Sound System Controller gets requests from
the AC-Link engine when it needs data. For play-
back, the AC-Link engine requests data
(
ac97_dacmux[3:0]
) one slot prior to sending the slot
on the AC Link. The AC-Link engine will only ask
for
ASDOUT
slots that have their Output Slot Valid
bits set (ACOSV). For record, the AC-Link engine
will request data be transferred (
ac97_adcen[3:0]
) for
incoming slots that have their Input Slot Valid bits
set (ACISV for
ASDIN
and ACISV2 for
ASDIN2
).
When the AC-Link engine has data, the SSC moves
the data (one channel at a time) into the FIFO. For
FIFOs that have one channel inactive (slot ID 31),
the SSC sends both valid channel signals to the
FIFO to make the write pointer increment. The
same is true when reading from a FIFO with one
channel inactive.
If the AC-Link engine gives the SSC AC-Link slots
that don’t have an attached FIFO, the data is dis-
carded. A typical example is when the CS4281 is
attached to a CS4297. Unless the ADCs are pow-
ered down, the slot 3 and slot 4 data will always be
valid. The Serial port engine will pass the data to
the SSC. Most of the time host software won’t be
recording. Therefore, slot 3 and 4 data will always
be valid, but no FIFO will be programmed for
AS-
DIN
slots 3 and 4 (Slot IDs 10, 11). The SSC takes
the data from the AC link and discard it.
If the AC Link has output slot valid bits set
(ACOSV), and no FIFO is attached to those slots,
the SSC sends 0’s when the AC-Link engine re-
quests data for those slots.
When the Sample Rate Converters are enabled, the
sample frequency clocks provide the “requests for
data movement” to the SSC. The PSRC, enabled by
setting
SSPM.PSRCEN
, uses the DACSR register for
the playback sample frequency. The CSRC, en-
CLSS[4:0]/
CRSS[4:0]*
AC ‘97
Input Slot
AC ‘97
Codec
AC ‘97 Slot Function
10 3 Primary Left PCM Record
11 4 Primary Right PCM Record
12 5 Primary Phone Line 1 ADC
13 6 Primary Mic ADC
14 7 Primary reserved
15 8 Primary reserved
16 9 Primary reserved
17 10 Primary Phone Line 2 ADC
18 11 Primary HeadSet ADC
20 3 Secondary Left PCM Record
21 4 Secondary Right PCM Record
22 5 Secondary Phone Line 1 ADC
23 6 Secondary Mic ADC
24 7 Secondary reserved
25 8 Secondary reserved
26 9 Secondary reserved
27 10 Secondary Phone Line 2 ADC
28 11 Secondary HeadSet ADC
31 Not used SRC channel is not used - power down
26. * Left and Right channels cannot be split across different FIFOs. Only one FIFOn can be
attached to CSRC.
Table 30. Record SRC Slot Assignments
D
ra
ft