Crystal CS4281, Programming Manual

Page: 69 / 231

CS4281 Programming Manual
DS308PRM1 69
Confidential Draft 3/7/00
The next register, at configuration space offset 0x44, controls the CS4281’s power management state and
indicates its current state.
Power Management Control/Status (PMCS)
Address: PCI CFG: 44h, Read-Write
BA0: 344h, Read-Write
Default: 0000h
Definition: Vaux powered. This register controls the power management device state and indicates the
current state. The
PS
bits are reset by the PCI VDD POR circuit. All other bits are reset by Vaux
POR.
Bit Descriptions:
PS[1:0] Power State: When written, indicates the power state the CS4281 should enter. When read,
indicates the CS4281’s current power state. Note D3
cold
is not listed since this register is not
readable in a D3
cold
state. These bits are reset by the PCI VDD POR signal - NOT Vaux POR.
0 0 = D0 (reset default)
0 1 = D1
1 0 = D2
1 1 = D3
hot
R[5:0] Reserved. Writes are ignored and reads return zeros.
PMEEN PME# Assertion Enable: When written, enables or disables the capability to assert
PME#
.
When read, indicates the current
PME#
assertion capability. When
IISR.VAUXS
= 1
,
the
PMEEN
bit is unaffected by the PCI
RST#
signal. When
IISR.VAUXS
= 0
,
the
PMEEN
bit is
reset by the PCI
RST#
signal. The default value is set by a Vaux POR signal.
0 =
PME#
assertion disabled (POR default)
1 =
PME#
assertion enabled
DSL[3:0] Data Select: Not supported on the CS4281. Writes are ignored and reads return 0.
DSC[1:0] Data Scale: Not supported on the CS4281. Writes are ignored and reads return 0.
PMES PME# Status: Indicates whether or not the CS4281 would be asserting
PME#
, regardless of the
state of the
PMEEN
bit (if a condition occurs where the CS4281 should assert
PME#
, the
PMES
bit is set but actual assertion of the
PME#
signal is gated by the
PMEEN
bit). Writing a
1 to this bit clears it. When
IISR.VAUXS
= 1
, PMES
is unaffected by the PCI
RST#
signal.
When
IISR.VAUXS
= 0
, PMES
is reset by the PCI
RST#
signal. The default value is set by a
Vaux POR signal.
0 =
PME#
not asserted (POR default)
1 =
PME#
asserted
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PMES DSC1 DSC0 DSL3 DSL2 DSL1 DSL0 PMEEN R5 R4 R3 R2 R1 R0 PS1 PS0
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