Crystal CS4281, Programming Manual

Page: 121 / 231

CS4281 Programming Manual
DS308PRM1 121
Confidential Draft 3/7/00
13.3.5 I/O Trap - PCPCI (IOTPCP)
Address: BA0: 52Ch, Read-Write
Default: 00000000h
Definition: I/O Trapping register for the PC/PCI mechanism. The addresses needed are 0 and 4, where 0
transfers data in and out, and 4 also transfers data - but also indicating terminal count. Although
double words are supported, this interface only uses 0/4 since Sound Blaster only supports byte
samples. The I/O access is only trapped if PCGNT# is low. For capture, the I/O Trap logic
redirects host PC/PCI agent reads (from 0/4) to the Legacy DMA controller. For playback, the I/O
Trap logic redirects host PC/PCI agent writes (to 0/4) to the Legacy DMA controller.
Bit Descriptions:
SA[15:0] PC/PCI Start Address: Starting PCI I/O space address of the trap range. Set to 0. Bits above the
I/O Decode Control bits must be set to 0. For example, if
IODC[1:0]
= 10,
SA15-SA10
must be
0.
MSK[2:0] Address Mask: Logically, these bits are used to selectively mask off the lower four bits of
address accompanying an I/O transaction. After the mask operation is performed, the resulting
address is compared against
SA[15:0]
; if they are equal, the original I/O transaction lies within
the trap range. Set to 4 for PC/PCI.
IODC[1:0] I/O Decode Control: These two bits control how many I/O address bits are decoded for the
trap range.
0 0 = Decode
SA15
down to
MSK
bits of I/O address (no aliasing, reset default)
0 1 = Decode
SA11
down to
MSK
bits of I/O address (
SA15-SA12
alias)
1 0 = Decode
SA9
down to
MSK
bits of I/O address (
SA15-SA10
alias)
1 1 = Reserved
WE Write Enable: This bit controls whether or not write trapping is enabled for the trap range.
0 = Write trapping disabled (reset default)
1 = Write trapping enabled
RE Read Enable: This bit controls whether or not read trapping is enabled for the trap range.
0 = Read trapping disabled (reset default)
1 = Read trapping enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RE WE res res res IODC1 IODC0 res MSK2 MSK1 MSK0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
D
ra
ft