Crystal CS4281, Programming Manual

Page: 104 / 231

Confidential Draft 3/7/00
CS4281 Programming Manual
104 DS308PRM1
11.5.7 Host DMA Status Register n (HDSRn)
Address: BA0: 0F0h, Read-Write, for DMA Engine 0
BA0: 0F4h, Read-Write, for DMA Engine 1
BA0: 0F8h, Read-Write, for DMA Engine 2
BA0: 0FCh, Read-Write, for DMA Engine 3
Default: 00000000h
Definition: Holds the status bits for DMA engine n. The
TC[a:d]
,
DTC
, and
DHTC
bits are cleared when this
register is read. Interrupts are enabled in the DCRn register. For DMA mode (
DMRn.DMA
= 1),
the available status/interrupts are
DTC
and
DHTC
. The
DTC
bit is a repeat of the respective
TC[d:a]
bits, but cleared independently. For host operation, the upper word of this register should
be used for clearing DMA related interrupts. For DMA interrupt logic diagram, see Figure 21.
DHTC
and
DTC
are forced clear if
DMRn.DMA
= 0. .
Bit Descriptions:
CH1P Channel 1 Pending. This bit is set when DMAn is requesting the first channel data, mono data,
or when stereo samples are transferred as an atomic unit. This bit is active in DMA or POLL
modes (DMRn).
CH1P
is generally the left channel, but is the right channel when
DMRn.SWAPC
is set.
CH2P Channel 2 Pending. This bit is set when DMAn is requesting the second channel data. This bit
is always clear when sending mono data or when stereo samples are transferred as an atomic
unit. This bit is active in DMA or POLL modes (DMRn).
CH1P
is generally the right channel,
but is the left channel when
DMRn.SWAPC
is set.
DHTC DMA Half Terminal Count. When set, indicates this DMA engine is half way through the
buffer. This bit is cleared by reading this byte. Forced clear when this engine not in DMA
mode
(DMRn.DMA
= 0). This interrupt is enabled by
DCRn.HTCIE
.
DTC DMA Terminal Count. When set, indicates this DMA engine is passed the end of the buffer
(rolled under).
DTC
is forced clear when this engine not in DMA mode (
DMRn.DMA
= 0).
This interrupt is enabled by
DCRn.TCIE
.
DRUN DMA Running. When the DMA engine starts a transaction, this bit is set. When the DMA
engine completes the transaction, this bit is clear. If
DRUN
and
RQ
bits are both clear, the
DMA engine is idle. When
DRUN
is set, the DMA arbiter will not change to the next DMA
engine until
DRUN
is clear.
RQ Set when the DMAn controller has a request pending (is requesting service).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1P CH2P DHTC DTC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRUN RQ
D
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