Crystal CS4281, Programming Manual

Page: 40 / 231

Confidential Draft 3/7/00
CS4281 Programming Manual
40 DS308PRM1
BONDID[1:0]
Bond Pad ID 1, 0
Inputs
These two pads are bonded to the PCI power or ground and do not appear on external pins. Their
logical state is reflected in the
FRR.ID[1:0]
bits and can be used for Marketing part differentiation if
needed. The default value is both pads grounded. These bits affect no internal hardware except the
register value.
4.3.3 External Interface Pins
TEST
Test Mode Strobe
Input with Pulldown, Edge triggered
This pin is used for test mode entry. A low-to-high transition enters test mode and activates the
selected test capability. The part remains in the test mode until the
TEST
pin goes low. This pin has an
internal pulldown to ground, and may remain floating. When the
TESTSEL
pin is high, the XOR-tree
test mode is entered. If
TESTSEL
is low, then the
MIDIIN
and four joystick button pins determine the
test mode. This pin has super-hysteresis input buffer.
TESTSEL
Test Mode Select
Input with Pullup
This pin selects the active test mode while the
TEST
pin is active high.
TESTSEL
is sampled on the
rising edge of
TEST
to determine the basic test mode functionality.
TESTSEL
low activates normal
factory test functions.
TESTSEL
high activates the I/O pin boundary XOR tree test mode.
EEDAT/GPIO2/PCGNT#
External EEPROM Data/PC/PCI Grant
Input/Output, Open Drain Serial I/O
For expansion card designs, a data line for external serial EEPROM containing device configuration
data. For motherboard designs using PC/PCI, the PC/PCI serialized grant input signal. This pin can
also be a general purpose I/O pin.
EECLK/GPOUT/PCREQ#
External EEPROM Clock/PC/PCI Request
Output, Serial Output
For expansion card designs, clock for external serial EEPROM containing configuration data. For
motherboard designs using PC/PCI, the PC/PCI serialized request signal or general purpose output.
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