Crystal CS4281, Programming Manual

Page: 221 / 231

CS4281 Programming Manual
DS308PRM1 221
Confidential Draft 3/7/00
22.5.12 Slot 12 Monitor Register for Primary Codec (SLT12M)
Address: BA0: 45Ch, Read-Only
Default: 00000000h
Definition: Monitor port for the Primary AC Link (
ASDIN
), Slot 12 data. These bit positions match the slot
12 recommendation in the AC ‘97 2.1 Audio Codec spec.
ASDIN
slot 12, bits 19 through 0, are
stored in this register in the same bit position (slot 12 has 19 bits and this register uses 19 bits).
For slot 12 on
ASDIN
to be stored in this register, the slot 12 tag bit from the codec must have
been set,
ACISV.ISV12
.
Bit Descriptions:
AGPI[15:0] AC Link GPIO bits. Bits from slot 12 of the Primary AC link (
ASDIN
).
VSPI[2:0] Vendor Specific Input bits. From same position in Slot 12.
GP_INT GPIO Interrupt - Slot 12, bit 0. Indicates that at least one of the Primary codec’s GPIO pins has
generated an interrupt. The rising edge of
GP_INT
is stored in
GPIOR.GPPS
and can generate a
host interrupt or PME event. The interrupt is maskable through
HIMR.GPPIM
and clearable by
writing a zero
GPIOR.GPPS
which clears the CS4281 interrupt. The ability to cause a
PME#
event is maskable through
SPMC.GIPPEN
and must be cleared by writing a zero to
GPIOR.GPPS
.
GP_INT
is cleared by writing to the Primary Codec’s GPIO Sticky register (Index
50h), and clearing the bit causing the interrupt. See Figure 52 in the General Purpose
Input/Output Pins section for conceptual logic.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AGPI15 AGPI14 AGPI13 AGPI12
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AGPI11 AGPI10 AGPI9 AGPI8 AGPI7 AGPI6 AGPI5 AGPI4 AGPI3 AGPI2 AGPI1 AGPI0 VSPI2 VSPI1 VSPI0 GP_INT
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