Crystal CS4281, Programming Manual

Page: 108 / 231

Confidential Draft 3/7/00
CS4281 Programming Manual
108 DS308PRM1
11.5.11 FIFO Channel Status (FCHS)
Address: BA0: 20Ch, Read-Only
Default: 18181818h
Definition: Core powered. These bits are generally used for debug only. Each FIFOn has 6 bits that indicate
when only one channel of the FIFO is read or written and overrun/underrun internal status. When
both channels are read or written, the read/write pointer is incremented and the associated channel
status bits are cleared. When
FCRn.FEN
clear, all bits associated with that FIFOn are forced clear,
except the
FE/FF
bits which are set when the frame-clock synchronized
FEN
is cleared. When
FEN
is set,
FF
going clear indicates that the internal frame-clock synchronized
FEN
is set. Writing
to or reading from the FIFO in polled mode should not occur until
FF
is read clear.
Bit Descriptions:
LCI[3:0] Left Channel In. When set, indicates that - only - the left channel has been written at the
current FIFO write pointer location. The write pointer will not be moved until the other
channel is received.
RCI[3:0] Right Channel In. When set, indicates that - only - the right channel has been written at the
current FIFO write pointer location. The write pointer will not be incremented until the other
channel is received.
IOR[3:0] Internal Overrun Flag. Set when one channel written to a full FIFO. Used in synchronizing
channel-to-channel overrun conditions.
FF[3:0] FIFO Full. Set when FIFO full. Both
FF
and
FE
will be set when
FEN
for a particular FIFO is
clear.
FE[3:0] FIFO Empty. Set when FIFO empty. Both
FF
and
FE
will be set when
FEN
for a particular
FIFO is clear.
LCO[3:0] Left Channel Out. When set, indicates that - only - the left channel at the current FIFO read
pointer location has been read. The read pointer will not be incremented until the other channel
is read.
RCO[3:0] Right Channel Out. When set, indicates that - only - the right channel at the current FIFO read
pointer location has been read. The read pointer will not be incremented until the other channel
is read.
MRP[3:0] Move Read Pointer. Set when FIFO empty and read pointer needs to move the next time the
write pointer moves. Supports previous sample data out (
DACZ
) when the FIFO is empty.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RCO3 LC03 MRP3 FE3 FF3 IOR3 RCI3 LCI3 RCO2 LCO2 MRP2 FE2 FF2 IOR2 RCI2 LCI2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCO1 LCO1 MRP1 FE1 FF1 IOR1 RCI1 LCI1 RCO0 LCO0 MRP0 FE0 FF0 IOR0 RCI0 LCI0
D
ra
ft