UG-498
ADuCM320 Hardware Reference Manual
Rev. C | Page 154 of 196
GENERAL-PURPOSE TIMERS
GENERAL-PURPOSE TIMERS FEATURES
Three identical general-purpose, 16-bit count-up/count-down timers
o
Timer 0, Timer 1, and Timer 2
Clocked from five different clock sources
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Peripheral clock (PCLK)
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80 MHz system clock (HCLK)
o
32 kHz internal oscillator (LFOSC)
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16 MHz external crystal (HFXTAL) or internal 16 MHz oscillator (HFOSC), depending on the value in CLKCON0[11].
Clock sources can be scaled down using a prescaler 16, 256, or 32768. Additionally, two of the clocks can be scaled down using a
prescaler of 4, and the other two clock sources can be used directly (prescaler of 1).
Two modes
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Free running
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Periodic
Capture events feature
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Capability to capture 15 different events on each timer
GENERAL-PURPOSE TIMERS BLOCK DIAGRAM
11
176
-029
16-BIT UP/DOWN COUNTER
PRESCALER
1, 4, 16, 256,
OR 32768
TIMER VALUE
CAPTURE
16-BIT LOAD
EVENT SELECT
PCLK
CLOCK SOURCES
HCLK
LFOSC
HFXTAL/HFOSC
TIMER INTERRUPT
NOTES
1. 16MHz EXTERNAL CRYSTAL (HFXTAL) OR INTERNAL 16MHz OSCILLATOR (HFOSC),
DEPENDING ON THE VALUE IN CLKCON0[11].
Figure 28. General-Purpose Timers Block Diagram
GENERAL-PURPOSE TIMERS OVERVIEW
Timer 0, Timer 1, and Timer 2 are three identical general-purpose, 16-bit count-up/count-down timers. They can be clocked from five
different clock sources:
PCLK
HCLK
32 kHz internal oscillator (LFOSC)
16 MHz external crystal (HFXTAL) or internal 16 MHz oscillator (HFOSC), depending on the value in CLKCON0[11].
The clock sources can be scaled down using a prescaler of 1, 4, 16, 256, or 32768.
The timers can be either free running or periodic.
In free running mode, the counter decrements from full scale to zero scale or increments from zero scale to full scale and then restarts.
In periodic mode, the counter decrements or increments from the value in the load register (TxLD MMR, where x is 0 for Timer 0, 1
for Timer 1, and 2 for Timer 2) until zero scale or full scale is reached and then restarts at the value stored in the load register.
The value of a counter can be read at any time by accessing its value register (TxVAL).
The TxCON register selects the timer mode, configures the clock source, selects count-up/count-down, starts the counter, and controls
the event capture function.
An interrupt signal is generated each time the value of the counter reaches 0 when counting down, or each time the counter value reaches
the maximum value when counting up. An IRQ can be cleared by writing 1 to the time clear interrupt register of that particular timer (TxCLRI).
In addition, Timer 0, Timer 1, and Timer 2 have a capture register (TxCAP) that is triggered by a selected IRQ source initial assertion.
When triggered, the current timer value is copied to TxCAP, and the timer continues to run. This feature can be used to determine the
assertion of an event with increased accuracy.
