Analog Devices ADuCM320, Hardware Reference Manual

Page: 141 / 196

ADuCM320 Hardware Reference Manual UG-498
Rev. C | Page 141 of 196
REGISTER SUMMARY: UART
Table 194. UART Register Summary
Address Name Description Reset RW
0x40005000 COMTX Transmit holding register 0x0000 W
0x40005000 COMRX Receive buffer register 0x0000 R
0x40005004 COMIEN Interrupt enable register 0x0000 RW
0x40005008 COMIIR Interrupt identification register 0x0001 RC
0x4000500C COMLCR Line control register 0x0000 RW
0x40005010 COMMCR Modem control register 0x0000 RW
0x40005014 COMLSR Line status register 0x0060 RC
0x40005018 COMMSR Modem status register 0x0000 RC
0x4000501C COMSCR Scratch buffer register 0x0000 RW
0x40005024 COMFBR Fractional baud rate register 0x0000 RW
0x40005028 COMDIV Baud rate divider register 0x0001 RW
REGISTER DETAILS: UART
Transmit Holding Register
Address: 0x40005000, Reset: 0x0000, Name: COMTX
COMRX and COMTX share the same address while they are implemented as different registers. If these registers are written to, the user
accesses the transmit holding register (COMTX). If these registers are read from, the user accesses the receive buffer register (COMRX).
Table 195. Bit Descriptions for COMTX
Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved. 0x0 R
[7:0] THR Transmit holding register. This is an 8-bit register to which the user can
write the data to be sent. If the ETBEI bit is set in the COMIEN register, an
interrupt is generated when COMTX is empty. If user code sets ETBEI while
COMTX is already empty, an interrupt is generated immediately.
0x0 W
Receive Buffer Register
Address: 0x40005000, Reset: 0x0000, Name: COMRX
Table 196. Bit Descriptions for COMRX
Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved. 0x0 R
[7:0] RBR Receive buffer register. This is an 8-bit register from which the user can
read received data. If the ERBFI bit is set in the COMIEN register, an
interrupt is generated when this register is fully loaded with the received
data via serial input port. If user code sets the ERBFI bit while COMRX is
already full, an interrupt is generated immediately.
0x0 R
Interrupt Enable Register
Address: 0x40005004, Reset: 0x0000, Name: COMIEN
COMIEN is the interrupt enable register that is used to configure which interrupt source generates the interrupt. Only the lowest four bits
in this register enable interrupts. Bit 4 and Bit 5 enable UART DMA signals. The UART DMA channel and interrupt must be configured
in the DMA block.
Table 197. Bit Descriptions for COMIEN
Bits Bit Name Description Reset Access
[15:6] RESERVED Reserved. 0x0 R
5 EDMAR DMA requests in receive mode. 0x0 RW
0: DMA requests disabled
1: DMA requests enabled