UG-498
ADuCM320 Hardware Reference Manual
Rev. C | Page 16 of 196
POWER MANAGEMENT UNIT
POWER MANAGEMENT UNIT FEATURES
The power management unit (PMU) controls the different power modes of the
Four power modes are available:
•
Active
•
CORE_SLEEP
•
SYS_SLEEP
•
Hibernate
POWER MANAGEMENT UNIT OVERVIEW
The Cortex-M3 sleep modes are linked to the PMU modes and are described in this section. The PMU is in the always-on section. Each
mode gives a power reduction benefit with a corresponding reduction in functionality.
POWER MANAGEMENT UNIT OPERATION
The debug tools can prevent the Cortex-M3 from fully entering its power saving modes by setting bits in the debug logic. Only a power-on reset
resets the debug logic. Therefore, the device should be power cycled after using serial wire debug with application code containing the
WFI instruction.
Power Mode: Active Mode, Mode 0
The system is fully active. Memories and all user enabled peripherals are clocked, and the Cortex-M3 processor is executing instructions.
Note that the Cortex-M3 processor manages its internal clocks and can be in a partial clock gated state. This clock gating affects only the
internal Cortex-M3 processing core. Automatic clock gating is used on all blocks and is transparent to the user. User code can use a WFI
command to put the Cortex-M3 processor into sleep mode; it is independent of the power mode settings of the PMU.
When the
wakes up from any of the low power modes, the device return to Mode 0.
Power Mode: CORE_SLEEP Mode, Mode 1
In CORE_SLEEP mode, the system gates the clock to the Cortex-M3 core after the Cortex-M3 has entered SLEEP mode. The rest of the
system remains active. No instructions can be executed; however, DMA transfers can continue to occur between peripherals and
memories. The Cortex-M3 processor FCLK is active, and the device wakes up using the NVIC.
Power Mode: SYS_SLEEP Mode, Mode 2
In SYS_SLEEP mode, the system gates HCLK (system bus clock) and PCLK (peripheral bus clock) after the Cortex-M3 has entered sleep
mode. The gating of these clocks stops all AHB attached masters/slaves and all peripherals attached to APB. Peripheral clocks are all off,
and they are no longer user programmable. The NVIC (interrupt controller) clock (FCLK) remains active, and the NVIC processes wake-
up events.
Power Mode: Hibernate Mode, Mode 3
In hibernate mode, the system disables power to all combinational logic and places sequential logic in retain mode. Because FCLK is
stopped, the number of sources capable of waking up the system is restricted. The sources listed in Table 55 are the only sources able to
wake up the system.
Power Mode 1 to Power Mode 3 should be entered when the processor is not in an interrupt handler. If Power Mode 1 to Power Mode 3 is
entered when the processor is in an interrupt handler, the power-down mode can be exited only by a reset or a higher priority interrupt source.
