ADuCM320 Hardware Reference Manual
UG-498
Rev. C | Page 65 of 196
Autorequest (CHNL_CFG[2:0] = 010)
When the controller operates in this mode, it is only necessary for the controller to receive a single request to enable it to complete the
entire DMA cycle. This allows a large data transfer to occur without significantly increasing the latency for servicing higher priority
requests or requiring multiple requests from the processor or peripheral. This mode is very useful for a memory-to-memory copy application.
Autorequest is not suitable for peripheral use, except for the ADC sequencer mode, where a number of peripheral operations need to be
completed.
In this mode, the controller can be configured to use either the primary or alternate data structure. After the channel is enabled, when the
controller receives a request, it performs the following operations:
1.
The controller performs min(2
R_POWER
, N) transfers for the channel, where R_POWER is Bits[17:14] of the control data configuration register
and N is the number of transfers. If the number of transfers remaining is zero, the flow continues at Step 3.
2.
A request for the channel is automatically generated. The controller arbitrates. If the channel has the highest priority, the DMA cycle
continues at Step 1.
3.
At the end of the transfer, the controller generates an interrupt for the corresponding DMA channel.
Ping-Pong (CHNL_CFG[2:0] = 011)
In ping-pong mode, the controller performs a DMA cycle using one of the data structures and then performs a DMA cycle using the
other data structure. The controller continues to alternate between using the primary and alternate data structures until it either reads a
data structure that is invalid or the host processor disables the channel.
This mode is useful for transferring data from peripheral to memory using different buffers in the memory. In a typical application, the
host must configure both primary and alternate data structures before starting the transfer. As the transfer progresses, the host can
subsequently configure primary or alternate control data structures in the interrupt service routine when the corresponding transfer ends.
The DMA controller interrupts the processor after the completion of transfers associated with each control data structure. The individual
transfers using either the primary or alternate control data structure work exactly the same as a basic DMA transfer.
Memory Scatter-Gather (CHNL_CFG[2:0] = 100 or 101)
In memory scatter-gather mode, the controller must be configured to use both the primary and alternate data structures. The controller
uses the primary data structure to program the control configuration for the alternate data structure. The alternate data structure is used
for actual data transfers, which are similar to an autorequest DMA transfer. The controller arbitrates after every primary transfer. The
controller needs only one request to complete the entire transfer. This mode is used when performing multiple memory-to-memory copy
tasks. The processor can configure all of the tasks simultaneously and does not need to intervene in between each task. The controller
generates the corresponding DMA channel interrupt in the NVIC when the entire scatter-gather transaction completes using a basic cycle.
In this mode, the controller receives an initial request and then performs four DMA transfers using the primary data structure to program
the control structure of the alternate data structure. After this transfer completes, the controller starts a DMA cycle using the alternate
data structure. After the cycle completes, the controller performs another four DMA transfers using the primary data structure. The
controller continues to alternate between using the primary and alternate data structures until either the processor configures the
alternate data structure for a basic cycle or the DMA reads an invalid data structure.
Table 75 lists the fields of the CHNL_CFG memory location for the primary data structure, which must be programmed with constant
values for the memory scatter-gather mode.
Table 75. CHNL_CFG for Primary Data Structure in Memory Scatter-Gather Mode, CHNL_CFG[2:0] = 100
Bits Name
Description
[31:30]
DST_INC
10: configures the controller to use word increments for the address.
[29:28]
DST_SIZE
10: configures the controller to use word transfers.
[27:26]
SRC_INC
10: configures the controller to use word increments for the address.
[25:24]
SRC_SIZE
10: configures the controller to use word transfers.
[23:18]
RESERVED
Undefined. Write as 0.
[17:14]
R_POWER
0010: indicates that the DMA controller is to perform four transfers.
[13: 4]
N_MINUS_1
Configures the controller to perform N DMA transfers, where N is a multiple of 4.
3
RESERVED
Undefined. Write as 0.
[2:0]
CYCLE_CTRL
100: configures the controller to perform a memory scatter-gather DMA cycle.
