Analog Devices ADuCM320 Hardware Reference Manual Download Page 145 | Manualshive

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ADuCM320 Hardware Reference Manual

UG-498

Rev. C | Page 145 of 196

Bits

Bit Name

Description

Reset

Access

3

DDCD

Delta DCD. If set, this bit self clears after COMMSR is read.

0x0

R

0: DCD has not changed state since COMMSR was last read

1: DCD changed state since COMMSR last read

2

TERI

Trailing edge RI. If set, this bit self clears after COMMSR is read.

0x0

R

0: RI has not changed from 0 to 1 since COMMSR last read

1: RI changed from 0 to 1 since COMMSR last read

1

DDSR

Delta DSR. If set, this bit self clears after COMMSR is read.

0x0

R

0: DSR has not changed state since COMMSR was last read

1: DSR changed state since COMMSR last read

0

DCTS

Delta CTS. If set, this bit self clears after COMMSR is read.

0x0

R

0: CTS has not changed state since COMMSR was last read

1: CTS changed state since COMMSR last read

Scratch Buffer Register

Address: 0x4000501C, Reset: 0x0000, Name: COMSCR

Table 203. Bit Descriptions for COMSCR

Bits

Bit Name

Description

Reset

Access

[15:8]

RESERVED

Reserved.

0x0

R

[7:0]

SCR

Scratch. The scratch register is an 8-bit register used to store intermediate

results. The value contained in the scratch register does not affect UART
functionality or performance. Only 8 bits of this register are implemented.
Bit 15 to Bit 8 are read only and always return 0x00 when read. Writable
with any value from 0 to 255. A read returns the last value written.

0x0

RW

Fractional Baud Rate Register

Address: 0x40005024, Reset: 0x0000, Name: COMFBR

Table 204. Bit Descriptions for COMFBR

Bits

Bit Name

Description

Reset

Access

15

FBEN

Fractional baud rate generator enable. The generating of fractional baud

rate can be described by the following formula, and the final baud rate of
UART operation is calculated as Baud rate = ((UCLK/CDPCLK)/(2 × (M +
N/2048)) 16 × COMDIV.

0x0

RW

[14:13]

RESERVED

Reserved.

0x0

R

[12:11]

DIVM

Fractional baud rate M divide bits 1 to 3. This bit should not be 0.

0x0

RW

[10:0]

DIVN

Fractional baud rate N divide bits 0 to 2047.

0x0

RW

Baud Rate Divider Register

Address: 0x40005028, Reset: 0x0001, Name: COMDIV

Table 205. Bit Descriptions for COMDIV

Bits

Bit Name

Description

Reset

Access

[15:0]

DIV

Baud rate divider. The COMDIV register should not be 0, which is not
specified. The range of allowed DIV values is from 1 to 65535.

0x1

RW

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Summary of Contents for ADuCM320

Page 1: ...esult from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trade...

Page 2: ...gram 21 ADC Circuit Overview 22 ADC Circuit Operation 22 ADC Transfer Function 23 ADC Typical Setup Sequence 24 ADC Input Buffer 24 ADC Internal Channels 24 ADC Support Circuits 25 Register Summary AD...

Page 3: ...gister Details I2C1 114 Serial Peripheral Interfaces 123 SPI Features 123 SPI Overview 123 SPI Operation 123 SPI Transfer Initiation 124 SPI Interrupts 126 SPI Wire OR ed Mode WOM 127 SPI CSERR Condit...

Page 4: ...h 1 ECC Error Address Register Section and Table 112 to Table 114 Renumbered Sequentially 86 Added MDIO Interrupt Power Up Register Write Sequence Section 184 1 2015 Rev 0 to Rev A Changes to Figure 1...

Page 5: ...on GPIO Port 5 Pull Down Enable Register Section GPIO Port 5 Input Path Enable Register Section d3fGPIO Port 5 Registered Data Input Section and Table 136 to Table 140 96 Deleted GPIO Port 5 Data Outp...

Page 6: ...s write access only MMR bits that are not documented are reserved When writing to MMRs with reserved bits the reserved bits should be written with the value in the reset column of the relevant MMR des...

Page 7: ...vice includes an MDIO interface capable of operating at up to 4 MHz The capability to simultaneously execute from one flash block and write erase the other flash block makes the ADuCM320 ideal for 40...

Page 8: ...timer Watchdog timer 32 element programmable logic array PLA Packages and Temperature Range 6 mm 6 mm 96 ball BGA package 40 C to 85 C Tools Low cost development system Third party compiler and emulat...

Page 9: ...CE 1GB NOT AVAILABLE IN ADuCM320 EXTERNAL RAM 1GB NOT AVAILABLE IN ADuCM320 0xDFFF FFFF 0xA000 0000 0x9FFF FFFF 0x6000 0000 PERIPHERAL 0 5GB 0x5FFF FFFF 0x400A FFFF ADuCM320 MMRs 0x4000 0000 0x4000 00...

Page 10: ...ip oscillators and circuitry for an external crystal and external clock source LFOSC is a 32 kHz low power internal oscillator that is used in low power modes HFOSC is a 16 MHz internal oscillator tha...

Page 11: ...UART D2D SPI0 SPI1 CORE PWM TIMER2CLK PCLK HCLK 80MHZ SPLL HFXTAL 16MHz OSC CDPCLK CLKCON1 10 8 I2C1 FLASH ACLK TO LV DIE ADC CDHCLK CLKCON1 2 0 CLKCON5 3 CLKCON5 4 CLKCON5 5 CLKCON5 6 CLKCON5 0 CLKCO...

Page 12: ...HITECTURE OPERATION At power up the processor executes at 80 MHz sourced from the 80 MHz PLL output The clock source for the 80 MHz PLL is the internal 16 MHz oscillator by default User code can selec...

Page 13: ...PLLIE SPLL interrupt enable 0x0 RW 0 SPLL interrupt is not generated 1 SPLL interrupt is generated 12 RESERVED Reserved 0x0 R 11 PLLMUX PLL source selection 0x0 RW 0 internal oscillator is selected HF...

Page 14: ...1 DIV32 Divide by 32 110 DIV64 Divide by 64 111 DIV128 Divide by 128 User Clock Gating Control Register Address 0x40028014 Reset 0x0040 Name CLKCON5 The user clock gating control register CLKCON5 is u...

Page 15: ...enabled Write a 1 to this location to clear it 0x0 RW 0 HF crystal stable signal has not been asserted 1 HF crystal stable signal has been asserted 12 HFXTALSTATUS HF crystal status 0x0 R 0 HF crysta...

Page 16: ...is independent of the power mode settings of the PMU When the ADuCM320 wakes up from any of the low power modes the device return to Mode 0 Power Mode CORE_SLEEP Mode Mode 1 In CORE_SLEEP mode the sy...

Page 17: ...CON 0 Power off the ADC pADI_IDAC0 IDACCON 0x1 Turn off IDAC0 pADI_IDAC1 IDACCON 0x1 Turn off IDAC1 pADI_IDAC2 IDACCON 0x1 Turn off IDAC2 pADI_IDAC3 IDACCON 0x1 Turn off IDAC3 pADI_VDAC0 DACCON 0x100...

Page 18: ...se bits contain the last power mode value entered by user code 0x0 RW Note that to place the Cortex in sleepdeep mode for hibernate the Cortex M3 system control register Address 0xE000ED10 must be con...

Page 19: ...rrival interrupt acceptance and tail chain interrupt entry Immediate execution of a nonmaskable interrupt request for safety critical applications System Features Support for bit band operation and un...

Page 20: ...his feature is transparent to the user and more details are available in the Power Management Unit section It is not recommended to enter a power saving mode while servicing an interrupt However if th...

Page 21: ...rift internal 2 51 V reference source An external reference can also be connected to the ADC_REFP and ADC_REFN pins Programmable ADC update rate from 19 55 kSPS to 1 MSPS Internal digital comparator f...

Page 22: ...DC_REFN pins Single or continuous conversion modes can be initiated in software An external pin alternate function of P2 4 can also be used to generate a repetitive trigger for ADC conversions ADC CIR...

Page 23: ...o the AIN and AIN pins that is AIN AIN The maximum amplitude of the differential signal is therefore VREF to VREF p p 2 VREF This is regardless of the common mode CM The common mode is the average of...

Page 24: ...ither the positive or negative input the bypass switch must be turned off IBUF_PD IBUFCON 3 2 powers up or powers down the ADC input buffer ADC INTERNAL CHANNELS Temperature Sensor Settings The ADuCM3...

Page 25: ...IOVDD 2 input channel is selected If a different ADC sampling rate is required for other channels after the conversion on any of these three channels is completed the ADCCNVC register must be updated...

Page 26: ...e will be sampled with the input buffer enabled It is recommended to split sequences into the following o Sample unbuffered channels together in one sequence o Sample buffered channels in a separate s...

Page 27: ...G 498 Rev C Page 27 of 196 11176 005 BG AFEREFC 0 AFEREFC 1 ADCCON 7 1 2V ADC BUFFER MUX MUX AFEREFC 3 AFEREFC 2 DACxCON 1 0 2 5V GAIN STAGE AVDD BUF_VRFF2 5B ADC CAPP ADC VDAC 2 5V DRIVER Figure 8 Sy...

Page 28: ...ADC11 data and flags Undefined R 0x40086030 ADCDAT12 ADC12 data and flags Undefined R 0x40086034 ADCDAT13 ADC13 data and flags Undefined R 0x40086038 ADCDAT14 ADC14 data and flags Undefined R 0x400860...

Page 29: ...er down 1 power up Must be set to 1 for the ADC to operate normally 6 RESTART_ADC Restart ADC reset analog part of ADC Active high 0x0 W 0 normal ADC operation 1 reset the ADC 5 RESERVED Reserved 0x0...

Page 30: ...ead happens exactly when a subsequent ADC conversion completes on that channel This behavior is valid for all conversion modes single conversions repeated conversions and sequencer conversions Table 1...

Page 31: ...is to measure half of the IOVDD supply voltage 0x1A AVDD_2 use this to measure half of the AVDD supply voltage 0x1B VREFN_PADC connect ADC_REFN to positive input 0x1C to 0x1F reserved ADC Sequencer Co...

Page 32: ...ptions for ADCCMP Bits Bit Name Description Reset Access 17 2 THR Digital compare threshold Value to compare to Channel 4 data 0x0000 RW 1 DIR Select digital comparator direction 0x0 RW 0 ADCTH less t...

Page 33: ...Buf Control Bit Register Address 0x40081400 Reset 0x000F Name IBUFCON Table 21 Bit Descriptions for IBUFCON Bits Bit Name Description Reset Access 15 4 RESERVED Reserved 0x0 RW 3 2 IBUF_PD Power down...

Page 34: ...t the external reference 0x0 RW 0 select internal 2 51 V reference 1 select external 2 51 V reference 2 B2MA_PDB Power down the reference 2 mA output driving Buffer B 0x0 RW 0 power down 2 5 V referen...

Page 35: ...mparator is shared with AIN6 The negative input of the comparator can be set by software to AVDD 2 AIN5 or DAC7 The comparator output is connected to the interrupt logic and can be used as described i...

Page 36: ...criptions for AFECOMP Bits Bit Name Description Reset Access 15 9 RESERVED Reserved 0x0 R 8 EN Powers up and enables comparator 0x0 RW 0 power down and disable comparator 1 power up and enable compara...

Page 37: ...s a 10 nF capacitor between PVDD and its CDAMP pin Figure 9 shows the typical architecture of the IDAC The parallel 11 bit and 5 bit IDACs set the output current The output of these IDACs are summed t...

Page 38: ...tput of quarter scale o If IDAC1 is used in an open loop system or in a set and forget type operation set IDAC1DAT 0x03FE0000 Set IDAC1DAT 27 17 0x1FF Set IDAC1DAT 16 12 0x00 o If IDAC1 is used in a c...

Page 39: ...uce power and therefore to reduce the die temperature Two options to enable shutdown include the following Enable a thermal interrupt by setting either INTSEL 12 or INTSEL 4 If the die temperature exc...

Page 40: ...ls to 1 prevents IDAC3 from updating When the SYNC3 bit of any of the IDAC channels is 0 IDAC3 updates immediately when it is written 0x0 RW 2 SYNC2 IDAC2 sync bit Setting the SYNC2 bits of all IDAC c...

Page 41: ...x0 RW 0 clear IDAC1DAT 1 enable write 6 SHT_EN IDAC1 shutdown enable Enables automatic shutdown in case of overtemperature 0x0 RW 0 disable this function 1 enable this function 5 2 BW IDAC1 bandwidth...

Page 42: ...C channels is 0 IDAC3 updates immediately when it is written 0x0 RW 2 SYNC2 IDAC2 sync bit Setting the SYNC2 bits of all IDAC channels to 1 prevents IDAC2 from updating When the SYNC2 bit of any of th...

Page 43: ...riving a 5 k resistive load to ground is guaranteed through the full transfer function except for Code 0 to Code 100 in 0 to AVDD mode the linearity specification is also not guaranteed for Code 3995...

Page 44: ...DAC2 data register 0x00000000 RW 0x40086410 DAC3DAT DAC3 data register 0x00000000 RW 0x40086414 DAC4DAT DAC4 data register 0x00000000 RW 0x40086418 DAC5DAT DAC5 data register 0x00000000 RW 0x4008641C...

Page 45: ...rved 0x0 RW 4 EN DAC2 enable Must be set to high 0x0 RW 0 DAC disable Clear DAC data immediately 1 DAC enable 3 2 RESERVED Reserved 0x0 RW 1 0 RN DAC2 reference selection These bits set the DAC range...

Page 46: ...ster Address 0x40082414 Reset 0x0100 Name DAC5CON Table 42 Bit Descriptions for DAC5CON Bits Bit Name Description Reset Access 15 9 RESERVED Reserved 0x0 R 8 PD DAC5 power down 0x1 RW 0 DAC5 is powere...

Page 47: ...and output is floating 7 5 RESERVED Reserved 0x0 RW 4 EN DAC7 enable Must be set to high 0x0 RW 0 DAC disable Clear DAC data immediately 1 DAC enable 3 2 RESERVED Reserved 0x0 RW 1 0 RN DAC7 referenc...

Page 48: ...Name Description Reset Access 31 28 RESERVED Reserved Write 0 0x0 R 27 16 DAT DAC4 data 0x0 RW 15 0 RESERVED Reserved Write 0 0x0 R DAC5 Data Register Address 0x40086418 Reset 0x00000000 Name DAC5DAT...

Page 49: ...asks and interrupts are serviced 15 SYSTICK Programmable System tick timer The peripheral interrupts are controlled by the NVIC and are listed in Table 54 All interrupt sources can wake up the device...

Page 50: ...d fault The ADuCM320 implements three priority bits which means that eight priority levels are available as programmable priorities Note that 0 is the default priority for all the programmable priorit...

Page 51: ...he NVIC_SetPriority function can be called For example NVIC_SetPriority TIMER0_IRQn 2 configures the GP Timer 0 interrupt with a priority level of 2 Table 55 lists the registers to enable and disable...

Page 52: ...ending Each bit corresponds to Interrupt 32 to Interrupt 54 in Table 54 RW 0xE000E300 IABR0 IRQ0 to IRQ31 active bits RW 0xE000E304 IABR1 IRQ32 to IRQ54 active bits RW 0xE000E400 IPR0 IRQ0 to IRQ3 pri...

Page 53: ...ppended code also enables the External Interrupt 0 NVIC interrupt source pADI_GP0 GPOE 0xf7 Disable P0 3 output pADI_GP0 GPIE 0x8 Enable input path for P0 3 input pADI_INTERRUPT EI0CFG 0x8 External IR...

Page 54: ...External Interrupt Configuration Register 1 Address 0x40002424 Reset 0x0000 Name EI1CFG Table 58 Bit Descriptions for EI1CFG Bits Bit Name Description Reset Access 15 IRQ7EN External Interrupt 7 enabl...

Page 55: ...edge same as 001 110 rising or falling edge same as 010 111 high level same as 011 External Interrupt Clear Register Address 0x40002430 Reset 0x0000 Name EICLR Table 60 Bit Descriptions for EICLR Bit...

Page 56: ...ailable on the interface between the digital and analog die If a read error occurs for example an error on the ADC result this interrupt is asserted Write ECC interrupt source If the ECC returns an er...

Page 57: ...bit to enable write ECC error interrupt for Interrupt Pin 0 0x0 RW 14 SEL_RDECC_ERR_0 Write 1 to this bit to enable read ECC error interrupt for Interrupt Pin 0 0x0 RW 13 SLE_IDAC_EXTRESLOW_0 Write 1...

Page 58: ...Write data ECC error interrupt status 0x0 R 6 RDECC_ERR Read data ECC error interrupt status 0x0 R 5 IDAC_EXTRESLOW IDAC EXTRESLOW interrupt status 0x0 R 4 IDAC_TSHUT IDAC temperature TSHT interrupt...

Page 59: ...PLA to reset after a software or watchdog reset Before writing to this register 0x2009 must be written to RSTKEY followed by 0x0426 After the two keys are written to RSTKEY RSTCFG must be immediately...

Page 60: ...C Reset Configuration Register Address 0x40002408 Reset 0x0000 Name RSTCFG Table 68 Bit Descriptions for RSTCFG Bits Bit Name Description Reset Access 0 GPIO_PLA_RETAIN GPIO PLA retain their status af...

Page 61: ...master 9 I2C1 slave Tx 10 I2C1 slave Rx 11 I2C1 master 12 ADC 13 Flash The channels are connected to dedicated hardware DMA requests a software trigger is also supported on each channel This configur...

Page 62: ...end pointer 0x04 DST_END_PTR Destination end pointer 0x08 CHNL_CFG Control data configuration 0x0C Reserved Reserved Before the controller can perform a DMA transfer the data structure related to the...

Page 63: ...the value that the DST_END_PTR memory location contains Half Word 00 Reserved 01 Half word 10 Word 11 No increment Address remains set to the value that the DST_END_PTR memory location contains Word...

Page 64: ...m memory with the N_MINUS_1 field changed to reflect the number of transfers yet to be completed When the DMA cycle is complete the CYCLE_CTRL bits are made invalid to indicate the completion of the t...

Page 65: ...the primary or alternate control data structure work exactly the same as a basic DMA transfer Memory Scatter Gather CHNL_CFG 2 0 100 or 101 In memory scatter gather mode the controller must be config...

Page 66: ...ata structure for a basic cycle or the DMA reads an invalid data structure Table 76 lists the fields of the CHNL_CFG memory location for the primary data structure which must be programmed with consta...

Page 67: ...or 0x00000000 RW 0x40010800 DMABSSET DMA channel bytes swap enable set 0x00000000 RW 0x40010804 DMABSCLR DMA channel bytes swap enable clear 0x00000000 W REGISTER DETAILS DMA DMA Status Register Addre...

Page 68: ...x4001000C Reset 0x00000100 Name DMAADBPTR The DMAADBPTR read only register returns the base address of the alternate channel control data structure This register removes the necessity for application...

Page 69: ...R Clear REQ_MASK_SET bits in DMARMSKSET This register enables DMA requests from peripherals by clearing the mask set in DMARMSKSET register Each bit of the register represents the corresponding channe...

Page 70: ...ther transfers Table 87 Bit Descriptions for DMAALTSET Bits Bit Name Description Reset Access 31 14 RESERVED Reserved Undefined 0x0 R 13 0 CHPRIALTSET Control structure status select alt struct Return...

Page 71: ...efault priority level The DMAPRICLR write only register enables the user to configure a DMA channel to use the default priority level Each bit of the register represents the corresponding channel numb...

Page 72: ...s enabled When written Bit C 0 no effect Use the DMABSCLR register to disable byte swap on Channel C Bit C 1 enables byte swap on Channel C DMA Channel Bytes Swap Enable Clear Register Address 0x40010...

Page 73: ...pace and information space 8 bit ECC 1 bit ECC error correction 1 bit ECC errors and 2 bit or greater ECC errors can be configured to generate a flash ECC interrupt or a system exception FLASH CONTROL...

Page 74: ...ion Y in ASCII code and A indicates minor revision A There are also hardware registers that identify the version of each silicon die For more information see the Silicon Identification section ADDRESS...

Page 75: ...flash operations are completed Customers must have a single function that performs all the writes to flash needed by the customer application It must only be possible to call this function once until...

Page 76: ...end address is reached A block can be a single page or multiple pages The hardware assumes that the signature for a block is stored in the upper four bytes of the most significant page of a block the...

Page 77: ...est address for i2 31 i2 0 i2 MSB first iCrc 1 Left shift if aiData i1 1 i2 iCrc 0x00800063 Polynomial if iCrc 1 24 iCrc 0x00800063 return iCrc 0x00ffffff Return 24 bits int FeeSign unsigned long ulSt...

Page 78: ...occurs the address at which the error is detected is available for the user If a system exception is configured the BFAR register contains the address for which ECC error is detected ECC Error During...

Page 79: ...onse to an interrupt is required during an erase or program cycle the interrupt service routine and the interrupt vector table must be moved to SRAM or must be in the other flash block for the duratio...

Page 80: ...ashData 64 pADI_DMA DMAENSET 0x2000 pADI_FEE FEEFLADR uiAdr pADI_FEE FEEKEY 0xF123F456 pADI_FEE FEECON1 FEECON1_KHDMA_EN Enable Flash DMA mode void FLASHDMAWRITE unsigned char pucTX_DMA unsigned int i...

Page 81: ...on Time Typical Comment Write 64 bit location 75 s Mass erase one flash block 18 ms Page erase one page 18 ms Sign Flash 0 Flash 1 information space 33 s 512 cycles 2 kB Sign Flash 0 Flash 1 user spac...

Page 82: ...x00000000 R 0x400180C0 CACHESTAT Cache status register 0x2 R 0x400180C4 CACHESETUP Cache setup register 0x2 RW 0x400180C8 CACHEKEY Cache key register 0x0 W REGISTER DETAILS FLASH CONTROLLER Status Reg...

Page 83: ...ead 1 bit error and 2 bit errors are detected in Flash 1 10 9 ECCREADERRFLSH0 ECC errors during read of Flash 0 if interrupt is enabled 0x0 RC Bits Name Description 00 NOERR No error Successful read f...

Page 84: ...able 1 IWRALCOMP Write almost complete interrupt enable Returns 0 when read 0x0 RW 0 disable 1 enable 0 IENCMD Command complete interrupt enable When set an interrupt is generated when a command or fl...

Page 85: ...stop a write that may be in progress If a write or erase is aborted the flash timing is violated and it is not possible to determine if the write or erase completed successfully To enable this operat...

Page 86: ...r FEEPRO0 Bits Bit Name Description Reset Access 31 0 WRPROT0 Write protection for Flash 0 32 bits Each bit corresponds to a 4 kB flash section Writing 0 to a bit protects the corresponding section of...

Page 87: ...TAG access Write Abort Address Register Address 0x40018040 Reset 0x0000000X Name FEEWRADDRA Table 109 Bit Descriptions for FEEWRADDRA Bits Bit Name Description Reset Access 31 0 WRABORTADDR If a write...

Page 88: ...ption 00 Exception is not generated if an ECC error occurs while reading from flash 01 Exception enable d only if a 2 bit error is detected during a read from Flash 0 or Flash 1 10 Exception enable d...

Page 89: ...every AHB access hit from write buffer is not checked 0x0 RW 18 DLOCK If this bit is set D cache contents are locked Any new misses are not replaced in D Cache This bit is cleared when CACHESETUP 16 i...

Page 90: ...CHIPID Digital die ID 0x0561 R 0x40082C30 LVID Low voltage die ID 0x0073 R DIGITAL DIE ID REGISTER Address 0x40002024 Reset 0x0561 Name CHIPID Table 119 Bit Descriptions for CHIPID Bits Bit Name Desc...

Page 91: ...nctional over the full supply range IOVDD 3 1 V to 3 6 V maximum and the logic input voltages are specified as percentages of the supply as follows VINL 0 25 IOVDD max VINH 0 58 IOVDD min The absolute...

Page 92: ...devices with typical performance shown in Figure 17 and Figure 18 If a pin is configured as an output the internal pull up pull down is disabled even in open drain mode 10 20 30 40 50 ROUT 0 0 5 1 0 1...

Page 93: ...in open drain mode it is possible to configure the GPIOs in pseudo open drain mode by setting the corresponding bits of GPxOUT and GPxODE to 0b0 and the corresponding bit of GPxPUL to 0b1 To change be...

Page 94: ...5 14 0x1 PLAO 5 GP0CON 15 14 0x3 GP1 GP1CON Controls These Bits P1 0 GPIO GP1CON 1 0 0x0 UART SIN GP1CON 1 0 0x1 ECLKIN GP1CON 1 0 0x2 PLAI 4 GP1CON 1 0 0x3 P1 1 GPI0 GP1CON 3 2 0x0 UART SOUT GP1CON 3...

Page 95: ...4 0x0 VDAC2 GP3CON 15 14 0x1 PLAO 29 GP3CON 15 14 0x3 GP4 GP4CON Controls These Bits P4 2 GPIO GP4CON 5 4 0x0 AIN8 GP4CON 5 4 0x1 P4 3 GPIO GP4CON 7 6 0x0 AIN9 GP4CON 7 6 0x1 P4 4 GPIO GP4CON 9 8 0x0...

Page 96: ...0088 GP2PUL GPIO Port 2 pull up enable 0x08 RW 0x4002008C GP2IE GPIO Port 2 input path enable 0xFF RW 0x40020090 GP2IN GPIO Port 2 registered data input 0xXX R 0x40020094 GP2OUT GPIO Port 2 data outpu...

Page 97: ...N Table 123 Bit Descriptions for GP0CON GP1CON GP2CON GP3CON GP4CON and GP5CON Bits Bit Name Description Reset Access 15 14 CON7 Configuration bits for Port x 7 See Table 121 1 See Table 122 RW 13 12...

Page 98: ...IO Port Input Path Enable Registers Address 0x4002000C Reset 0xFF Name GP0IE Address 0x4002004C Reset 0xFF Name GP1IE Address 0x4002008C Reset 0xFF Name GP2IE Address 0x400200CC Reset 0xFF Name GP3IE...

Page 99: ...ddress 0x400200D8 Reset 0x00 Name GP3SET Address 0x40020118 Reset 0x00 Name GP4SET Address 0x40020258 Reset 0x00 Name GP5SET Table 130 Bit Descriptions for GP0SET GP1SET GP2SET GP3SET GP4SET and GP5SE...

Page 100: ...s addresses should not be used for this register See Table 122 W 0 clearing this bit has not effect 1 set by user code to invert the corresponding GPIO pin GPIO Port Open Drain Enable Registers Addres...

Page 101: ...d the bus becomes idle Figure 19 shows a typical I2 C transfer A master device can be configured to generate the serial clock The frequency is programmed by the user in the serial clock divisor regist...

Page 102: ...nce is generally used in cases where the first data sent to the part sets up the register address to be read from MSB START BIT SCL ACK BIT ACK BIT SLAVE ADDRESS SDA MSB LSB LSB DATA 1 1 7 8 8 9 9 2 3...

Page 103: ...s byte during a write sequence Slave Transfer Initiation If the slave enable bit I2CxSCON 0 SLVEN is set a slave transfer sequence is monitored for the device address in Register I2CxID0 Register I2Cx...

Page 104: ...rface master and slave is reset The general call interrupt status asserts and the general call ID bits GCID I2CxSSTA 9 8 are 0x1 User code should take corrective action to reset the entire system or s...

Page 105: ...slave address device ID register 0x0000 RW 0x40003048 I2C0ID3 4th slave address device ID register 0x0000 RW 0x4000304C I2C0FSTA Master and slave FIFO status register 0x0000 RW 0x40003050 I2C0SHCON Ma...

Page 106: ...e a Transaction completion Tx underflow Rx overflow or a NACK by the slave This is different from the TCOMP as this bit is not asserted when the STOP condition occurs due to any other I2C0 master No i...

Page 107: ...er allows access to the receive data FIFO The FIFO can hold 2 bytes 0x0 R Master Transmit Data Register Address 0x4000300C Reset 0x0000 Name I2C0MTX Table 139 Bit Descriptions for I2C0MTX Bits Bit Nam...

Page 108: ...Reset Access 15 8 RESERVED Reserved 0x0 R 7 0 ADR1 Address byte 1 This register is only required when addressing a slave with a 10 bit address Bit 7 to Bit 0 of ADR1 are programmed with the lower 8 b...

Page 109: ...ection bit SCL clock pulse 0x0 RW 4 GCSBCLR General call status bit clear The general call status and general call ID bits are cleared when a 1 is written to this bit The general call status and gener...

Page 110: ...s written to 1 These status bits are not cleared by a general call reset 0x0 R 00 no general call 01 general call reset and program address 10 general call program address 11 general call matching alt...

Page 111: ...the slave Tx FIFO is empty 0x1 RW If EARLYTXR 1 TXFSEREQ is set when the direction bit for a transfer is received high It asserts on the positive edge of the SCL clock pulse that clocks in the directi...

Page 112: ...is don t care See the ADR10EN bit in the slave control register to see how this register is programmed with a 10 bit address 0x0 RW Third Slave Address Device ID Register Address 0x40003044 Reset 0x00...

Page 113: ...1 1 bytes in the FIFO 10 2 bytes in the FIFO 11 reserved 5 4 MTXFSTA Master transmit FIFO status The status is a count of the number of bytes in a FIFO 0x0 R 00 FIFO empty 01 1 bytes in the FIFO 10 2...

Page 114: ...slave address device ID register 0x0000 RW 0x40003448 I2C1ID3 4th slave address device ID register 0x0000 RW 0x4000344C I2C1FSTA Master and slave FIFO status register 0x0000 RW 0x40003450 I2C1SHCON Ma...

Page 115: ...transaction completion Tx underflow Rx overflow or a NACK by the slave This is different from the TCOMP as this bit is not asserted when the STOP condition occurs due to any other I2 C master No inter...

Page 116: ...ster allows access to the receive data FIFO The FIFO can hold 2 bytes 0x0 R Master Transmit Data Register Address 0x4000340C Reset 0x0000 Name I2C1MTX Table 160 Bit Descriptions for I2C1MTX Bits Bit N...

Page 117: ...eset Access 15 8 RESERVED Reserved 0x0 R 7 0 ADR1 Address byte 1 This register is only required when addressing a slave with a 10 bit address Bit 7 to Bit 0 of ADR1 are programmed with the lower 8 bit...

Page 118: ...e direction bit SCL clock pulse 0x0 RW 4 GCSBCLR General call status bit clear The general call status and general call ID bits are cleared when a 1 is written to this bit The general call status and...

Page 119: ...is written to 1 These status bits are not cleared by a general call reset 0x0 R 00 no general call 01 general call reset and program address 10 general call program address 11 general call matching a...

Page 120: ...the slave Tx FIFO is empty 0x1 RW If EARLYTXR 1 TXFSEREQ is set when the direction bit for a transfer is received high It asserts on the positive edge of the SCL clock pulse that clocks in the directi...

Page 121: ...is don t care See the ADR10EN bit in the slave control register to see how this register is programmed with a 10 bit address 0x0 RW Third Slave Address Device ID Register Address 0x40003444 Reset 0x00...

Page 122: ...1 1 bytes in the FIFO 10 2 bytes in the FIFO 11 reserved 5 4 MTXFSTA Master transmit FIFO status The status is a count of the number of bytes in a FIFO 0x0 R 00 FIFO empty 01 1 bytes in the FIFO 10 2...

Page 123: ...I pins should be disabled via the GPxPUL registers when using the SPI MISO Master In Slave Out Pin The MISO pin is configured as an input line in master mode and an output line in slave mode The MISO...

Page 124: ...FO Similarly when the user wants to only receive data and does not want to write data to the Tx FIFO SPIxCON 13 can be set to avoid receiving underrun interrupts from the Tx FIFO Tx Initiated Transfer...

Page 125: ...if there is no space left in the FIFO When the RXOF is set the contents of the SPI Rx FIFO are undefined and its contents should be discarded by user code Full Duplex Operation Simultaneous reads writ...

Page 126: ...SPIxCON 6 is cleared the Rx FIFO status causes the interrupt The SPIxCON 15 14 bits control when the interrupt occurs The interrupt is cleared by a read of SPIxSTA The status of this interrupt can be...

Page 127: ...pt is generated To avoid generating overflow interrupts the Rx FIFO flush bit should be set or the SPI interrupt should be disabled in the NVIC If only the DMA receive request SPIxDMA 2 is enabled the...

Page 128: ...x0000 RW 0x4002C018 SPI0CNT Transfer byte count register 0x0000 RW REGISTER DETAILS SPI0 Status Register Address 0x4002C000 Reset 0x0000 Name SPI0STA Table 179 Bit Descriptions for SPI0STA Bits Bit Na...

Page 129: ...derflow 0x0 RC 0 cleared to 0 when the SPI0STA register is read 1 set to 1 when a transmit is initiated without any valid data in the Tx FIFO This bit generates an interrupt except when TFLUSH is set...

Page 130: ...nterrupt occurs when 1 or more bytes have been received into the FIFO 01 Tx interrupt occurs when 2 bytes has been transferred Rx interrupt occurs when 2 or more bytes have been received into the FIFO...

Page 131: ...FO 1 set this bit to transmit 0x00 when there is no valid data in the Tx FIFO 6 TIM SPI transfer and interrupt mode 0x0 RW 0 cleared by user to initiate transfer with a read of the SPI0RX register Int...

Page 132: ...that a master mode transfer terminates at the proper time and that 16 bit DMA transfers are byte padded or discarded as required to match odd transfer counts Reset by clearing SPI0CON 0 or if SPI0CNT...

Page 133: ...e FIFO 100 4 valid bytes in the FIFO 7 RXOF SPI Rx FIFO overflow 0x0 RC 0 cleared to 0 when the SPI1STA register is read 1 set to 1 when the Rx FIFO was already full when new data was loaded to the FI...

Page 134: ...nable interrupt on every CS edge in CONT mode If this bit is set and the SPI module is in continuous mode any edge on CS generates an interrupt and the corresponding status bits CSRSG CSFLG is asserte...

Page 135: ...ired If this bit is set all incoming data is ignored and no interrupts are generated If set and TIM 0 a read of the Rx FIFO initiates a transfer 11 CON Continuous transfer enable 0x0 RW 0 DIS Cleared...

Page 136: ...Name Description Reset Access 15 3 RESERVED Reserved 0x0 R 2 IENRXDMA Enable receive DMA request 0x0 RW 0 disable RX DMA interrupt 1 enable RX DMA interrupt 1 IENTXDMA Enable transmit DMA request 0x0...

Page 137: ...pended as required UCLK CDPCLK 2 16 COMDIV M N 2048 All data words begin with a low going start bit The transfer of COMTX to the TSR causes the transmit register empty status flag to be set The receiv...

Page 138: ...oth Rx and Tx interrupts The COMIIR register must be read by software to determine the cause of the interrupt Note that in DMA mode the break interrupt is not available In I O mode when receiving the...

Page 139: ...IRQ DMA_UART_TX_IRQn UART Tx DMA interrupt sources pADI_UART COMLCR COMLCR_WLS_8BITS COMLCR_STOP 8 data bits 1 stop bit pADI_UART COMDIV 0x41 Set UART baud rate pADI_UART COMFBR COMFBR_FBEN_EN 0x803 D...

Page 140: ...ned int pADI_UART COMTX Desc ctrlCfg Bits n_minus_1 iNumRX 0x1 Desc ctrlCfg Bits src_inc DMA_SRCINC_BYTE Desc ctrlCfg Bits dst_inc DMA_DSTINC_NO Dma_GetDescriptor UARTTX_C Desc UART DMA Tx IRQ handler...

Page 141: ...0x0 R 7 0 THR Transmit holding register This is an 8 bit register to which the user can write the data to be sent If the ETBEI bit is set in the COMIEN register an interrupt is generated when COMTX i...

Page 142: ...is used 0x0 RC 00 modem status interrupt read COMMSR to clear 01 transmit buffer empty interrupt write to COMTX or read COMIIR to clear 10 receive buffer full interrupt read COMRX to clear 11 receive...

Page 143: ...is 6 WLS 01 7 WLS 10 or 8 bits WLS 11 1 0 WLS Word length select Selects the number of bits per transmission 0x0 RW 00 5 bits 01 6 bits 10 7 bits 11 8 bits Modem Control Register Address 0x40005010 R...

Page 144: ...d 1 an invalid stop bit was detected on a received word 2 PE Parity error If set this bit self clears after COMLSR is read 0x0 RC 0 No parity error was detected 1 A parity error occurred on a received...

Page 145: ...ster is an 8 bit register used to store intermediate results The value contained in the scratch register does not affect UART functionality or performance Only 8 bits of this register are implemented...

Page 146: ...BLOCK X ELEMENT 7 OUTPUT ELEMENT n WHERE BLOCK X IS BLOCK 0 OR BLOCK 1 PLA_ELEMn IS THE MMR CONTROLING ELEMENT n n 0 TO 15 NC NO CONNECTION 11176 124 Figure 25 PLA Element Block 0 and Block 1 4 2 0 A...

Page 147: ...plete list of the possible connections is given in Table 207 and Table 208 The four blocks can be interconnected as follows Output of Element 7 Block 0 Element 7 can be fed back to the Input 0 of Mux...

Page 148: ...n 16 BLOCK 1 ELEMENT 7 ELEMENT 15 4 BLOCK 3 ELEMENT 7 ELEMENT 31 2 4 BLOCK 0 ELEMENT 0 ELEMENT 0 0 4 BLOCK 0 ELEMENT 7 ELEMENT 7 4 BLOCK 1 ELEMENT 0 ELEMENT 8 4 0 BLOCK 2 ELEMENT 7 ELEMENT 23 2 4 0 B...

Page 149: ...ement 18 Element 26 Element 26 10 Element 4 Element 4 Element 12 Element 12 Element 20 Element 20 Element 28 Element 28 11 Element 6 Element 6 Element 14 Element 14 Element 22 Element 22 Element 30 El...

Page 150: ...Descriptions for PLA_ELEMn Bits Bit Name Description Reset Access 15 11 RESERVED Not used 0x00 Reserved 10 9 MUX0 Even element feedback selection in respective block 0x0 RW 00 feedback from Element 0...

Page 151: ...00 MOSC 16 MHz 101 Timer 0 110 Timer 2 111 KOSC 32 kHz 11 RESERVED Not used 0x0 Reserved 10 8 BLOCK2 Clock select for Block 2 0x0 RW 000 GPIO clock on P0 3 001 GPIO clock on P1 1 010 GPIO clock on P2...

Page 152: ...0x0 Reserved 12 IRQ3_EN IRQ3 enable 0x0 RW 0 disable IRQ3 interrupt 1 enable IRQ3 interrupt 11 8 IRQ3_SRC IRQ3 source select Elements 16 to Element 31 Element number corresponds to 4 bit value 16 for...

Page 153: ...ster Address 0x4000589C Reset 0x0000 Name PLA_DOUT1 Table 218 Bit Descriptions for PLA_DOUT1 Bits Bit Name Description Reset Access 15 0 DOUT Output bit from Element 31 to Element 16 0x0 R Write Lock...

Page 154: ...lock sources PCLK HCLK 32 kHz internal oscillator LFOSC 16 MHz external crystal HFXTAL or internal 16 MHz oscillator HFOSC depending on the value in CLKCON0 11 The clock sources can be scaled down usi...

Page 155: ...set to count down Interval TxLD Prescaler Source Clock For example if TxLD 0x100 prescaler 4 and clock source UCLK the interval is 12 8 s where UCLK 80 MHz If the timer is set to count up Interval Fu...

Page 156: ...tten until a 1 is written to TxCLRI 1 Table 220 Capture Event Function Event Select Bits TxCON EVENT TxCON 11 8 T0 Capture Source T1 Capture Source T2 Capture Source 0000 Wake up timer External Interr...

Page 157: ...nter value Value delayed two PCLK cycles due to clock synchronizers 0x0 R Control Register Address 0x40000008 Reset 0x000A Name T0CON Table 224 Bit Descriptions for T0CON Bits Bit Name Description Res...

Page 158: ...ock If CLK Source 0 PCLK or CLK Source 1 HCLK is selected then Prescaler Value 0 means divide by 4 else it means divide by 1 0x2 RW 00 source clock 1 or 4 01 source clock 16 10 source clock 256 11 sou...

Page 159: ...ock domain 6 BUSY Timer busy This bit informs the user that a write to T0CON is still crossing into the timer clock domain This bit should be checked after writing T0CON and further writes should be s...

Page 160: ...counter value Value delayed two PCLK cycles due to clock synchronizers 0x0 R Control Register Address 0x40000408 Reset 0x000A Name T1CON Table 231 Bit Descriptions for T1CON Bits Bit Name Description...

Page 161: ...ock If CLK Source 0 PCLK or CLK Source 1 HCLK is selected then Prescaler Value 0 means divide by 4 else it means divide by 1 0x2 RW 00 source clock 1 or 4 01 source clock 16 10 source clock 256 11 sou...

Page 162: ...ock domain 6 BUSY Timer busy This bit informs the user that a write to T1CON is still crossing into the timer clock domain This bit should be checked after writing T1CON and further writes should be s...

Page 163: ...counter value Value delayed two PCLK cycles due to clock synchronizers 0x0 R Control Register Address 0x40000808 Reset 0x000A Name T2CON Table 238 Bit Descriptions for T2CON Bits Bit Name Description...

Page 164: ...ock If CLK Source 0 PCLK or CLK Source 1 HCLK is selected then Prescaler Value 0 means divide by 4 else it means divide by 1 0x2 RW 00 source clock 1 or 4 01 source clock 16 10 source clock 256 11 sou...

Page 165: ...ock domain 6 BUSY Timer Busy This bit informs the user that a write to T2CON is still crossing into the timer clock domain This bit should be checked after writing T2CON and further writes should be s...

Page 166: ...og timer is a 16 bit count down timer with a programmable prescaler The prescaler is selectable and can divide LFOSC by a factor of 1 16 256 or 4096 WATCHDOG TIMER OPERATION The watchdog timer is enab...

Page 167: ...1 PERIODIC Set by user to operate in periodic mode default 5 ENABLE Timer enable 0x1 RW 0 DIS Cleared by user to disable the timer 1 EN Set by user to enable the timer default 4 RESERVED Reserved 0x0...

Page 168: ...ed 0x0 R 4 LOCK Lock status bit Set automatically in hardware if T3CON 5 has been set by user code Cleared by default and until user code sets T3CON 5 0x0 R 3 CON T3CON write sync in progress 0x0 R 0...

Page 169: ...x00000000 In periodic mode the timer counts from 0x00000000 to T4WUFD T4WUFD0 and T4WUFD1 In addition the wake up timer has four specific time fields to compare with the wake up counter T4WUFA T4WUFB...

Page 170: ...val value set STOPINC T4CON 11 1 while the timer is running The new T4INC value takes effect after the next Wake Up Field A interrupt If the user is writing to this register while the timer is enabled...

Page 171: ...32 kHz clock cycles for the interrupt clear to take effect when the 32 kHz internal oscillator is used Ensure that the register write has fully completed before returning from the interrupt handler Us...

Page 172: ...0x0000 R REGISTER DETAILS WAKE UP TIMER Current Count Value Least Significant 16 Bits Register Address 0x40002500 Reset 0x0000 Name T4VAL0 Table 249 Bit Descriptions for T4VAL0 Bits Bit Name Descript...

Page 173: ...ce clock 16 10 PREDIV256 source clock 256 11 PREDIV32768 source clock 32 768 12 Bit Interval for Wake Up Field A Register Address 0x4000250C Reset 0x00C8 Name T4INC Table 252 Bit Descriptions for T4IN...

Page 174: ...over Cleared by user to disable the roll over interrupt default 0x0 RW 3 WUFD T4WUFD interrupt enable Set by user code to generate an interrupt when T4VAL reaches T4WUFD Cleared by user code to disab...

Page 175: ...r interrupt has occurred Cleared automatically after a write to the corresponding bit in T4CLRI 0x0 R Clear Interrupt Register Address 0x40002530 Reset 0x0000 Name T4CLRI Table 261 Bit Descriptions fo...

Page 176: ...dard mode the user has control over the period of each pair of outputs and over the duty cycle of each individual output In the event of external fault conditions a falling edge on the PWMTRIP pin pro...

Page 177: ...GREATER THAN OR EQUAL TO THE HIGH PERIOD OF PWM1 Figure 32 Waveform of PWM Channel Pair in Standard Mode Table 265 lists equations for the period and duration for both the outputs of a PWM channel Tab...

Page 178: ...s register PWM1COM2 PWM3 output goes low when the PWM timer reaches the count value stored in this register PWM1LEN PWM3 output goes high when the PWM timer reaches the count value stored in this regi...

Page 179: ...trip function is enabled TRIPEN PWMCON1 6 and the PWM trip input signal goes low falling edge the PWM peripheral disables itself PWMCON0 0 0 It also generates the PWM trip interrupt The interrupt is...

Page 180: ...0x40024040 PWM3COM0 Compare Register 0 for PWM6 and PWM7 0x0000 RW 0x40024044 PWM3COM1 Compare Register 1 for PWM6 and PWM7 0x0000 RW 0x40024048 PWM3COM2 Compare Register 2 for PWM6 and PWM7 0x0000 R...

Page 181: ...ptions for PWMCON1 Bits Bit Name Description Reset Access 15 7 RESERVED Reserved Return 0 on reads 0x00 Reserved 6 TRIP_EN Set to enable PWM trip functionality 0x0 RW 5 0 RESERVED Reserved 0x0 Reserve...

Page 182: ...Compare Register 0 data 0x0 RW Compare Register 1 for PWM2 and PWM3 Address 0x40024024 Reset 0x0000 Name PWM1COM1 Table 277 Bit Descriptions for PWM1COM1 Bits Bit Name Description Reset Access 15 0 CO...

Page 183: ...s 15 0 LEN Period value 0x0 RW Compare Register 0 for PWM6 and PWM7 Address 0x40024040 Reset 0x0000 Name PWM3COM0 Table 284 Bit Descriptions for PWM3COM0 Bits Bit Name Description Reset Access 15 0 CO...

Page 184: ...STA CFP MDIO INTERFACE REGISTERS FOR REGISTER SET CFP IEEE 802 3 CFP MODULE INTERNAL BUS NONVOLATILE MEMORY NVM DIGITAL DIAGNOSTIC MONITORING DDM MDIO BUS 2 3 OR 5 PORT ADD BUS MMD CPU CONTROL LOGIC 1...

Page 185: ...crement the address in the MDADR register PHYADR Physical Address This address is five bits allowing 32 unique addresses The PHYADR is set either by 5 pins or by software DEVAD Device Address This add...

Page 186: ...1 ACTIVE NVR DATA 8kB IMAGE A INACTIVE PROGRAM 120kB IMAGE B NOT USED KEY2 K2B1 KEY1 K1B1 NOT USED 0x3FFFF 0x3FFE8 0x3E000 0x3DFE8 0x3DFE0 0x20000 FLASH BLOCK 0 ACTIVE FEECON1 3 0 0x1FFFF 0x0 FLASH 1...

Page 187: ...modes can be entered only via a reset Every reset causes the kernel to run and the kernel chooses the appropriate mode according to keys in the program images Each program image contains two keys For...

Page 188: ...st be left erased as 0xFFs After the download the part must be reset to allow a trial run to occur Typical Sequence A typical sequence is shown in Table 290 On a new device the initial code can be dow...

Page 189: ...0 Y Y N K2B1 0 Y CHANGE TO USER CODE SWITCH TO FLASH 1 KEY1 KEY1 KEY2 0 TRIAL RUN TRIAL OK N Y Y N WRITE KEY2 0 FLASH OTHER BLOCK KEY2 0xFFs K1 K1 1 ERROR NORMAL RUN KERNEL CODE HARDWARE USER CODE K2...

Page 190: ...lash Block 1 at 0x3DFE8 Key1 Key used to identify latest revision in active flash block at 0x1DFE0 Key2 Key used for trial runs in active flash block at 0x1DFE8 Key1 Key1 for the other flash block at...

Page 191: ...ddress 0x40005C00 Reset 0x0000 Name MDCON Control for MDIO block Table 293 Bit Descriptions for MDCON Bits Bit Name Description Reset Access 15 3 RESERVED Reserved 0x0 R 2 MD_DRV 0 MDIO drive open dra...

Page 192: ...DPHY Bits Bit Name Description Reset Access 15 RESERVED Reserved 0x0 R 14 10 MD_DEVADD Expected DEVADD Normally 01 0x1 RW 9 5 MD_PHYSEL Selects expected PHYADR bits For each of the 5 bits 0x0 RW 0 set...

Page 193: ...s requested when MD_DEVN becomes active 0x0 RW 4 MD_DEVMI If set interrupt is requested when MD_DEVM becomes active 0x0 RW 3 MD_RDFI If set interrupt is requested when MD_RDF becomes active 0x0 RW 2 M...

Page 194: ...ible to the pins VDD1 should either have a separate power supply or should be filtered from the other digital supply using an inductor bead and a resistor The same applies to the AVDD supply Decouplin...

Page 195: ...MP2 CDAMP1 CDAMP0 PVDD3 PVDD2 PVDD1 PVDD0 XTALO XTALI RESET RESET A4 A8 B4 B8 B5 VDD1 CDAMP3 B7 SWCLK P1 0 SIN P2 3 BM K1 IOVDD1 IOVDD3 IOVDD2 VDD1 DVDD_1V8 DVDD_2V5 DGND1 DGND2 IOGND1 IOGND2 IOGND3 1...

Page 196: ...and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore prope...

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