UG-498
ADuCM320 Hardware Reference Manual
Rev. C | Page 18 of 196
REGISTER SUMMARY: POWER MANAGEMENT UNIT
Table 9. Power Management Register Summary
Address
Name
Description
Reset
RW
0x40002400
PWRMOD
Power modes
0x0000
RW
0x40002404
PWRKEY
Key protection for PWRMOD
0x0000
RW
REGISTER DETAILS: POWER MANAGEMENT UNIT
Power Modes Register
Address: 0x40002400, Reset: 0x0000, Name: PWRMOD
Table 10. Bit Descriptions for PWRMOD
Bits
Bit Name
Description
Reset
Access
[14:2]
RESERVED
Reserved. These bits should be written 0 by user code.
0x0
R
[1:0]
PWRMOD
Power modes control bits. When read, these bits contain the last power
mode value entered by user code.
0x0
RW
Note that, to place the Cortex in sleepdeep mode for hibernate, the
Cortex-M3 system control register (Address 0xE000ED10) must be
configured to 0x4 or 0x06.
00: active mode
01: CORE_SLEEP mode
10: SYS_SLEEP mode
11: hibernate mode
Key Protection for PWRMOD Register
Address: 0x40002404, Reset: 0x0000, Name: PWRKEY
Table 11. Bit Descriptions for PWRKEY
Bits
Bit Name
Description
Reset
Access
[15:0]
PWRKEY
Power control key register. The PWRMOD register is key-protected. Two
writes to the key are necessary to change the value in the PWRMOD
register: first 0x4859, then 0xF27B. The PWRMOD register should then be
written. A write to any other register before writing to PWRMOD returns
the protection to the lock state.
0x0
RW