ADuCM320 Hardware Reference Manual
UG-498
Rev. C | Page 7 of 196
INTRODUCTION TO THE
The
is a fully integrated single-package device that incorporates high performance analog peripherals together with digital
peripherals controlled by an 80 MHz ARM Cortex™-M3 processor and integral flash for code and data.
The ADC on the
provides 14-bit, 1 MSPS data acquisition on up to 16 input pins that can be programmed to be single-ended
or differential. Additionally, chip temperature and supply voltages can be measured. The ADC input voltage is 0 V to V
REF
. A sequencer is
provided that allows a user selected set of ADC channels to be measured in sequence without software involvement during the sequence.
The sequence can optionally auto repeat at a user-selectable rate.
Up to eight voltage DACs are provided with output ranges programmable to one of two voltage ranges. The DAC outputs have an
enhanced feature of being able to retain their output voltage during a watchdog or software reset sequence. On the
, four
current output DAC sources are provided. The output currents are programmable with ranges of 0 mA to 150 mA. A low drift band gap
reference and a voltage comparator complete the analog input peripheral set.
The microcontroller core is a low power ARM Cortex-M3 processor, a 32-bit RISC machine that offers up to 100 MIPS peak
performance. Also integrated on chip are two 128 kB Flash/EE memory and 32 kB of SRAM. The flash comprises two separate 128 kB
blocks supporting execution from one flash block and simultaneous writing/erasing of the other flash block.
The
operates from an on-chip oscillator or a 16 MHz external crystal and a PLL at 80 MHz. This clock can optionally be
divided down to reduce current consumption. Additional low power modes can be set via software. In the normal operating mode, the
digital core consumes about 300 µA/MHz.
The device includes an MDIO interface capable of operating at up to 4 MHz. The capability to simultaneously execute from one flash
block and write/erase the other flash block makes the
ideal for 40 G/100 G optical applications. User programming is eased
by receiving interrupts after PHYADR, DEVADD, and end of frame and by having PHYADR and DEVADD hardware comparators. In
addition, the nonerasable kernel code plus flags in user flash can provide assistance to allow user code to robustly switch between the two
blocks of user flash code and data spaces as required for MDIO.
The
also integrates a range of on-chip peripherals that can be configured via software control as required in the application.
These peripherals include one UART, two I
2
Cs, two SPI serial I/O communication controllers, GPIO, 32-element programmable logic
array, three general-purpose timers, one wake-up timer, and one system watchdog timer. In addition, 16-bit PWMs with seven output
signals are provided.
GPIO pins on the device power up in input mode. In output mode, the software can choose between open-drain mode and push-pull
mode. The outputs can drive at least 4 mA. The pull-ups can be disabled and enabled in software. In GPIO mode, the inputs can always
be enabled to monitor the pins. The GPIO pins can also be programmed to handle digital or analog peripheral signals, in which case the
pin characteristics are matched to the specific requirement.
A large support ecosystem is available for the ARM Cortex-M3 processor, which eases product development of the
. Access is
via the JTAG serial wire interface. On-chip factory firmware supports in-circuit serial download via MDIO. These features are incorporated in a
low cost QuickStart development system supporting this precision analog microcontroller family.
MAIN FEATURES OF
ADC
•
Multichannel, 14-bit, 1 MSPS SAR ADC
•
Low drift on-chip voltage reference
DACs
•
Eight voltage output DACs
o
VDACs are 12-bit monotonic
•
Four current output DACs
o
Current DACs are 12-bit monotonic
•
Low drift, on-chip 2.5 V voltage reference source
o
Two buffered reference outputs
